JP2001291397A - Semiconductor integrated device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relieve a bit line and a word line as a nondefective memory cell even if defect is caused in them without incorporating previously a memory cell for relieving when flash memory size has margin for code size of a program. SOLUTION: Information of a defective bit line and a defective word line is stored previously so that a row decoder and a column decoder are set so that the defective bit line or the defective word line can correspond to continuous space on a memory map. Based on information all or one part of address signals inputted to the row decoder of the address signal can be exchanged with all or one part of address signals inputted to the column decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device having a memory cell array composed of nonvolatile memory cells such as flash memories, and more particularly to a semiconductor integrated device capable of relieving a defect in the memory cell array. Things.

[0002]

2. Description of the Related Art In recent years, it has been difficult to improve the yield due to the tendency to increase the memory capacity of flash memories, miniaturization of processes, and the complexity of manufacturing steps.

FIG. 6 is a diagram showing address decoding of a conventional flash memory. An address decoding method of the flash memory will be described below.

Reference numeral 51 denotes an address signal, 52 denotes a row decoder, 53 denotes a column decoder, 54 denotes a flash memory cell, 55 denotes a word line, and 56 denotes a bit line.

FIG. 7 is a diagram showing the correspondence between address signals and decoders. As shown in FIG.
1, address signals A14 to A10 and address signal A
4 to A0 are input to the row decoder 52, and the word lines 55 corresponding to the address signals A14 to A10 and the address signals A4 to A0 are selected. Next, of the input address signals 51, the address signals A9 to A5 are input to the column decoder 53, the bit lines 56 corresponding to the address signals A9 to A5 are selected, and the flash memory cells 54 corresponding to the address signal 51 are selected. To be elected.

FIG. 8 is a memory map of a conventional flash memory.

Reference numeral 61 denotes a defective area which cannot be used due to a defective bit line or a defective word line; 62, a loader area;
3 is a firmware area. The loader area 62 is an area for storing a program for rewriting the firmware area 63 after being incorporated into the board.

In the address signal 51, the address corresponding to the word line is determined by the address signal input to the row decoder 52, and the address corresponding to the bit line is determined by the address signal input to the column decoder 53. When a word line has a defect, address signals A14 to A10, A4 to A0 corresponding to the defective word line.
In the address space diagram, the defective area 61 that cannot be used appears at every 32nd address and is divided into very small areas as shown in FIG. 8, and the amount of usable continuous address space is reduced.

Therefore, as a means for relieving a defect, a method of replacing a defective bit line or a defective word line with a completely different rescue bit line or word line so that there is no area which cannot be used due to the defect on the memory map. Was taken.

[0010]

However, in the conventional defect repair system, the memory size is increased by the amount of the repair bit lines and word lines. In addition, the rescue bit lines and word lines have to be mounted on the semiconductor integrated device in advance.

An object of the present invention is to remedy a non-defective product even if a defect occurs in a bit line or a word line without mounting a memory cell for rescue in advance if a flash memory size has a margin for a program code size. It is an object.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor integrated device having a memory cell array including nonvolatile memory cells arranged in an array. One address signal is decoded by a row decoder, a corresponding word line is selected, and a second address signal is decoded by a column decoder, and a corresponding bit line is selected, thereby being input to the memory cell array. Storage means for selecting a memory cell corresponding to an address signal; and setting means for setting the row decoder and the column decoder so that a defective bit line or a defective word line corresponds to a continuous space on a memory map. Features.

According to a second aspect of the present invention, there is provided the semiconductor integrated device according to the first aspect, wherein position information of the defective bit line or the defective word line in the memory cell array is stored in the memory cell array. .

According to a third aspect of the present invention, in the semiconductor integrated device of the second aspect, the storage means includes a plurality of memory cell arrays and stores position information of the defective bit line or the defective word line in the memory cell array. It is characterized by further comprising selecting means for arbitrarily selecting a memory cell array.

According to a fourth aspect of the present invention, in the semiconductor integrated device of the third aspect, array selection information indicating a memory cell array for storing position information of the defective bit line or the defective word line in the memory cell array is stored. Means for selecting a memory cell array for storing the position information based on the array selection information.

According to a fifth aspect of the present invention, in the semiconductor integrated device of the first aspect, the setting means arbitrarily exchanges address signals input to the row decoder and the column decoder. .

According to a sixth aspect of the present invention, in the semiconductor integrated device according to the fifth aspect, means for storing exchange information as to which of the row decoder and the column decoder each of the address signal is to be inputted, and The setting means has means for exchanging all or part of the address signal input to the row decoder with all or part of the address signal input to the column decoder based on the exchange information. It is characterized by.

According to a seventh aspect of the present invention, in the semiconductor integrated device of the fifth aspect, when the word line is defective, the setting means sets the address signal input to the row decoder to an address signal of an upper bit. When the bit line is defective, the setting means sets an address signal input to the column decoder as an address signal of a higher-order bit.

With the above configuration, a nonvolatile semiconductor memory device having a defective bit line or a defective word line can be remedied as a non-defective product.

According to an eighth aspect of the present invention, there is provided the semiconductor integrated device according to the second aspect, wherein a microcomputer and an address corresponding to position information of the defective bit line or the defective word line in the memory cell array of the storage means are stored. A match circuit for comparing the input address signal with the match circuit, and when the output of the match circuit is a match, invalidates the output from the storage means and issues a branch instruction to the microcomputer to jump over the address of the defective area. And a circuit.

According to a ninth aspect of the present invention, there is provided the semiconductor integrated device according to the second aspect, wherein a microcomputer and an address corresponding to positional information of the defective bit line or the defective word line in the memory cell array of the storage means. A matching circuit that compares the input address signal with the input signal; and a circuit that invalidates an output from the storage unit and issues a no-operation instruction to the microcomputer when an output of the matching circuit is a match. It is characterized by.

A semiconductor integrated device according to a tenth aspect of the present invention is the semiconductor integrated device according to the second aspect, wherein a microcomputer and an address corresponding to positional information of the defective bit line or the defective word line in the memory cell array of the storage means. It further comprises a matching circuit for comparing the input address signal with the input signal, and a circuit for adding the address of the defective area to a program counter of the microcomputer when the output of the matching circuit matches.

With the above configuration, it is not necessary to provide a branch instruction immediately before a defective area on a program.

According to an eleventh aspect of the present invention, there is provided the semiconductor integrated device according to the second aspect, further comprising a microcomputer, wherein the microcomputer corresponds to positional information of the defective bit line or the defective word line in the memory cell array. And comparing the calculated address with the value of the program counter of the microcomputer, and when the comparison result shows a match, stops operations other than updating the value of the program counter.

According to a twelfth aspect of the present invention, in the semiconductor integrated device of the second, fourth or sixth aspect, the position information or the position information of the defective bit line or the defective word line in the memory means in the memory cell array is stored. Information indicating a memory cell array having a storage area or information indicating a test result such as exchange information as to which decoder a part of the address signal is to be input to an area for storing a firmware rewrite program or once written, It is characterized in that writing is performed in an area that cannot be changed.

According to a thirteenth aspect of the present invention, in the semiconductor integrated device according to the second, fourth, sixth, or twelfth aspect, information indicating the inspection result is written in an inspection step.

As described above, it is not necessary to check the memory every time the program is rewritten.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.

FIG. 1 is a memory map according to an embodiment of the present invention. Assuming that the flash memory of the present invention has a two-array structure, 13 and 14 are address spaces corresponding to the divided memory cell arrays 1 and 2, respectively, 11 is a loader area, and 12 is a defective bit line or a defective word. A defective information storage area 15 for storing line position information, and a defective area 15 which cannot be used due to a defective bit line or a defective word line.

When a certain bit line or word line is defective,
By storing the position information of the defective bit line and the defective word line in advance in the defect information storage area 12, the position information of the defective bit line and the defective word line is stored in the defect information at the time of rewriting the program in the firmware area after the board is assembled. A chip can be remedied as a non-defective product by reading from the area 12, selecting software to be written from several kinds of software based on the information, and setting the defective area 15 as an unused area.

FIG. 2 is a block diagram showing a register according to an embodiment of the present invention. 21 is an array selection register, 22 is an array selection multiplexer, 23
Is a register for changing the decoder for inputting the address signal, 24 is a multiplexer for selecting an address signal to the row decoder 52, 25 is a multiplexer for selecting an address signal to the column decoder 53, 26 is an array selection address signal, 27 is an address signal input to the row decoder 52, 28 is an address signal selected by the multiplexer 24 input to the row decoder 52, and 29 is an address signal selected by the multiplexer 25 input to the column decoder 53.

If there is a defective bit line or a defective word line in the loader area 11, data cannot be rewritten to the firmware area normally, so that the loader area 11 must not be defective. Therefore, when a certain bit line or word line is defective, the register 21 is assigned to either the memory cell array 1 or the memory cell array 2 in order to allocate the memory cell array having no defective bit line or defective word line to the loader area. Is written in advance as to whether or not to place. For example, register 21
When A15 is 0, 0 is output from the multiplexer 22 and the memory cell array 1 is selected by the array selection address signal 26. When 1 is written to the register 21, when A15 is 0, 1 is output from the multiplexer 22. Then, the memory cell array 2 is selected by the array selection address signal 26. Thereby, even if either memory cell array has a defect, the rewrite program can be normally written by allocating the loader area to the memory cell array having no defect. Here, the method of writing information in the register 21 in advance is, for example, if the difference in information is determined based on the presence or absence of connection by a fuse, after the inspection, an overcurrent flows from the dedicated terminal to the overcurrent fusing type fuse to cut the fuse. I do. Alternatively, it can be realized by a method of cutting a fuse by a laser.

Depending on whether the defect is on the bit line or the word line, the defective area is arranged on the memory map.
There are cases where the continuous address space that can be used is reduced by being divided into very small areas like the defective area 61 in FIG. Therefore, programming becomes difficult even when the defective area 61 is set as an unused area.

FIG. 3 shows a register 2 according to an embodiment of the present invention.
FIG. 3 is a diagram showing the correspondence among No. 3, address signals, and decoders.

For example, if 1 is written to the register 23, the address signals A14 to A10 are input to the column decoder 53, and A4 to A0 are input to the row decoder 52.

When there is a defect in a word line, specific address signals A9 to A5 (for example, 100
10 [binary number]) and A4 to A0 (for example, 11010 [binary number]) are the address signals 27 input to the row decoder 52.
And the address signal 28 selected by the multiplexer 24 input to the row decoder 52,
, The row decoder 52 selects and decodes the defective word line, and as a result, the address 025A (1
000000100101101 in hexadecimal and binary
0), 065A (hexadecimal, binary 00000)
11001011010), address 0A5A (hexadecimal,
The defective area 15 appears one by one every 1024 addresses as in binary number 0000101001011010).
The address space that can be used as shown in FIG. 1A is divided into a plurality of spaces by the defective area 15, and the usable continuous address space is reduced. However, by writing 0 to the change register 23 of the decoder that inputs the address signal, the addresses A14 to A10 are input to the row decoder 52 and A4 to A0 are input to the column decoder 53. 2
9 to the column decoder 53, the decoded defective area 15 becomes the address 4B40 on the memory map (hex 0100101101000 in hexadecimal and binary).
The area which appears continuously from address 000) to 32 and becomes unusable becomes a contiguous address space on the memory map as in the memory cell array 2 in FIG. 1B, and the usable continuous address space is enlarged. I can do it. Specifically, when the defect is on the bit line,
Register 23 for changing decoder for inputting address signal
The address A14 to A10 are input to the column decoder 53 and the addresses A4 to A0 are input to the row decoder 52. When the defect is on the word line,
Register 23 for changing decoder for inputting address signal
To the column decoder 53 and the row decoder 52 with the address A14.
To A10. By making it possible to change the selection of the defective word line or the defective bit line to the higher-order bits of the address signal, the usable continuous address space is increased, and the defect is detected in either the bit line or the word line. Even this can be remedied as a good product.

An inspection for determining the position information of the defective bit line or the defective word line and the information to be written in the array selection register 21 and the change register 23 of the decoder for inputting the address signal is performed when the customer rewrites the firmware area. Insufficient bit lines and defective word lines may operate properly depending on the operating conditions such as the operating voltage and operating temperature of the customer. Even if it operates normally, under a condition of use different from that at the time of rewriting, a defective bit line or a defective word line may not be used normally. In addition, since all the word lines and bit lines must be inspected for defects, not only the rewriting time for rewriting the firmware area but also all the word lines and bit lines must be inspected for defects. It takes time.

On the other hand, in general, the loader area does not need to be rewritten and must not be erased by mistake. Therefore, the loader area is not erased by erasing the firmware area.
The loader area is erased and rewritten by a dedicated jig. At the final stage of the product inspection process, a product operation guarantee condition is checked with a margin secured, and the information of the detected defective bit line or defective word line, the information of the array selection register 21, and the decoder for inputting the address signal are inputted. By writing the information of the change register 23 into the loader area, it is possible to prevent the product from operating abnormally due to the difference between the condition at the time of writing the firmware and the use condition, and to make it impossible for the customer to rewrite after shipping the product. The inspection of all words and all bit lines by the customer can be omitted.

FIG. 4 is a block diagram of a semiconductor integrated device according to one embodiment of the present invention. 31 is a microcomputer, 32 is a flash memory, 33 is a register for storing defect information, 34 is an address and a register 3
3, a comparator for comparing the value of 3; 35, a branch instruction issuing circuit;
6 is a data bus, 37 is a comparison result signal, 38 is an address bus, 39 is a chip select signal to the flash memory 32, 311 is a chip select signal issued by the microcomputer 31, and 23 is an address A9 to A9 in FIG.
3 shows a change register of a decoder that inputs an address signal of A0.

If the microcomputer 31 is operated using the data of the defective area 15, there is a risk of malfunction. Although it is necessary to add a branch instruction immediately before each defective area 15 so as not to malfunction, the address space for the added branch instruction is wasted.

Therefore, at the time of reset, the information in the defect information storage area 12 is loaded into the register 33. The comparator 34 compares the value of the register 33 with the address signals A15 to A5 of the address bus 38 if the value of the register 33 and the value of the register 23 for changing the column decoder and row decoder in FIG. If it is, it is compared with the address signals A15 to A10 of the address bus 38. The comparison result signal 37 is sent to the branch instruction issuing circuit 35 based on the comparison result. Here, if the comparison result of the comparator 34 matches, the branch instruction issuing circuit 35 issues a branch instruction to the data bus 36. At this time, the chip select signal 39 is negated so that data is not read from the flash memory 32 even if the chip select signal 311 is asserted from the microcomputer 31. If the comparison result of the comparator 34 does not match, the chip select signal 311 is output as it is to the chip select signal 39. As a result, a defective area 15 which cannot be used due to a defective bit line or a defective word line.
Does not require a branch instruction immediately before each defective area 15.

Further, a no-operation instruction may be issued instead of the branch instruction in order to prevent the data in the defective area 15 from being used.

FIG. 5 is a block diagram showing a program counter of the microcomputer according to one embodiment of the present invention. 41 is a program counter of the microcomputer 31, 42 is an adder for increasing the value of the program counter 41 by an address which cannot be used as a defect, 45 is the addition result, and 46 is the next program counter in normal operation. Where 43 is the addition result 45
And a selector for selecting the next program counter value 46, and 44 is the current program counter value.

Here, the adder 42 adds the address of the defective area 15 to the current value 44 of the program counter in order to jump the defective area 15 which cannot be used due to the defective bit line or the defective word line. is there.
The selector 43 switches the addition result 45 of the adder 42 and the value 46 of the next program counter in the normal operation based on the comparison result signal 37. Specifically, the comparison result signal 3
If the value of 7 is 1, the addition result 45 is output to the program counter 41, and if the value of the comparison result signal is 0, the value 46 of the next program counter in the normal operation is output to the program counter 41.

Thus, the same effect as that of the branch instruction issuing circuit 35 can be obtained by operating the microcomputer of the microcomputer without providing the branch instruction issuing circuit 35.

The same effect can be obtained by stopping operations other than updating the program counter.

[0047]

As described above, the semiconductor integrated device of the present invention stores information on a defective bit line and a defective word line in a memory cell array provided with a column decoder and a row decoder. Also, by making it possible to change the address signal input to the column decoder and the row decoder, the area that cannot be used due to the defective bit line or the defective word line becomes a continuous address space on the memory map,
The usable continuous address space can be increased.

With this configuration, if there is a margin in the code size of the ROM, a nonvolatile semiconductor memory device having a defective bit line or a defective word line can be rescued as a non-defective product even if a rescue memory cell is not mounted in advance. You can do it.

[Brief description of the drawings]

FIG. 1 is a memory map address space diagram according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a register according to one embodiment of the present invention;

FIG. 3 is a diagram showing correspondence between a register 23, an address signal, and a decoder in one embodiment of the present invention.

FIG. 4 is a block diagram of a semiconductor integrated device according to one embodiment of the present invention;

FIG. 5 is a block diagram showing a program counter of a microcomputer according to one embodiment of the present invention.

FIG. 6 is a diagram showing a conventional address decoding method of a flash memory;

FIG. 7 is a diagram showing a correspondence between an address signal and a decoder in a conventional semiconductor integrated device.

FIG. 8 is a diagram showing a memory map of a conventional flash memory.

[Explanation of symbols]

Reference Signs List 11 loader area 12 defect information storage area for storing defect information of defective bit line or defective word line 13 address space corresponding to memory cell array 1 14 address space corresponding to memory cell array 2 15 defect area 21 array selection register 22 Array selection multiplexer 23 Decoder change register for inputting address signal 24 Selection multiplexer for row decoder 52 25 Selection multiplexer for column recorder 53 26 Array selection address signal 27 Address signal input to row decoder 52 28 Multiplexer 24 29 Address signal selected by multiplexer 25 31 Microcomputer 32 Flash memory 33 Register for storing defect information 34 Address and register Comparator for comparing the value of 33 35 Branch instruction issuing circuit 36 Data bus 37 Comparison result signal 38 Address bus 39 Chip select signal to flash memory 32 41 Program counter of microcomputer 42 Adder 43 Selector 44 Current value of program counter 45 Addition result 46 Next program counter value during normal operation 51 Address signal 52 Row decoder 53 Column decoder 54 Flash memory cell 55 Word line 56 Bit line 61 Defective area 62 Loader area 63 Farm area 311 Chip issued by microcomputer 31 Select signal

Claims (13)

[Claims] 1. A memory cell array comprising nonvolatile memory cells arranged in an array, wherein a first address signal among address signals input to the memory cell array is decoded by a row decoder to correspond to the first address signal. When the word line is selected, the second address signal is decoded by the column decoder, and the corresponding bit line is selected.
Storage means for selecting a memory cell corresponding to an address signal input to the memory cell array; and setting for setting the row decoder and the column decoder so that a defective bit line or a defective word line corresponds to a continuous space on a memory map. A semiconductor integrated device comprising: 2. The semiconductor integrated device according to claim 1, wherein position information of the defective bit line or the defective word line in the memory cell array is stored in the memory cell array. 3. The storage unit further includes a selection unit including a plurality of memory cell arrays and arbitrarily selecting a memory cell array for storing position information of the defective bit line or the defective word line in the memory cell array. The semiconductor integrated device according to claim 2. 4. The memory according to claim 1, wherein said selection means stores array selection information indicating a memory cell array for storing position information of said defective bit line or said defective word line in said memory cell array, and stores said position information based on said array selection information. 4. The semiconductor integrated device according to claim 3, further comprising: means for selecting a memory cell array to be used. 5. The semiconductor integrated device according to claim 1, wherein said setting means arbitrarily exchanges address signals input to said row decoder and said column decoder. 6. The setting means includes means for storing exchange information indicating whether the address signal is to be input to the row decoder or the column decoder, and inputting the address signal to the row decoder based on the exchange information. 6. The semiconductor integrated device according to claim 5, further comprising means for exchanging all or part of the address signal to be input with all or part of the address signal input to the column decoder. 7. The setting means sets an address signal input to the row decoder as an upper bit address signal when the word line is defective, and sets an address signal input to the column decoder when the bit line is defective. 6. The semiconductor integrated device according to claim 5, wherein the signal is an upper bit address signal. 8. A matching circuit for comparing a microcomputer, an address corresponding to position information of the defective bit line or the defective word line in the memory cell array of the storage means with an input address signal, and an output of the matching circuit. 3. The semiconductor integrated device according to claim 2, further comprising: a circuit for invalidating the output from said storage means when a match is found, and issuing a branch instruction for jumping over an address of a defective area to said microcomputer. . 9. A matching circuit for comparing an address corresponding to position information of the defective bit line or defective word line in the memory cell array in the memory cell array with an input address signal, and an output of the matching circuit. 3. The semiconductor integrated device according to claim 2, further comprising: a circuit for invalidating an output from said storage means when a match is found, and issuing a no-operation instruction to said microcomputer. 10. A microcomputer, a matching circuit for comparing an address corresponding to position information of the defective bit line or the defective word line in the memory cell array of the storage means with an input address signal, and an output of the matching circuit. 3. The semiconductor integrated device according to claim 2, further comprising: a circuit for adding an address of the defective area to a program counter of the microcomputer when the two values match. 11. A microcomputer further comprising a microcomputer,
An address corresponding to the position information of the defective bit line or the defective word line in the memory cell array of the storage means is compared with a value of a program counter of the microcomputer. 3. The semiconductor integrated device according to claim 2, wherein operations other than updating are stopped. 12. A decoder which stores position information of the defective bit line or the defective word line in the memory cell array of the storage means, information indicating a memory cell array having an area for storing the position information, and a part of the address signal. 7. The semiconductor according to claim 2, wherein information indicating a test result such as exchange information to be input to the memory is written in an area for storing a firmware rewrite program or an area which cannot be changed once written. Integrated device. 13. The semiconductor integrated device according to claim 2, wherein information indicating the inspection result is written in an inspection step.