US20230162811A1 - Integrated circuit, memory and operation method of memory - Google Patents
Integrated circuit, memory and operation method of memory Download PDFInfo
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- US20230162811A1 US20230162811A1 US17/727,000 US202217727000A US2023162811A1 US 20230162811 A1 US20230162811 A1 US 20230162811A1 US 202217727000 A US202217727000 A US 202217727000A US 2023162811 A1 US2023162811 A1 US 2023162811A1
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- 238000000034 method Methods 0.000 title claims description 11
- 230000007547 defect Effects 0.000 claims abstract description 8
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- 230000002950 deficient Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
- G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1802—Address decoder
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
Definitions
- Various embodiments of the present invention relate to a memory.
- Embodiments of the present invention are directed to providing a technique for efficiently using resources that are required for memory repair and configuration.
- a memory includes: a memory array; a nonvolatile memory circuit suitable for storing a plurality of data sets each including flag information and multi-bit data; a plurality of repair register sets suitable for receiving and storing the multi-bit data included in the data sets whose flag information is marked for repair among the data sets during a boot-up operation; a plurality of setting register sets suitable for storing setting information included in the data sets whose flag information is marked for setting among the data sets during the boot-up operation; and a repair circuit suitable for repairing a defect in the memory array based on the multi-bit data stored in the repair register sets.
- an integrated circuit includes: a nonvolatile memory circuit suitable for storing first data sets each including first-level flag information and data, and second data sets each including second-level flag information, a setting address, and setting information; a plurality of first register sets respectively suitable for storing the data included in the first data sets that are read from the nonvolatile memory circuit; and a plurality of second register sets each suitable for storing the setting information included in the second data set which includes the setting address corresponding thereto among the second data sets that are read from the nonvolatile memory circuit.
- a method for operating a memory includes: reading a first data set from a nonvolatile memory circuit; confirming that flag information included in the first data set is of a first level; storing repair information included in the first data set in one among a plurality of repair register sets; reading a second data set from the nonvolatile memory circuit; confirming that flag information included in the second data set is of a second level; selecting one of a plurality of setting register sets by decoding a setting address included in the second data set; and storing setting information included in the second data set in the selected setting register set.
- an integrated circuit includes: a nonvolatile storage circuit suitable for storing therein information pieces each flagged with one of first and second flags and outputting, while the integrated circuit is booted up, the stored information pieces; first and second register sets each suitable for storing therein each of the output information pieces according to a corresponding one of the first and second flags, with which the output information piece is flagged; and a control circuit suitable for performing a first operation according to the information piece stored in the first register set and a second operation according to the information piece stored in the second register set.
- FIG. 1 is a block diagram illustrating a memory in accordance with an embodiment of the present invention.
- FIG. 2 illustrates data sets that are stored in a nonvolatile memory circuit shown in FIG. 1 in accordance with an embodiment of the present invention.
- FIG. 3 is a block diagram illustrating a memory in accordance with another embodiment of the present invention.
- FIG. 4 illustrates data sets that are stored in a nonvolatile memory circuit shown in FIG. 3 in accordance with an embodiment of the present invention.
- FIG. 5 is a table showing information included in the data sets shown in FIG. 4 in accordance with an embodiment of the present invention.
- FIG. 1 is a block diagram illustrating a memory 100 in accordance with an embodiment of the present invention.
- the memory 100 may include a nonvolatile memory circuit 110 , a selection circuit 120 , setting register sets 131 to 134 , repair register sets 141 to 144 , internal circuits 150 _ 0 to 150 _ 3 , a repair circuit 160 , and a memory array 170 .
- the nonvolatile memory circuit 110 may store data necessary for an operation of the memory 100 .
- the nonvolatile memory circuit 110 may be one among all types of nonvolatile memory circuits, such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an Erasable Programmable Read Only Memory (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a Ferroelectric Random Access Memory (FRAM), and a Magneto-resistive RAM (MRAM).
- Data stored in the nonvolatile memory circuit 110 may be read from and outputted from the nonvolatile memory circuit 110 during a boot-up operation.
- the nonvolatile memory circuit 110 may store a plurality of data sets.
- FIG. 2 shows data sets 201 to 208 that are stored in the nonvolatile memory circuit 110 in accordance with an embodiment of the present invention.
- the type of information may be determined according to locations where corresponding information is stored.
- the data sets 201 to 204 may include setting information for setting the memory 100 .
- the data set 201 may include 0 th setting information for setting a voltage level ‘A’
- the data set 202 may include 1 st setting information for setting a voltage level ‘B’.
- the data set 203 may include 2 nd setting information for setting a timing parameter ‘C’
- the data set 204 may include 3 rd setting information for setting a timing parameter ‘D’.
- the data sets 205 to 208 may include information for repairing the memory array 170 .
- Each of the data sets 205 to 208 may include information on a defective area in the memory array 170 , that is, a defective address corresponding to the defective area.
- Each of the data sets 201 to 208 may have the same number of bits. As shown (“Boot-up sequence”) in FIG. 2 , the data sets 201 to 208 may be loaded from the nonvolatile memory circuit 110 to the register sets 131 to 134 and 141 to 144 in the order of 201 , 202 , 203 . . . 208 .
- the information output from the nonvolatile memory circuit 110 may not be used directly but may be used after being transferred to the register sets 131 to 134 and 141 to 144 .
- the operation of transferring information from the nonvolatile memory circuit 110 to the register sets 131 to 134 and 141 to 144 to utilize the information stored in the register sets 131 to 134 and 141 to 144 may be called a boot-up operation.
- the boot-up operation may be performed during an initialization of the memory 100 .
- the selection circuit 120 may generate selection signals S ⁇ 0 : 7 > for selecting the register sets 131 to 134 and 141 to 144 during the boot-up operation.
- the selection circuit 120 may sequentially activate the selection signals S ⁇ 0 : 7 > in the order of S ⁇ 0 > to S ⁇ 7 > during the boot-up operation.
- the setting register sets 131 to 134 may receive and store data that are read from the nonvolatile memory circuit 110 during a boot-up operation.
- the setting register sets 131 to 134 may store data DATA_ARE output from the nonvolatile memory circuit 110 when a selection signal corresponding thereto among the selection signals S ⁇ 0 : 3 > is activated.
- data may be output from the nonvolatile memory circuit 110 in the order of the data set 201 , the data set 202 , the data set 203 and the data set 204 , and the selection signals S ⁇ 0 : 3 > may be activated in the order of S ⁇ 0 >, S ⁇ 1 >, S ⁇ 2 > and S ⁇ 3 >.
- the setting register set 131 may store the data included in the data set 201
- the setting register set 132 may store the data included in the data set 202
- the setting register set 133 may store the data included in the data set 203
- the setting register set 134 may store the data included in the data set 204 .
- the repair register sets 141 to 144 may receive and store data read from the nonvolatile memory circuit 110 during a boot-up operation.
- the repair register sets 141 to 144 may store data DATA_ARE output from the nonvolatile memory circuit 110 when a corresponding selection signal among the selection signals S ⁇ 4 : 7 > is activated.
- data may be output from the nonvolatile memory circuit 110 in the order of the data set 205 , the data set 206 , the data set 207 and the data set 208 , and the selection signals S ⁇ 4 : 7 > may be activated in the order of S ⁇ 4 >, S ⁇ 5 >, S ⁇ 6 > and S ⁇ 7 > .
- the repair register set 141 may store the data included in the data set 205
- the repair register set 142 may store the data included in the data set 206
- the repair register set 143 may store the data included in the data set 207
- the repair register set 144 may store the data included in the data set 208 .
- the internal circuits 150 _ 0 to 150 _ 3 may be circuits that operate based on setting information stored in the setting register sets 131 to 134 .
- the internal circuit 150 _ 0 may be a circuit that generates a voltage ‘A’ and may set a level of the voltage ‘A’ based on the setting information stored in the setting register set 131 .
- the internal circuit 150 _ 1 may be a circuit that generates a voltage ‘B’ and may set a level of the voltage ‘B’ based on the setting information stored in the setting register set 132 .
- the internal circuit 150 _ 2 may be a circuit that performs an operation ‘C’ and may set the timing parameters related to the operation ‘C’ based on the setting information stored in the setting register set 133 .
- the internal circuit 150 _ 3 may be a circuit that performs an operation ‘D’ and may set the timing parameter related to the operation ‘D’ based on the setting information stored in the setting register set 134 .
- the operations of the internal circuits 150 _ 0 to 150 _ 3 are mere examples, and the internal circuits 150 _ 0 to 150 _ 3 may perform diverse operations based on the setting information stored in the setting register sets 131 to 134 .
- the memory array 170 may include a plurality of memory cells for storing data, and circuits for writing data to and reading data from the memory cells.
- the repair circuit 160 may repair a defect in the memory array 170 based on the information stored in the repair register sets 141 to 144 .
- Each of the repair register sets 141 to 144 may store a bad address corresponding to the defect of the memory array 170 , and the repair circuit 160 may replace the memory cells of the memory array 170 corresponding to the bad addresses stored in the repair register sets 141 to 144 with redundant memory cells.
- the type of information included in the data sets may be limited. For example, information for setting the voltage ‘A’ has to be included in the data set 201 to be loaded to the setting register set 131 , and the information for setting the timing parameter of the operation ‘C’ has to be included in the data set 203 to be loaded to the setting register set 133 .
- FIG. 3 is a block diagram illustrating a memory 300 in accordance with another embodiment of the present invention.
- the memory 300 may include a nonvolatile memory circuit 310 , a setting selection circuit 321 , a repair selection circuit 323 , setting register sets 331 to 334 , repair register sets 341 to 344 , internal circuits 350 _ 0 to 350 _ 3 , a repair circuit 360 , and a memory array 370 .
- the nonvolatile memory circuit 310 may store data necessary for the operation of the memory 300 .
- the nonvolatile memory circuit 310 may be one among diverse types of nonvolatile memory circuits, such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an Erasable Programmable Read Only Memory (EPROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a Ferroelectric RAM (FRAM), and a Magneto-resistive RAM (MRAM).
- Data stored in the nonvolatile memory circuit 310 may be read and output from the nonvolatile memory circuit 310 during a boot-up operation.
- the nonvolatile memory circuit 310 may store a plurality of data sets.
- FIG. 4 illustrates the data sets 401 to 406 that are stored in the nonvolatile memory circuit 310 shown in FIG. 3 in accordance with an embodiment of the present invention. Unlike in FIG. 2 , in FIG. 4 , the types of the information included in the data sets 401 to 406 may not match to locations where the information is stored. Referring to FIG. 4 , it may be seen that the data set 401 includes Oth repair information; the data set 402 includes 2 nd setting information; the data set 403 includes 1 st repair information; the data set 404 includes 2 nd repair information; the data set 405 includes 3 rd setting information; and the data set 406 includes 3 rd repair information.
- the data sets may be loaded from the nonvolatile memory circuit 310 in the order of 401 , 402 , 403 , . . . 406 .
- the setting information and the repair information are loaded from the nonvolatile memory circuit 310 in a mixed order
- the information included in the data sets 401 to 406 may be transferred to the proper register sets among the setting register sets 331 to 334 and the repair register sets 341 to 344 . This is because the information included in the data sets 401 to 406 has a structure as shown in FIG. 5 .
- FIG. 5 is a table showing information included in the data sets 401 to 406 shown in FIG. 4 .
- Each of the data sets 401 to 406 may include data of N+1 bits.
- the N th bit of each of the data sets 401 to 406 may be a flag signal indicating whether information included in the corresponding data set is repair information or setting information. When the flag information is ‘0’, it may indicate that information included in the corresponding data set is repair information, and when the flag information is ‘1’, it may indicate that the information included in the corresponding data set is setting information.
- the flag information is ‘0’, it may indicate that information included in the corresponding data set is repair information
- the flag information is ‘1’
- the flag information (N th bit) of the data sets 401 , 403 , 404 , and 406 since the flag information (N th bit) of the data sets 401 , 403 , 404 , and 406 is ‘0’, it may be seen that the data sets 401 , 403 , 404 , and 406 store repair information. 0 to (N ⁇ 1) th bits of the data sets 401 , 403 , 404 , and 406 may be repair information. Also, in FIG. 5 , since the flag information (N th bit) of the data sets 402 and 405 is ‘1’, it may be seen that the data sets 402 and 405 store setting information.
- the (N ⁇ 1) th bit and the (N ⁇ 2) th bit may be setting addresses indicating which setting information the information included in the corresponding data sets is.
- the setting address included in the data set 402 may be ‘10’
- the setting address included in the data set 405 may be ‘11’
- bits 0 th to (N ⁇ 3) th included in the data sets 402 and 405 may be setting information.
- the setting selection circuit 321 may generate selection signals SS ⁇ 0 : 3 > for the setting information included in the data sets 402 and 405 whose flag information is marked for setting among the data sets 401 to 406 to be loaded from the nonvolatile memory circuit 310 to the setting register sets 331 to 334 .
- the setting selection circuit 321 may decode the setting address to activate one of the selection signals SS ⁇ 0 : 3 > .
- the selection signal SS ⁇ 0 > may be activated.
- the selection signal SS ⁇ 1 > may be activated.
- the selection signal SS ⁇ 2 > may be activated, and when the set address is ‘11’, the selection signal SS ⁇ 3 > may be activated.
- the repair selection circuit 323 may generate selection signals RS ⁇ 0 : 3 > for storing the repair information included in the data sets 401 , 403 , 404 , and 406 whose flag information is marked for repair among the data sets 401 to 406 to be loaded from the nonvolatile memory circuit 310 to the repair register sets 341 to 344 .
- the repair selection circuit 323 may sequentially activate the selection signals in the order of RS ⁇ 0 > to RS ⁇ 3 > whenever the data sets 401 , 403 , 404 , and 406 whose flag information is marked for repair among the data sets 401 to 406 are sequentially loaded from the nonvolatile memory circuit 310 .
- the setting register sets 331 to 334 may receive and store data that are read from the nonvolatile memory circuit 310 during a boot-up operation.
- the setting register sets 331 to 334 may store data DATA_ARE output from the nonvolatile memory circuit 310 when a corresponding selection signal among the selection signals SS ⁇ 0 : 3 > is activated.
- the repair register sets 341 to 344 may receive and store data read from the nonvolatile memory circuit 310 during a boot-up operation.
- the repair register sets 341 to 344 may store data
- the internal circuits 350 _ 0 to 350 _ 3 may be circuits that operate based on the setting information stored in the setting register sets 331 to 334 .
- the internal circuit 350 _ 0 may be a circuit that generates a voltage ‘A’ and may set the level of the voltage ‘A’ based on the setting information stored in the setting register set 331 .
- the internal circuit 350 _ 1 may be a circuit that generates a voltage ‘B’ and may set the level of the voltage ‘B’ based on the setting information stored in the setting register set 332 .
- the internal circuit 350 _ 2 may be a circuit that performs an operation ‘C’ and may set a timing parameter related to the operation ‘C’ based on the setting information stored in the setting register set 333 .
- the internal circuit 350 _ 3 may be a circuit that performs an operation ‘D’ and may set a timing parameter related to the operation ‘D’ based on the setting information stored in the setting register set 334 .
- the operations of the internal circuits 350 _ 0 to 350 _ 3 are mere examples, and the internal circuits 350 _ 0 to 350 _ 3 may perform diverse operations based on the setting information stored in the setting register sets 331 to 334 .
- the memory array 370 may include a plurality of memory cells for storing data, and circuits for writing data to and reading data from the memory cells.
- the repair circuit 360 may repair a defect in the memory array 370 based on the information stored in the repair register sets 341 to 344 .
- Bad addresses corresponding to defects of the memory array 370 may be stored in the repair register sets 341 to 344 , and the repair circuit 360 may replace the memory cells of the memory array 370 corresponding to the bad addresses stored in the repair register sets 341 to 344 with redundant memory cells.
- a boot-up operation process of the memory 300 shown in FIG. 3 will be described with reference to FIGS. 3 to 5 .
- the data set 401 may be read and output from the nonvolatile memory circuit 310 . Since the flag information included in the data set 401 is ‘0’, the repair selection circuit 323 may activate the first selection signal RS ⁇ 0 >, and the 0 th to (N ⁇ 1) th bits that are repair information included in the data set 401 may be stored in the repair register set 341 .
- the data set 402 may be read and output from the nonvolatile memory circuit 310 . Since the flag information included in the data set 402 is ‘1’, the setting selection circuit 321 may decode the setting address to activate one of the selection signals SS ⁇ 0 : 3 >.
- the setting selection circuit 321 may activate the selection signal SS ⁇ 2 >, and 0 th to (N ⁇ 3) th bits, which are setting information included in the data set 402 , may be stored in the setting register set 333 .
- the data set 403 may be read and output from the nonvolatile memory circuit 310 . Since the flag information included in the data set 403 is ‘0’, the repair selection circuit 323 may activate the second selection signal RS ⁇ 1 >, and the 0 th to (N ⁇ 1) th bits, which are repair information included in the data set 403 , may be stored in the repair register set 342 .
- the data set 404 may be read and output from the nonvolatile memory circuit 310 . Since the flag information included in the data set 404 is ‘0’, the repair selection circuit 323 may activate the third selection signal RS ⁇ 2 >, and the 0 th to (N ⁇ 1) th bits, which are repair information included in the data set 404 , may be stored in the repair register set 343 . To have a look at the 0 th to (N ⁇ 1) th bits, which are repair information included in the data set 404 , it may be seen that all values are ‘0’. This may mean that the repair information included in the data set 404 is not valid.
- all values of the data set 404 even including the flag information are ‘0’, which may mean that the data set 404 has never been recorded. Since the repair information included in the data set 404 is invalid, a boot-up operation itself may not be performed on the data set 404 . In short, the nonvolatile memory circuit 310 may not perform the operation of outputting data included in the data set 404 whose information is invalid.
- the data set 405 may be read and output from the nonvolatile memory circuit 310 . Since the flag information included in the data set 405 is ‘1’, the setting selection circuit 321 may decode the setting address to activate one of the selection signals SS ⁇ 0 : 3 >. Since the setting address, which occupies (N ⁇ 1) th to (N ⁇ 2) th bits, included in the data set 405 are ‘11’, the setting selection circuit 321 may activate the selection signal SS ⁇ 3 >, and 0 th to (N ⁇ 3) th bits, which are setting information included in the data set 405 , which may be stored in the setting register set 334 .
- the data set 406 may be read and output from the nonvolatile memory circuit 310 . Since the flag information included in the data set 406 is ‘0’, the repair selection circuit 323 may activate the fourth selection signal RS ⁇ 3 >, and the 0 th to (N ⁇ 1) th bits, which are repair information included in the data set 406 , which may be stored in the repair register set 344 .
- no information may be stored in the setting register sets 331 and 332 . This is because the nonvolatile memory circuit 310 does not store the setting information to be stored in the setting register sets 331 and 332 .
- the setting operation of the internal circuits 350 _ 0 and 350 _ 1 is not necessary or omittable, no data may be stored in the setting register sets 331 and 332 even after the boot-up operation is completed. Similarly, even after the boot-up operation is completed, no data may be stored in some repair register sets.
- the use of the data sets 401 to 406 stored in the nonvolatile memory circuit 310 may not be predetermined.
- the data sets 401 to 406 may be used for repair or setting according to the value of flag information.
- the type of setting may be flexibly changed according to the value of the stored setting address. Accordingly, it may be possible to flexibly use the resources of the nonvolatile memory circuit 310 .
- resources that are required for memory repair and configuration may be efficiently used.
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Abstract
Description
- The present application claims priority to Korean Patent Application No. 10-2021-0164787, filed on Nov. 25, 2021, which is incorporated herein by reference in its entirety.
- Various embodiments of the present invention relate to a memory.
- In the early stage of a semiconductor memory device industry, there were many originally good dies on the wafers, which means that a memory could be produced through a semiconductor fabrication process with no defective memory cells. However, as the capacity of memories increases, it became difficult to fabricate a memory device that does not have any defective memory cells, and nowadays, it may be said that there is substantially no chance that a memory device is fabricated without any defective memory cells. To address this issue, a repair method of including redundant memory cells in a memory and replacing defective memory cells with the redundant memory cells may be used.
- Embodiments of the present invention are directed to providing a technique for efficiently using resources that are required for memory repair and configuration.
- In accordance with an embodiment of the present invention, a memory includes: a memory array; a nonvolatile memory circuit suitable for storing a plurality of data sets each including flag information and multi-bit data; a plurality of repair register sets suitable for receiving and storing the multi-bit data included in the data sets whose flag information is marked for repair among the data sets during a boot-up operation; a plurality of setting register sets suitable for storing setting information included in the data sets whose flag information is marked for setting among the data sets during the boot-up operation; and a repair circuit suitable for repairing a defect in the memory array based on the multi-bit data stored in the repair register sets.
- In accordance with another embodiment of the present invention, an integrated circuit includes: a nonvolatile memory circuit suitable for storing first data sets each including first-level flag information and data, and second data sets each including second-level flag information, a setting address, and setting information; a plurality of first register sets respectively suitable for storing the data included in the first data sets that are read from the nonvolatile memory circuit; and a plurality of second register sets each suitable for storing the setting information included in the second data set which includes the setting address corresponding thereto among the second data sets that are read from the nonvolatile memory circuit.
- In accordance with yet another embodiment of the present invention, a method for operating a memory includes: reading a first data set from a nonvolatile memory circuit; confirming that flag information included in the first data set is of a first level; storing repair information included in the first data set in one among a plurality of repair register sets; reading a second data set from the nonvolatile memory circuit; confirming that flag information included in the second data set is of a second level; selecting one of a plurality of setting register sets by decoding a setting address included in the second data set; and storing setting information included in the second data set in the selected setting register set.
- In accordance with still another embodiment of the present invention, an integrated circuit includes: a nonvolatile storage circuit suitable for storing therein information pieces each flagged with one of first and second flags and outputting, while the integrated circuit is booted up, the stored information pieces; first and second register sets each suitable for storing therein each of the output information pieces according to a corresponding one of the first and second flags, with which the output information piece is flagged; and a control circuit suitable for performing a first operation according to the information piece stored in the first register set and a second operation according to the information piece stored in the second register set.
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FIG. 1 is a block diagram illustrating a memory in accordance with an embodiment of the present invention. -
FIG. 2 illustrates data sets that are stored in a nonvolatile memory circuit shown inFIG. 1 in accordance with an embodiment of the present invention. -
FIG. 3 is a block diagram illustrating a memory in accordance with another embodiment of the present invention. -
FIG. 4 illustrates data sets that are stored in a nonvolatile memory circuit shown inFIG. 3 in accordance with an embodiment of the present invention. -
FIG. 5 is a table showing information included in the data sets shown inFIG. 4 in accordance with an embodiment of the present invention. - Various embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
-
FIG. 1 is a block diagram illustrating amemory 100 in accordance with an embodiment of the present invention. - Referring to
FIG. 1 , thememory 100 may include anonvolatile memory circuit 110, aselection circuit 120, settingregister sets 131 to 134,repair register sets 141 to 144, internal circuits 150_0 to 150_3, arepair circuit 160, and amemory array 170. - The
nonvolatile memory circuit 110 may store data necessary for an operation of thememory 100. Thenonvolatile memory circuit 110 may be one among all types of nonvolatile memory circuits, such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an Erasable Programmable Read Only Memory (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a Ferroelectric Random Access Memory (FRAM), and a Magneto-resistive RAM (MRAM). Data stored in thenonvolatile memory circuit 110 may be read from and outputted from thenonvolatile memory circuit 110 during a boot-up operation. - The
nonvolatile memory circuit 110 may store a plurality of data sets.FIG. 2 showsdata sets 201 to 208 that are stored in thenonvolatile memory circuit 110 in accordance with an embodiment of the present invention. In thedata sets 201 to 208, the type of information may be determined according to locations where corresponding information is stored. Thedata sets 201 to 204 may include setting information for setting thememory 100. Thedata set 201 may include 0th setting information for setting a voltage level ‘A’, and thedata set 202 may include 1st setting information for setting a voltage level ‘B’. Thedata set 203 may include 2nd setting information for setting a timing parameter ‘C’, and thedata set 204 may include 3rd setting information for setting a timing parameter ‘D’. Also, thedata sets 205 to 208 may include information for repairing thememory array 170. Each of thedata sets 205 to 208 may include information on a defective area in thememory array 170, that is, a defective address corresponding to the defective area. Each of thedata sets 201 to 208 may have the same number of bits. As shown (“Boot-up sequence”) inFIG. 2 , thedata sets 201 to 208 may be loaded from thenonvolatile memory circuit 110 to theregister sets 131 to 134 and 141 to 144 in the order of 201, 202, 203 . . . 208. The information output from thenonvolatile memory circuit 110 may not be used directly but may be used after being transferred to theregister sets 131 to 134 and 141 to 144. The operation of transferring information from thenonvolatile memory circuit 110 to theregister sets 131 to 134 and 141 to 144 to utilize the information stored in theregister sets 131 to 134 and 141 to 144 may be called a boot-up operation. The boot-up operation may be performed during an initialization of thememory 100. - The
selection circuit 120 may generate selection signals S<0:7> for selecting theregister sets 131 to 134 and 141 to 144 during the boot-up operation. Theselection circuit 120 may sequentially activate the selection signals S<0:7> in the order of S<0> to S<7> during the boot-up operation. - The
setting register sets 131 to 134 may receive and store data that are read from thenonvolatile memory circuit 110 during a boot-up operation. Thesetting register sets 131 to 134 may store data DATA_ARE output from thenonvolatile memory circuit 110 when a selection signal corresponding thereto among the selection signals S<0:3> is activated. During the boot-up operation, data may be output from thenonvolatile memory circuit 110 in the order of the data set 201, the data set 202, the data set 203 and the data set 204, and the selection signals S<0:3> may be activated in the order of S<0>, S<1>, S<2> and S<3>. Accordingly, thesetting register set 131 may store the data included in thedata set 201, and the setting register set 132 may store the data included in thedata set 202. Thesetting register set 133 may store the data included in thedata set 203, and the setting register set 134 may store the data included in thedata set 204. - The repair register sets 141 to 144 may receive and store data read from the
nonvolatile memory circuit 110 during a boot-up operation. The repair register sets 141 to 144 may store data DATA_ARE output from thenonvolatile memory circuit 110 when a corresponding selection signal among the selection signals S<4:7> is activated. During the boot-up operation, data may be output from thenonvolatile memory circuit 110 in the order of the data set 205, the data set 206, the data set 207 and the data set 208, and the selection signals S<4:7> may be activated in the order of S<4>, S<5>, S<6> and S<7> . Accordingly, the repair register set 141 may store the data included in the data set 205, and the repair register set 142 may store the data included in thedata set 206. The repair register set 143 may store the data included in thedata set 207, and the repair register set 144 may store the data included in thedata set 208. - The internal circuits 150_0 to 150_3 may be circuits that operate based on setting information stored in the
setting register sets 131 to 134. The internal circuit 150_0 may be a circuit that generates a voltage ‘A’ and may set a level of the voltage ‘A’ based on the setting information stored in thesetting register set 131. The internal circuit 150_1 may be a circuit that generates a voltage ‘B’ and may set a level of the voltage ‘B’ based on the setting information stored in the setting register set 132. The internal circuit 150_2 may be a circuit that performs an operation ‘C’ and may set the timing parameters related to the operation ‘C’ based on the setting information stored in thesetting register set 133. The internal circuit 150_3 may be a circuit that performs an operation ‘D’ and may set the timing parameter related to the operation ‘D’ based on the setting information stored in the setting register set 134. Here, the operations of the internal circuits 150_0 to 150_3 are mere examples, and the internal circuits 150_0 to 150_3 may perform diverse operations based on the setting information stored in thesetting register sets 131 to 134. - The
memory array 170 may include a plurality of memory cells for storing data, and circuits for writing data to and reading data from the memory cells. - The
repair circuit 160 may repair a defect in thememory array 170 based on the information stored in therepair register sets 141 to 144. Each of the repair register sets 141 to 144 may store a bad address corresponding to the defect of thememory array 170, and therepair circuit 160 may replace the memory cells of thememory array 170 corresponding to the bad addresses stored in the repair register sets 141 to 144 with redundant memory cells. - In the
memory 100 ofFIG. 1 , since the data sets in thenonvolatile memory circuit 110 are matched to the respective register sets 131 to 134, the type of information included in the data sets may be limited. For example, information for setting the voltage ‘A’ has to be included in thedata set 201 to be loaded to thesetting register set 131, and the information for setting the timing parameter of the operation ‘C’ has to be included in thedata set 203 to be loaded to thesetting register set 133. -
FIG. 3 is a block diagram illustrating amemory 300 in accordance with another embodiment of the present invention. - Referring to
FIG. 3 , thememory 300 may include anonvolatile memory circuit 310, asetting selection circuit 321, arepair selection circuit 323, setting register sets 331 to 334, repair register sets 341 to 344, internal circuits 350_0 to 350_3, arepair circuit 360, and amemory array 370. - The
nonvolatile memory circuit 310 may store data necessary for the operation of thememory 300. Thenonvolatile memory circuit 310 may be one among diverse types of nonvolatile memory circuits, such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an Erasable Programmable Read Only Memory (EPROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a Ferroelectric RAM (FRAM), and a Magneto-resistive RAM (MRAM). Data stored in thenonvolatile memory circuit 310 may be read and output from thenonvolatile memory circuit 310 during a boot-up operation. - The
nonvolatile memory circuit 310 may store a plurality of data sets.FIG. 4 illustrates thedata sets 401 to 406 that are stored in thenonvolatile memory circuit 310 shown inFIG. 3 in accordance with an embodiment of the present invention. Unlike inFIG. 2 , inFIG. 4 , the types of the information included in thedata sets 401 to 406 may not match to locations where the information is stored. Referring toFIG. 4 , it may be seen that thedata set 401 includes Oth repair information; thedata set 402 includes 2nd setting information; thedata set 403 includes 1st repair information; thedata set 404 includes 2nd repair information; thedata set 405 includes 3rd setting information; and thedata set 406 includes 3rd repair information. As shown (“Boot-up sequence”) inFIG. 4 , the data sets may be loaded from thenonvolatile memory circuit 310 in the order of 401, 402, 403, . . . 406. Although the setting information and the repair information are loaded from thenonvolatile memory circuit 310 in a mixed order, the information included in thedata sets 401 to 406 may be transferred to the proper register sets among the setting register sets 331 to 334 and the repair register sets 341 to 344. This is because the information included in thedata sets 401 to 406 has a structure as shown inFIG. 5 . -
FIG. 5 is a table showing information included in thedata sets 401 to 406 shown inFIG. 4 . Each of thedata sets 401 to 406 may include data of N+1 bits. The Nth bit of each of thedata sets 401 to 406 may be a flag signal indicating whether information included in the corresponding data set is repair information or setting information. When the flag information is ‘0’, it may indicate that information included in the corresponding data set is repair information, and when the flag information is ‘1’, it may indicate that the information included in the corresponding data set is setting information. In FIG. 5, since the flag information (Nth bit) of the data sets 401, 403, 404, and 406 is ‘0’, it may be seen that the data sets 401, 403, 404, and 406 store repair information. 0 to (N−1)th bits of the data sets 401, 403, 404, and 406 may be repair information. Also, inFIG. 5 , since the flag information (Nth bit) of thedata sets data sets data sets data set 402 may be ‘10’, and the setting address included in thedata set 405 may be ‘11’, andbits 0th to (N−3)th included in thedata sets - Referring back to
FIG. 3 , thesetting selection circuit 321 may generate selection signals SS<0:3> for the setting information included in thedata sets data sets 401 to 406 to be loaded from thenonvolatile memory circuit 310 to the setting register sets 331 to 334. Thesetting selection circuit 321 may decode the setting address to activate one of the selection signals SS<0:3> . When the setting address is ‘00’, the selection signal SS<0> may be activated. When the setting address is ‘01’, the selection signal SS<1> may be activated. When the setting address is ‘10’, the selection signal SS<2> may be activated, and when the set address is ‘11’, the selection signal SS<3> may be activated. - The
repair selection circuit 323 may generate selection signals RS<0:3> for storing the repair information included in the data sets 401, 403, 404, and 406 whose flag information is marked for repair among thedata sets 401 to 406 to be loaded from thenonvolatile memory circuit 310 to the repair register sets 341 to 344. Therepair selection circuit 323 may sequentially activate the selection signals in the order of RS<0> to RS<3> whenever the data sets 401, 403, 404, and 406 whose flag information is marked for repair among thedata sets 401 to 406 are sequentially loaded from thenonvolatile memory circuit 310. - The setting register sets 331 to 334 may receive and store data that are read from the
nonvolatile memory circuit 310 during a boot-up operation. The setting register sets 331 to 334 may store data DATA_ARE output from thenonvolatile memory circuit 310 when a corresponding selection signal among the selection signals SS<0:3> is activated. - The repair register sets 341 to 344 may receive and store data read from the
nonvolatile memory circuit 310 during a boot-up operation. The repair register sets 341 to 344 may store data - ARE_DATA output from the
nonvolatile memory circuit 310 when a corresponding selection signal among the selection signals RS<0:3> is activated. - The internal circuits 350_0 to 350_3 may be circuits that operate based on the setting information stored in the setting register sets 331 to 334. The internal circuit 350_0 may be a circuit that generates a voltage ‘A’ and may set the level of the voltage ‘A’ based on the setting information stored in the
setting register set 331. The internal circuit 350_1 may be a circuit that generates a voltage ‘B’ and may set the level of the voltage ‘B’ based on the setting information stored in the setting register set 332. The internal circuit 350_2 may be a circuit that performs an operation ‘C’ and may set a timing parameter related to the operation ‘C’ based on the setting information stored in thesetting register set 333. The internal circuit 350_3 may be a circuit that performs an operation ‘D’ and may set a timing parameter related to the operation ‘D’ based on the setting information stored in thesetting register set 334. Here, the operations of the internal circuits 350_0 to 350_3 are mere examples, and the internal circuits 350_0 to 350_3 may perform diverse operations based on the setting information stored in the setting register sets 331 to 334. - The
memory array 370 may include a plurality of memory cells for storing data, and circuits for writing data to and reading data from the memory cells. - The
repair circuit 360 may repair a defect in thememory array 370 based on the information stored in the repair register sets 341 to 344. Bad addresses corresponding to defects of thememory array 370 may be stored in the repair register sets 341 to 344, and therepair circuit 360 may replace the memory cells of thememory array 370 corresponding to the bad addresses stored in the repair register sets 341 to 344 with redundant memory cells. - A boot-up operation process of the
memory 300 shown inFIG. 3 will be described with reference toFIGS. 3 to 5 . - (1) The
data set 401 may be read and output from thenonvolatile memory circuit 310. Since the flag information included in thedata set 401 is ‘0’, therepair selection circuit 323 may activate the first selection signal RS<0>, and the 0th to (N−1)th bits that are repair information included in thedata set 401 may be stored in the repair register set 341. - (2) The
data set 402 may be read and output from thenonvolatile memory circuit 310. Since the flag information included in thedata set 402 is ‘1’, thesetting selection circuit 321 may decode the setting address to activate one of the selection signals SS<0:3>. - Since the setting address, which occupies (N−1)th to (N−2)th bits, included in the
data set 402 is ‘10’, thesetting selection circuit 321 may activate the selection signal SS<2>, and 0th to (N−3)th bits, which are setting information included in thedata set 402, may be stored in thesetting register set 333. - (3) The
data set 403 may be read and output from thenonvolatile memory circuit 310. Since the flag information included in thedata set 403 is ‘0’, therepair selection circuit 323 may activate the second selection signal RS<1>, and the 0th to (N−1)th bits, which are repair information included in thedata set 403, may be stored in the repair register set 342. - (4) The
data set 404 may be read and output from thenonvolatile memory circuit 310. Since the flag information included in thedata set 404 is ‘0’, therepair selection circuit 323 may activate the third selection signal RS<2>, and the 0th to (N−1)th bits, which are repair information included in thedata set 404, may be stored in the repair register set 343. To have a look at the 0th to (N−1)th bits, which are repair information included in thedata set 404, it may be seen that all values are ‘0’. This may mean that the repair information included in thedata set 404 is not valid. Namely, all values of thedata set 404 even including the flag information are ‘0’, which may mean that thedata set 404 has never been recorded. Since the repair information included in thedata set 404 is invalid, a boot-up operation itself may not be performed on thedata set 404. In short, thenonvolatile memory circuit 310 may not perform the operation of outputting data included in thedata set 404 whose information is invalid. - (5) The
data set 405 may be read and output from thenonvolatile memory circuit 310. Since the flag information included in thedata set 405 is ‘1’, thesetting selection circuit 321 may decode the setting address to activate one of the selection signals SS<0:3>. Since the setting address, which occupies (N−1)th to (N−2)th bits, included in thedata set 405 are ‘11’, thesetting selection circuit 321 may activate the selection signal SS<3>, and 0th to (N−3)th bits, which are setting information included in thedata set 405, which may be stored in thesetting register set 334. - (6) The
data set 406 may be read and output from thenonvolatile memory circuit 310. Since the flag information included in thedata set 406 is ‘0’, therepair selection circuit 323 may activate the fourth selection signal RS<3>, and the 0th to (N−1)th bits, which are repair information included in thedata set 406, which may be stored in the repair register set 344. - After the boot-up operation is completed, no information may be stored in the setting register sets 331 and 332. This is because the
nonvolatile memory circuit 310 does not store the setting information to be stored in the setting register sets 331 and 332. When the setting operation of the internal circuits 350_0 and 350_1 is not necessary or omittable, no data may be stored in the setting register sets 331 and 332 even after the boot-up operation is completed. Similarly, even after the boot-up operation is completed, no data may be stored in some repair register sets. - The use of the
data sets 401 to 406 stored in thenonvolatile memory circuit 310 may not be predetermined. For example, thedata sets 401 to 406 may be used for repair or setting according to the value of flag information. Also, the type of setting may be flexibly changed according to the value of the stored setting address. Accordingly, it may be possible to flexibly use the resources of thenonvolatile memory circuit 310. - According to the embodiment of the present invention, resources that are required for memory repair and configuration may be efficiently used.
- While the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. Furthermore, the embodiments may be combined to form additional embodiments.
Claims (15)
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Citations (5)
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US20070033449A1 (en) * | 2005-07-25 | 2007-02-08 | Samsung Electronics Co., Ltd. | Flash memory device and method of repairing defects and trimming voltages |
US20210065836A1 (en) * | 2019-09-02 | 2021-03-04 | Samsung Electronics Co., Ltd. | Method of test and repair of memory cells during power-up sequence of memory device |
US20210166777A1 (en) * | 2019-12-03 | 2021-06-03 | iSTART-Tek Technologies Co.,Ltd | Memory repair circuit, memory repair method, and memory module using memory repair circuit |
US20210233581A1 (en) * | 2020-01-28 | 2021-07-29 | Micron Technology, Inc. | Apparatus with latch balancing mechanism and methods for operating the same |
US20210357279A1 (en) * | 2020-05-15 | 2021-11-18 | Samsung Electronics Co., Ltd. | Handling operation system (os) in system for predicting and managing faulty memories based on page faults |
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KR102182419B1 (en) | 2013-06-28 | 2020-11-24 | 에스케이하이닉스 주식회사 | Non-volatile memory and semiconductor device including the same |
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- 2021-11-25 KR KR1020210164787A patent/KR20230077478A/en unknown
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070033449A1 (en) * | 2005-07-25 | 2007-02-08 | Samsung Electronics Co., Ltd. | Flash memory device and method of repairing defects and trimming voltages |
US20210065836A1 (en) * | 2019-09-02 | 2021-03-04 | Samsung Electronics Co., Ltd. | Method of test and repair of memory cells during power-up sequence of memory device |
US20210166777A1 (en) * | 2019-12-03 | 2021-06-03 | iSTART-Tek Technologies Co.,Ltd | Memory repair circuit, memory repair method, and memory module using memory repair circuit |
US20210233581A1 (en) * | 2020-01-28 | 2021-07-29 | Micron Technology, Inc. | Apparatus with latch balancing mechanism and methods for operating the same |
US20210357279A1 (en) * | 2020-05-15 | 2021-11-18 | Samsung Electronics Co., Ltd. | Handling operation system (os) in system for predicting and managing faulty memories based on page faults |
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