JP2001291099A - Graphic processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a graphic processor which can quickly process plural commands concerning drawing. SOLUTION: A graphic processor contains a single memory and plural drawing units for processing commands concerning drawing. Then every drawing unit executes the command processing concerning drawing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a graphic processor.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional drawing processing system. This drawing processing system includes a graphic processor 70, a host CPU 80, and a monitor 81.

[0003] The host CPU 80 is a device that executes a predetermined drawing application and outputs a command (hereinafter, referred to as a drawing command) relating to drawing, such as drawing a straight line between two points in a two-dimensional coordinate system. The graphic processor 70 is a device that interprets the contents of the drawing command and creates image data corresponding to the command.

Hereinafter, the contents of the drawing process performed by the graphic processor 70 will be described more specifically. Host CPU
The drawing command generated from 80 is supplied to the drawing unit 72 via the host interface 71 of the graphic processor 70. The drawing unit 72 interprets the contents of the drawing command and outputs drawing data for the command. Then, the memory controller 74 stores the drawing data in the memory 75.

Next, when displaying the drawing data stored in the memory 75 on the monitor 81, the memory controller 74 first reads out the drawing data to be displayed from the memory 75. Then, the display unit 73 receives the drawing data and displays it on the monitor 81.

[0006]

By the way, the host CP
A plurality of drawing commands may be issued from U80.
For example, as shown in FIG. 6, there is a case where a triangle and a circle are respectively drawn. In this case, it is necessary for one drawing unit 72 to perform, for example, a process of drawing a triangular figure, and then perform a process of drawing a circular figure. After that, the time required for the drawing process is determined by the memory control 74.
5 is longer than the time required for the data write process to be performed on No. 5. Therefore, when a plurality of drawing commands are generated, there is a problem that the drawing process is delayed in the method of performing the drawing process with one drawing unit 72.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a graphic processor which can quickly process each drawing command even when a plurality of drawing commands are generated. It is the purpose.

[0008]

According to a first aspect of the present invention, there is provided a graphic processor, comprising: a memory; and a plurality of drawing units for writing image data into the memory in response to a drawing command. And characterized in that:

In the graphic processor according to the present invention, a memory, a plurality of drawing units for writing image data to the memory in response to a drawing command, and image data written to the memory by a display device And a means for reading out each image data written in the memory for each drawing unit from which each is written, and supplying the image data to one of the plurality of display units. It is a feature.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. Such an embodiment shows one embodiment of the present invention and does not limit the present invention. Any changes can be made without departing from the spirit of the present invention.

A: Configuration of Embodiment FIG. 1 is a block diagram showing a configuration of a drawing signal processing system GS using a graphic processor 10 according to an embodiment of the present invention. As shown in FIG. 1, the system includes a graphic processor 10, a host CPU 2
0, monitors 21 to 24.

As shown in FIG. 1, the graphic processor 10 comprises a host interface 11, drawing units 201 to 203, display units 301 to 303, a memory controller 14, a memory 15, and an overlay controller 16.

The host interface 11 is a host C
This is a device that receives a drawing command generated from the PU 20 and outputs it to any of the drawing units 201 to 203. In the present embodiment, a drawing command from the host CPU 20 includes information for specifying a drawing unit. The host interface 11 has a function of detecting this information and outputting a drawing command to a drawing unit corresponding to the detection result.

The drawing units 201 to 203 are devices for interpreting the contents of supplied drawing commands and creating drawing data according to the contents of the commands. Then, each of the drawing units 201 to 203 transmits the created drawing data and a request to store the drawing data in the memory 15 (hereinafter, referred to as a request).
Described as a memory write request. ) Is output.

The memory controller 14 is a device that receives drawing data output from each of the drawing units 201 to 203 and a memory write request, and actually performs a memory write access to the memory 15. Hereinafter, the memory controller 14 will be described in more detail.

FIG. 2 is a block diagram showing a configuration of the memory controller 14 according to the present embodiment. As shown in the figure, the memory controller 14
Write request FI corresponding to each of 1 to 203
It has an FO (First In First Out) and a write FIFO. In FIG. 2, a write request FIFO 201A provided for the drawing unit 201 and a write FI
The FO 201B is shown, but other drawing units 20
Write request FIF for 2,203
O and a write FIFO are provided.

Of these, the write request FIFO 20
1A is a device for storing a memory write request output from the drawing unit 201. Also, write FIFO
201 </ b> B is a device for storing drawing data output from the drawing unit 201.

The control unit 141 controls each write request FI
This device detects a memory write request stored in the FO and executes a data write access to the memory 15 in accordance with the request. For example, the control unit 14
1 detects a memory write request stored in the write request FIFO 201A, and outputs a data write request to the memory 15. And light FI
The drawing data stored in the FO 201B is output to the data bus line 142.

As shown in FIG. 2, the memory controller 14 includes a read request FIFO and a read FIFO corresponding to each of the display units 301 to 303.
It also has O. In the figure, a display unit 301
Read request FIFO 301A provided for
And a read FIFO 301B, a read request FIFO and a read FIFO are similarly provided for the other display units 302 and 303.

The read request FIFO 301A is a device for storing a request to read out data from the memory 15 (hereinafter referred to as a memory read request) when drawing data stored in the memory 15 is displayed on a monitor. It is. Also, the read FIFO 301B is
This is a device for temporarily storing drawing data actually read from the memory 15.

The control unit 141 controls each read request FI
It has a function of detecting a data read request stored in the FO and executing an access to read data from the memory 15. For example, when detecting a data read request in the read request FIFO 301A, the control unit 141 outputs a data read request to the memory 15 and stores the drawing data read from the memory 15 in the read FIFO 301B.

Referring again to FIG. 1, the drawing processing system GS
The configuration will be described. The display units 301 to 303 are
Read the drawing data stored in each read FIFO,
This device outputs the data as data for displaying on a monitor screen. The monitors 21 to 23 are devices for displaying data output from the display units 301 to 303 on a screen.

The overlay control 16 is a device for synthesizing display data supplied from the display units 301 to 303 and outputting the data. And monitor 2
Reference numeral 4 denotes an apparatus for displaying combined data output from the overlay control 16 on a screen.

B: Operation of Embodiment Next, the operation of the drawing processing system GS according to the embodiment will be described. In order to facilitate the description of the operation, the operation will be described below on the assumption that the host CPU 20 is executing two drawing applications A and B.

First, when starting the execution of the two drawing applications A and B, the host CPU 20 negotiates with the memory controller 14 and determines the memory use area of the memory 15 for the drawing applications A and B. . This is performed in consideration of the fact that the memory usage varies depending on the drawing application to be executed. In other words, when a plurality of drawing applications are executed, the used memory area is not divided equally, but, for example, a lot of memory areas are allocated to a high-performance drawing application, thereby effectively utilizing the memory space. is there. Further, by performing the above-described negotiations and the like, a drawing unit for processing a command generated from each drawing application and a display unit for displaying each image stored in the memory 15 from each drawing unit are also determined. .

FIG. 3 shows the signal flow of each part of the graphic processor 10 when a drawing command is generated in the order of A1 and A2 from the drawing application A and a drawing command is generated in the order of B1 and B2 from the drawing application B. It is a time chart shown.

First, for the generated drawing commands A1 and B1, the host CPU 20 specifies a drawing unit for performing a drawing process, and then outputs these drawing commands. These drawing commands are sent to the host interface 1
1 are supplied to the designated drawing units. Here, it is assumed that the drawing command A1 is supplied to the drawing unit 201 and the drawing command B1 is supplied to the drawing unit 202.

The drawing units 201 and 202 interpret the contents of the supplied drawing commands A1 and B1 and create drawing data according to the contents of the commands. Then, each drawing unit outputs the created drawing data and a memory write request to the memory controller 14. The drawing data and the memory write request output from each drawing unit are stored in the write FIFO and the write request FIFO of the memory controller 14, respectively. The above operation is performed in synchronization with the operation clock UCLK of the drawing units 201 and 202.

Thereafter, the control unit 141 of the memory controller 14 detects a memory write request stored in the write request FIFO. In this specific example, two write requests F are output from the drawing units 201 and 202.
The memory write request is stored in the IFO.
The control unit 141 detects one by one in the order of requests stored earlier in the write request FIFO, and executes data write access to the memory 15 in response to the requests. At the same time, the control unit 141 causes the drawing data stored in the write FIFO to be output to the data bus line 142, and actually executes data writing to the memory 15. The above operation is performed by the operation clock MCLK of the memory 15.
It is performed in synchronization with.

FIG. 3 is a time chart showing the contents of the operation described so far. As shown in FIG. 3, the operation clock MCLK of the memory is sufficiently higher than the operation clock UCLK of each drawing unit. If it is faster, it is possible to process memory write requests from the two drawing units almost simultaneously.

Thereafter, in this specific example, the drawing command A2 generated from the drawing application A
01, and the drawing command B2 generated from the drawing application B is supplied to the drawing unit 202. After each of the drawing units 201 and 202 outputs a memory write request and drawing data to the memory controller 14, the drawing units 201 and 202 can perform a drawing process for another drawing command. Therefore, as shown in FIG. 3, each drawing unit can continuously process a plurality of drawing commands.

Next, the operation for displaying the drawing data stored in the memory 15 on a monitor will be described. As described above, when starting the execution of the two drawing applications A and B, the host CPU 20 determines the memory use area of the memory 15 for the drawing applications A and B in advance, and sets the drawing data stored in each memory area. The display unit that performs the process for displaying the monitor on the monitor is also determined.

Here, the host CPU 20 decides to allocate the memory area A of the memory 15 and the display unit 301 to the drawing application A, and to allocate the memory area B and the display unit 302 of the memory 15 to the drawing application B. It shall be assumed. Then, a command to monitor display the drawing data stored in the memory area A from the host CPU 20 to the display unit 301 (hereinafter, referred to as a display command).
Is output to the display unit 302, and a display command to monitor display of the drawing data stored in the memory area B is output to the display unit 302. These two display commands are supplied to each of the display units 301 and 302 via the host interface 11.

The display units 301 and 302 interpret and execute the contents of the display command. For example, when receiving the display command, the display unit 301 performs an operation of reading out the drawing data stored in the memory area A and outputting the drawing data in association with the monitor 21.

More specifically, the display unit 301
Is a request to read the drawing data stored in the memory area A (hereinafter, referred to as a memory read request).
Is output to the memory controller 14.

The memory read request is stored in the read request FIFO 301A of the memory controller 14. When detecting the memory read request, the memory controller 14 actually executes a memory read access to the area A of the memory 15 in response to the request. Then, the memory controller 14 stores the read drawing data in the read FIFO 301B.

The display unit 301 reads out the drawing data from the read FIFO 301B as needed, and outputs the drawing data according to the vertical synchronization signal of the monitor 21. Thus, the contents of the drawing data stored in the area A of the memory 15 are displayed on the monitor 21.

The processing related to monitor display for the display unit 301 has been described above.
The processing related to the monitor display for is performed in the same manner. That is, from the display unit 302, the memory 15
A memory read request to read the drawing data stored in the area B is output to the memory controller 14. Then, the display unit 302 reads out the drawing data read out from the memory area B as needed via the read FIFO, and outputs the drawing data in accordance with the vertical synchronization signal of the monitor 22.

FIG. 4 is a time chart showing the contents of the monitor display operation described so far.
As shown in FIG.
If the operation clock MCLK of the memory is sufficiently fast with respect to CLK2, it is possible to process requests to read drawing data from the two memory areas almost simultaneously.

C: Effects of the Embodiment As described above, according to the drawing processing system GS of the present embodiment, even when a plurality of drawing commands are generated, the drawing processing for each drawing command can be performed quickly. It is possible. Further, when displaying a plurality of drawing data stored in the memory on a monitor, it is possible to quickly perform display processing on the drawing data read from the memory.

D: Modifications Although the embodiment of the present invention has been described above, the above embodiment is merely an example, and can be arbitrarily modified without departing from the gist of the present invention.

FIG. 5 shows a modification of the drawing processing system GS. The drawing processing system GS according to the present embodiment is obtained by adding devices such as a CDROM, a DVD player, and a communication module. A host CPU according to this system can execute a plurality of drawing applications and operate each device of the CDROM, DVD player, and communication module. Also in this case, as shown in FIG. 5, a memory use area for each drawing application and each device, a drawing unit,
If the display unit is determined in advance and a drawing unit and a display unit are provided for each drawing application and each device, the same effect as in the above embodiment can be obtained.

[0043]

As described above, according to the graphic processor of the present invention, even when a plurality of commands related to drawing are generated, it is possible to quickly process each command.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a drawing processing system using a graphic processor according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory controller of the graphic processor.

FIG. 3 is a time chart for explaining an operation of a drawing processing system using a graphic processor according to an embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the system.

FIG. 5 is a diagram illustrating a modification of the system.

FIG. 6 shows a configuration diagram of a conventional drawing processing system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Graphic processor 11 ... Host interface 201,202,203 ... Drawing unit 301,302,303 ... Display unit 14 ... Memory controller 15 ... Memory 16 ... Overlay control 70 ... Graphic processor 80 ... Host CPU 81 ... Monitor

Claims (2)

[Claims] 1. A graphic processor, comprising: a memory; and a plurality of drawing units for writing image data to the memory in response to a drawing command. 2. A memory, a plurality of drawing units for writing image data to the memory in response to a drawing command, a plurality of display units for displaying image data written to the memory by a display device, and a plurality of display units for writing to the memory. Means for reading out each of the obtained image data for each drawing unit as a writing source, and supplying the image data to any one of the plurality of display units.