JP2001290858A - Performance estimating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for estimating the performance of a logical system composed of software running on a processor and dedicated hardware at a high speed. SOLUTION: An intermediate code 103 is generated from a logical system description program 101 in which the whole logical system is described in a program language; while a dedicated hardware performance table 104 and performance tables 105 by instructions of the processor are referred to, an instruction series 107 to be executed by the process is generated from the intermediate code 103 and a performance estimate value 108 is calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to software / hardware for supporting simultaneous design of software and hardware when designing a logical system composed of software operating on a processor and dedicated hardware. An object of the present invention is to provide a method for estimating the performance of the entire logical system for realizing the cooperative design method.

[0002]

2. Description of the Related Art A logical system includes a part implemented by software operating on a processor and a part implemented by dedicated hardware. Conventionally, this division of software and hardware is performed based on the experience of a designer. Then, in order to estimate the performance of the logical system, a simulation model of the software operating on the processor and a simulation model of the dedicated hardware are created, and both are connected to simulate the entire logical system. Estimates the performance of the entire system.

[0003]

However, in the above-described method for estimating performance, it is necessary to divide the hardware part and the software part and to create respective simulation models, which takes a lot of man-hours to develop the simulation model. There is. Therefore, when the division is changed after performing the simulation, it is necessary to recreate the interface part of the simulation model.

[0004] In addition, there is a problem that it takes time to create a simulation model and further to perform a simulation using these simulation models in order to estimate the performance, so that it takes a long time to estimate the performance.

[0005] The present invention has been made in view of the above, and an object of the present invention is to provide a performance estimating method capable of estimating the performance of an entire logical system in a short time.

Specifically, in the performance estimation of the entire logical system composed of a software unit operating on a processor and a dedicated hardware unit, a part realized by the dedicated hardware is used for a program of the entire logical system. The performance of the software part is specified by the designer, compiling the part realized by software excluding the part realized by dedicated hardware, and referring to the performance of each instruction of the generated instruction sequence from the instruction performance table. Calculate the value and refer to the performance value table of the dedicated hardware given by the designer for the performance value of the dedicated hardware part.
An object of the present invention is to provide a method for calculating the performance value of the entire logical system at high speed.

Also, the required performance is given to the entire logical system, the performance value to be realized by the dedicated hardware is calculated backward, and the feasibility of the entire logical system and the validity of separating software and hardware are determined. It is an object of the present invention to provide a method for performing a high-speed performance estimation for determination.

[0008]

In order to achieve the above object, in a method for estimating the performance of an entire logical system including a software unit operating on a processor and a dedicated hardware unit, the entire logical system is described in a programming language. In the logical system description, the part to be realized by the dedicated hardware is specified in the logical system description, and the logical system description is compiled. It estimates the overall performance.

More specifically, the performance estimation method according to the first aspect of the present invention, when estimating the performance of a logical system composed of software operating on a processor and dedicated hardware, uses a logical language described using a programming language. A step of defining a part to be processed by dedicated hardware in the logical system description from a system description and generating an intermediate code from the logical system description; and a processor from the intermediate code except for the dedicated hardware processing definition part in the intermediate code. The process of generating an instruction sequence that operates on the above. For the instruction sequence, refer to the performance value from the performance table of each instruction. For the dedicated hardware unit, refer to the performance value from the performance table of the dedicated hardware. And a step of calculating the performance of the programming language. The performance estimates of the overall logic system described in had can be performed in a short time.

According to a second aspect of the present invention, in the performance estimation method according to the first aspect, the step of generating an instruction sequence operating on the processor from the intermediate code except for the dedicated hardware processing definition unit includes controlling the dedicated hardware. The present invention is characterized in that a performance estimation including a process of controlling dedicated hardware is performed by inserting an instruction sequence to be performed, and a performance estimation can be performed with higher accuracy including an instruction sequence for controlling dedicated hardware.

According to a third aspect of the present invention, in the performance estimation method, a program for interrupt processing and a frequency of occurrence of the interrupt processing are separately defined in the logical system, and the performance estimation including the interrupt processing in the logical system is performed with higher accuracy. Specifically, a step of defining an interrupt processing program to be executed when an interrupt signal is input to a logical system to be evaluated, and a step of defining an interrupt occurrence frequency are executed. The performance of the processing program is estimated by the performance estimating method according to claim 1, and the performance of the entire logical system including the performance in the interrupt processing is estimated from the interrupt program and the interrupt frequency.

According to a fourth aspect of the present invention, there is provided a performance estimating method that defines a permissible performance value of a logical system, calculates the performance of a software unit processed by a processor other than dedicated hardware from an instruction performance table, It calculates the design index of dedicated hardware by back-calculating the permissible performance value of hardware.Specifically, the dedicated hardware of a logical system consisting of software running on a processor and dedicated hardware In estimating the permissible performance, a part to be processed by dedicated hardware in the logical system description is defined from a logical system description described using a programming language, and a processing unit is excluded from the logical system description by dedicated hardware. The process of generating intermediate code and the performance values required for the entire logical system And a step of generating an instruction sequence that operates on the processor from the intermediate code excluding the processing unit by using dedicated hardware; and for the instruction sequence, refer to a performance value from a performance table for each instruction to obtain a performance value of the instruction sequence. And calculating a permissible performance value for the dedicated hardware from the performance value required for the entire logical system and the performance value of the instruction sequence.

According to a fifth aspect of the present invention, there is provided a performance estimating method wherein a performance value allowed for a logical system and an instruction sequence for controlling dedicated hardware are defined in advance, and a dedicated hardware control instruction is generated when the instruction sequence is generated. Insert a series,
Calculate the performance of the software part processed by other than the dedicated hardware, including the instruction sequence for dedicated hardware control, from the instruction performance table and calculate the permissible performance value of the dedicated hardware in reverse order. Calculates design indices with higher accuracy. Specifically,
Except for the dedicated hardware processing definition part, when generating an instruction sequence that operates on the processor from the intermediate code, insert the instruction sequence that controls the dedicated hardware and operate on the processor including the process that controls the dedicated hardware The performance estimation of the instruction sequence to be performed is performed, and the performance value allowed for the dedicated hardware is calculated by the performance estimation method according to the fourth aspect.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The performance estimation method of the present invention will be described below based on specific embodiments. (First Embodiment) FIGS. 1 to 11 show (first embodiment) according to claims 1 and 2 of the claims.

FIG. 1 shows a procedure of a performance estimation method according to the first embodiment, which is executed by hardware shown in FIG. 3 described later. In FIG. 1, reference numeral 101 denotes a logical system description program in which the entire logical system whose performance is to be estimated is described in a programming language. An intermediate code generation process 102 generates an intermediate code from the logical system description program 101. Reference numeral 103 denotes an intermediate code generated by the intermediate code generation processing 102. 104 is a performance table of dedicated hardware, and 105 is a performance table for each instruction of the processor. Reference numeral 106 denotes a performance estimation process for calculating an instruction sequence executed by the processor and an estimated performance value from the intermediate code. 107 is a generated instruction sequence, and 108 is an estimated performance value.

The procedure of FIG. 1 will be specifically described. FIG.
Shows an example of an instruction set of a processor used in a logical system whose performance is to be estimated.

The instruction LD is a data transfer instruction for transferring data from data in a memory area specified by an address to a register A, a register B, or a register C. Instruction ST is a data transfer instruction for transferring data from register A, register B, or register C to a memory area specified by an address.

The instruction MOV is an arithmetic operation instruction for substituting a register A, a register B, a register C, or a constant value specified by a source into a register A, a register B, or a register C specified by a destination.

The instruction ADD adds a register A, a register B, a register C, or a constant value specified by a source to a register A, a register B, or a register C specified by a destination, and adds a result specified by the destination. Arithmetic operation instruction to be assigned to the register.

The instruction MUL multiplies register A, register B, register C, or a constant value specified by the source with register A, register B, or register C specified by the destination, and multiplies the result by the destination. This is an arithmetic operation instruction to be assigned to a register.

The instruction CMP compares a register A, a register B, a register C, or a constant value specified by a source with a register A, a register B, a register C, or a constant value specified by a destination. This is a comparison instruction that sets a flag and resets a comparison result flag if they are not equal. The comparison result flag is stored until the next CMP instruction is executed.

The instruction BEQ is a conditional branch instruction that causes the processing to jump to the instruction position specified by the label if the comparison result flag is set. The instruction JMP is an unconditional branch instruction that causes the processing to jump to the instruction position specified by the label.

The instruction RETI is an interrupt processing return instruction for returning the processing from the interrupt processing performed after the input of the interrupt signal to the instruction position processed before the input of the interrupt signal. The instruction NOP does nothing.

FIG. 3 shows hardware for realizing the performance estimation method according to the first embodiment.
1001 is a display device for viewing all processed information, 1002 is a keyboard for a designer to input all information and processing instructions, 1003 is a central processing unit for performing all processing, 1004 is a storage for storing each information The device stores the logical system description program, the generated intermediate code, the instruction sequence, and the estimated performance. 10
Reference numeral 05 denotes an instruction performance table in which an instruction is associated with a performance value. Reference numeral 1006 denotes a dedicated hardware table in which a dedicated hardware is associated with a performance value and describes a control instruction sequence.

FIG. 4 shows an example of the logical system description program 101 describing a logical system, which is described in C language. In this program, the part to be processed by dedicated hardware is not defined.

The logical system description program 101 shown in FIG.
Will be described. The logical system description program is 1
It is executed sequentially from the line. The first line substitutes the value 3 for the variable a. Lines 2 to 6 form a while loop, and a while loop condition is described in line 6,
In this case, when the variable a is not 0 after the execution of the fifth line, the process returns to the third line. The third line substitutes the input to the logical system for the variable b. The fourth line substitutes the multiplication result of b and a into the array variable x [a]. In the fifth line, the value of a is reduced by one. The seventh line outputs the sum of 0.5 times the array variable x [3] and the array variable x [2] and 0.25 times the array variable x [1] from the logical system.

The logical system description program of FIG. 4 is converted into an intermediate code by the intermediate processing code generation processing 102 shown in FIG. FIG. 5 shows an intermediate code created from the logical system description program of FIG.

Reference numeral 701 corresponds to the entire logical system description program of FIG. 4, and reference numeral 702 denotes an intermediate code corresponding to BLK1 of the label L2 in the intermediate code 701 in the execution unit of the while loop.

The intermediate code shown in FIG. 5 will be described. Label L1 corresponds to the first line of the logical system description program of FIG. Label L2 performs BLK1. BLK1
Corresponds to the third to fifth lines of the logical system description program of FIG.

Labels L3 to L5 correspond to the sixth line of the logical system description program in FIG. 4, and are executed from the label L6 when the variable a is 0 and the label L when the variable a is not 0.
Return to 2.

Labels L6 to L12 correspond to the seventh line of the logical system description program. Label L7 multiplies variable a by array variable x [2] and substitutes the result for variable a. Label L10 substitutes the sum of variable a and variable b for variable a. Label LB3 of BLK1 substitutes the address of array variable x [0] secured in the memory area for variable c. The label LB4 adds the value of the variable a to the variable c, and the label LB4
5 assigns the value of the variable b to the memory area at the address indicated by the variable c. The level L6 decreases the variable a by one.

For the intermediate code shown in FIG. 5, an instruction sequence is generated in the performance estimation processing 106 shown in FIG. FIG. 6 shows an instruction sequence obtained by converting the intermediate code of FIG. The instruction sequence in FIG. 6 will be described.

The label START corresponds to the label L1 of the intermediate code in FIG. AD on line 7 from label LB1
Up to D corresponds to the label L2 of the intermediate code in FIG.
That is, it corresponds to 702 of BLK1.

The label LB1 is the label LB of the intermediate code.
The MOVs in the first and third rows are the label LB3, the MUL in the fifth row is the label LB2, the ADD in the fourth row is the label LB4, the ST in the sixth row is the label LB5, and the ADD in the seventh row is the label LB6.
Corresponding to

From CMP on the eighth line to JMP on the tenth line, they correspond to L3 to L5 of the intermediate code in FIG. Label L
6 to the label END, L6 to L of the intermediate code in FIG.
Corresponding to 12.

FIG. 7 is an example of a performance table storing the performance values of the respective instructions in FIG. The value obtained by calculating the instruction sequence and the performance value with reference to the performance value of FIG. 7 is the value described in the performance value column of FIG. Since the part to be processed by the dedicated hardware is not defined, all the processing is executed on the processor. When this software is executed on the processor, the total of the performance values is 31.

FIG. 8 shows an example in which a logical system in which dedicated hardware definitions are added to the logical system description program of FIG. 4 is described. It is defined that the description on the eighth line is assigned to the HW1 as dedicated hardware on the seventh and ninth lines. FIG. 9 is a performance table of the dedicated hardware storing the performance values of the dedicated hardware and an instruction sequence for controlling the dedicated hardware. FIG. 10 shows the intermediate code generated from the logical system description program of FIG.

Reference numeral 2001 denotes the whole, and reference numeral 702 denotes the same as in FIG. L6 of 2001 is a dedicated hardware unit. This is the part of the intermediate code 701 from the labels L6 to L12. The label L6 in FIG. 10 is replaced with a dedicated hardware control instruction sequence when the instruction sequence is generated, and the general register portion of the control instruction sequence in FIG. 9 is specifically replaced with regA. As a result, the generated instruction sequence is as shown in FIG. 11, and the performance value of the entire logical system including the instruction sequence for controlling dedicated hardware can be estimated. Performance value of the entire logical system = performance value of software + Performance value of dedicated hardware = 17 + 4 = 21

As described above, according to the first embodiment of the present invention, high-speed performance estimation of a logical system including software and hardware can be performed. Although only one dedicated hardware is defined and only one performance table is shown as an example, a plurality of dedicated hardware and a plurality of performance tables are prepared, and their performance values are obtained and selected. It goes without saying that it is possible.

Although one value is used as the performance value of the instruction unit and the performance value of the dedicated hardware, a plurality of performance values are defined. For example, the area and speed are defined in the dedicated hardware.
It goes without saying that the trade-off between area and speed can be considered from a plurality of dedicated hardware.

(Second Embodiment) FIGS. 12 to 18 show
Claim 2 of the Claims (Second Embodiment)
Is shown.

FIG. 12 shows the procedure of the performance estimation method of the second embodiment, which is executed by the hardware shown in FIG. 3 as in the case of the first embodiment. FIG.
Reference numeral 1101 in FIG. 2 denotes an interrupt processing program that describes, in a programming language, an interrupt process executed when an interrupt signal is input. Reference numeral 1102 denotes interrupt generation data that defines the frequency of occurrence of an interrupt in the entire logical system and the performance value required to shift to interrupt processing when an interrupt occurs.

FIG. 13 shows an example of an interrupt processing program executed in the interrupt processing. FIG. 14 shows an intermediate code generated from the interrupt processing program of FIG.
FIG. 15 shows an instruction sequence generated from the intermediate code of the interrupt processing in FIG. 14 and the performance value of the interrupt processing program calculated from the performance value for each instruction in FIG.

FIG. 16 shows the frequency of occurrence of the interrupt processing in the logical system and the performance value of the overhead required for shifting to the interrupt processing. The same logical system description program of FIG. 8 as in the first embodiment is input to the hardware of FIG. 3, and the interrupt processing program of FIG. 13 is input. The intermediate code generation processing 102 generates the intermediate code in FIG. 5 and the intermediate code in FIG. FIG. 16 shows the interrupt frequency and the overhead of interrupt processing transition,
From the performance value of the dedicated hardware in FIG. 17 and the performance value table for each instruction in FIG.
Is generated. In FIG. 18, the portion corresponding to the label L6 is a portion processed by the dedicated hardware, and the performance value of the entire logical system excluding the interrupt is 21.

Here, from the frequency of occurrence of the interrupts in FIG. 16, the definition that one interrupt occurs for the performance value 30 is calculated, so that the logical system is calculated to have 21/30 interrupts. With respect to the performance value of the interrupt processing migration overhead of 15 and the performance value 8 which is the integration of the performance value of the interrupt processing program of FIG. 15, the logical system performance value + interrupt processing performance value × interrupt occurrence frequency = 21 + 8 × 21 / 30 = 26.6 is calculated as the performance value of the entire logical system.

As described above (according to the second embodiment), the performance estimation method according to the third aspect of the present invention enables the performance value including interrupt processing of a logical system composed of software and hardware to be processed at high speed. Performance can be estimated.

Although only one program is defined as the interrupt processing, if a plurality of interrupt programs, the frequency of occurrence of each interrupt processing, and the performance value of each interrupt processing are defined, the performance value including those interrupt processing can be obtained. Needless to say, it can be estimated.

Although only one dedicated hardware is defined and only one performance table is shown as an example, a plurality of dedicated hardware and a plurality of performance tables are prepared, and their performance values are respectively set. Needless to say, it is possible to obtain and select.

Although one value is used as the performance value of the instruction unit and the performance value of the dedicated hardware, a plurality of performance values are defined. For example, the area and the speed are defined in the dedicated hardware.
It goes without saying that the trade-off between area and speed can be considered from a plurality of dedicated hardware.

(Third Embodiment) FIG. 19 and FIG.
A third embodiment according to claims 4 and 5 of the claims will be described.

FIG. 19 shows the procedure of the method for estimating the required performance of the dedicated hardware of the (third embodiment), which is executed by the hardware shown in FIG. 3 as in the case of the (first embodiment). You.

In FIG. 19, reference numeral 1601 denotes a required performance value required for the entire logical system, which is input by the user. In this embodiment, it is assumed that the user inputs 25 as the performance value of the entire logical system. Reference numeral 1602 denotes definition data of a control instruction sequence for controlling the dedicated hardware, and a performance estimation process 160 based on the intermediate code 103, the required performance value 1601, the dedicated hardware control code 1602, and the instruction performance table 105.
3 to obtain a performance value 1604 required for the dedicated hardware.

The same logical system description program of FIG. 8 as that of the first embodiment is input to the hardware of FIG. 3, and the intermediate code of FIG. 10 is generated. The performance table for each instruction in FIG. 7 is input, the dedicated hardware control instruction sequence in FIG.
The instruction sequence shown in FIG. 11 is generated. The performance value of this instruction sequence is calculated as 17 from the performance value from the performance table of FIG.
From the required performance value 25, the dedicated hardware permitted performance value = the required performance value−the software processing performance value = 25−17 = 8, and the performance value to be assigned to the dedicated hardware can be calculated as 8.

As described above, according to the third embodiment, the performance value to be allocated to the dedicated hardware is calculated from the performance required for the entire logical system, and the index for developing the dedicated hardware is set at a high speed. Can be obtained.

Even when there are a plurality of dedicated hardware, it is possible to calculate a performance value to be assigned to the entire dedicated hardware. It goes without saying that an index of the performance value can be calculated.

[0056]

As described above, according to the first, second and third aspects of the present invention, the entire logical system is realized by dedicated hardware using a logical system description program described in a programming language. A description to be specified is specified, and the performance of the entire logical system is estimated from a performance table for each processor instruction input by a designer and a performance table of dedicated hardware.

According to the fourth and fifth aspects of the present invention, a description in which the entire logical system is realized by dedicated hardware using a logical system description program written in a programming language, and Specify the required performance value, calculate the performance value of the part processed by software from the performance table for each instruction of the processor,
It estimates the performance values allowed for dedicated hardware.

In particular, according to the configuration of the first aspect of the present invention, a logical system description program described using a programming language and a part to be processed by dedicated hardware in the logical system description program are defined and input. Generating an intermediate code from the system description program, excluding the dedicated hardware processing definition part in the intermediate code, and generating an instruction sequence operating on the processor from the intermediate code;
By referring to the performance value from the performance table for each instruction and referring to the performance value from the performance table of the dedicated hardware for the dedicated hardware unit, it is possible to estimate the performance of the entire logical system in a short time.

According to the configuration of the second aspect of the present invention, an instruction sequence for controlling the dedicated hardware is registered in the dedicated hardware performance table in advance, and when the instruction sequence is generated, the dedicated hardware control instruction sequence is inserted. However, performance estimation can be performed with higher accuracy, including the performance of instructions for dedicated hardware control.

According to the configuration of the third aspect of the present invention, it is possible to separately define the interrupt processing program and the frequency of occurrence of the interrupt processing in the logical system, and to perform the performance estimation with higher accuracy including the interrupt processing in the logical system. it can.

According to the configuration of claim 4 of the present invention, the performance value allowed for the logical system is defined, the performance of the software section processed by the processor other than the dedicated hardware is calculated from the instruction performance table, and By calculating the permissible performance value back, the design index of the dedicated hardware can be calculated.

According to the fifth aspect of the present invention, the performance value allowed for the logical system is defined, an instruction sequence for controlling the dedicated hardware is defined in advance, and the dedicated hardware control instruction sequence is generated when the instruction sequence is generated. Insert and calculate the performance of the software part processed by the processor, including the performance of dedicated hardware control instructions, from the instruction performance table, and back-calculate the permissible performance values of the dedicated hardware, A design index can be calculated.

[Brief description of the drawings]

FIG. 1 is a flowchart of a performance estimating method according to a first embodiment of the present invention.

FIG. 2 shows an example of an instruction set of a processor according to the first embodiment to the third embodiment of the present invention.

FIG. 3 is a diagram showing an example of a computer hardware configuration for realizing the performance estimation method of the present invention.

FIG. 4 is an explanatory diagram of a logical system description program according to (first embodiment) to (third embodiment) of the present invention;

FIG. 5 is an intermediate code according to the first to third embodiments of the present invention.

FIG. 6 shows an instruction sequence and a performance estimation value generated in the first embodiment of the present invention.

FIG. 7 is an explanatory diagram of a performance table for each instruction of a processor according to (first embodiment) to (third embodiment) of the present invention;

FIG. 8 is an explanatory diagram of a logical system description program in which dedicated hardware processing is defined in (first embodiment) to (third embodiment) of the present invention.

FIG. 9 is an explanatory diagram of a performance table of dedicated hardware according to the first embodiment of the present invention.

FIG. 10 is an explanatory diagram of an intermediate code according to (first embodiment) to (third embodiment) of the present invention.

FIG. 11 is an explanatory diagram of an instruction sequence and a performance estimation value generated in the first and third embodiments of the present invention.

FIG. 12 is a functional block diagram of a performance estimation function according to the second embodiment of the present invention;

FIG. 13 shows an interrupt processing program according to the second embodiment of the present invention.

FIG. 14 shows an intermediate code of an interrupt process according to the second embodiment of the present invention.

FIG. 15 shows an instruction sequence of interrupt processing and a performance value of interrupt processing according to the second embodiment of the present invention.

FIG. 16 shows an interrupt frequency definition and an interrupt transfer processing performance value according to the second embodiment of the present invention.

FIG. 17 shows performance values of dedicated hardware according to the second embodiment of the present invention.

FIG. 18 shows an instruction sequence and its performance value according to the second embodiment of the present invention.

FIG. 19 is a block diagram of a performance estimating function according to the third embodiment of the present invention;

FIG. 20 shows a control instruction sequence of dedicated hardware according to the third embodiment of the present invention.

[Explanation of symbols]

 101 Logical system description program 102 Intermediate code generation processing 103 Intermediate code 104 Dedicated hardware performance table 105 Per-instruction performance table 106 Performance estimation processing 107 Instruction sequence 108 Performance estimation value 1101 Interrupt processing program description 1102 Interrupt processing frequency definition 1601 Logical system Required performance 1602 Dedicated hardware control instruction sequence 1604 Dedicated hardware permitted performance value

Claims (5)

[Claims] When estimating the performance of a logical system composed of software running on a processor and dedicated hardware, processing is performed by a dedicated hardware in the logical system description from a logical system description described using a programming language. Defining a part to be executed and generating intermediate code from the logical system description; generating an instruction sequence operating on a processor from the intermediate code in the intermediate code excluding the dedicated hardware processing definition unit; Refers to a performance value from a performance table for each instruction, and refers to a performance value from a performance table of the dedicated hardware for a dedicated hardware unit, and calculates the performance of the entire logical system. 2. The step of generating an instruction sequence operating on a processor from an intermediate code except for a dedicated hardware processing definition unit includes a process of inserting an instruction sequence for controlling the dedicated hardware and controlling the dedicated hardware. 2. The performance estimating method according to claim 1, wherein the performance is estimated by performing the estimation. 3. A step of defining an interrupt processing program to be executed when an interrupt signal is input to a logical system to be evaluated, and a step of defining an interrupt occurrence frequency. A performance estimating method for estimating the performance by the performance estimating method according to item 1, and estimating the performance of the entire logical system including the performance in the interrupt processing from the interrupt program and the interrupt frequency. 4. Estimating the permissible performance of a dedicated hardware of a logical system composed of software operating on a processor and dedicated hardware, the logical system description is described from a logical system description described using a programming language. Defining a part to be processed by dedicated hardware and generating an intermediate code from the logical system description by removing the processing unit by the dedicated hardware; inputting a performance value required for the entire logical system; A step of generating an instruction sequence operating on a processor from the intermediate code excluding a processing unit by hardware; and a step of calculating a performance value of the instruction sequence by referring to a performance value from a performance table for each instruction for the instruction sequence. From the performance values required for the entire logical system and the performance values of the instruction sequence, A performance estimation method that calculates the permissible performance value for the software. 5. Except for a dedicated hardware processing definition part, when generating an instruction sequence operating on a processor from an intermediate code, an instruction sequence for controlling the dedicated hardware is inserted, and processing for controlling the dedicated hardware is also included. A method for estimating the performance of an instruction sequence operating on a processor, and calculating a permissible performance value for dedicated hardware by the performance estimating method according to claim 4.