JP2001285272A - Signal receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmitter which is hard to be influenced by a noise and can smoothly process data. SOLUTION: An edge detection circuit 32 detects an edge of a clock pulse CP transmitted while a gate signal S2 is active to output an edge detection pulse W1. Then a real synchronous pulse generating circuit 33 delays the edge detection pulse W1 by a delay time T2 to generate and output a real synchronous pulse W2, which is given to a data processing circuit 37 as it is via a synthesis circuit 40. However, in the case that the real synchronous pulse W2 is missing due to a transmission error of the clock pulse CP, the synthesis circuit 40 gives a pseudo synchronous pulse W3 to the data processing circuit 37 in place of the missing real synchronous pulse W2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for receiving serial data from a partner via a data transmission line.
The present invention relates to a signal receiving apparatus for synchronizing with a partner based on a start pulse and a clock pulse included in the serial data.

[0002]

2. Description of the Related Art For example, serial data transmitted and received between apparatuses performing multiplex communication is provided with a plurality of clock pulses having a predetermined period based on a start pulse at the head of the serial data. An address (position) on the serial data is specified depending on whether it is a clock pulse, and a predetermined data pulse is allocated to each address. The receiving device counts the clock pulse of the received serial data, identifies each address based on the count result, and receives information by associating each address with the data pulse.

[0003]

The number of clock pulses contained in the serial data and the cycle of the clock pulses are determined by the protocol between the devices, but a plurality of clock pulses are affected by noise or the like. Some of them may not be received and may be dropped. Then, in the conventional signal receiving apparatus, if even one clock pulse is lost, the number of clock pulses is determined not to conform to the protocol, all the received serial data is canceled, and the serial data is received again. Had become. For this reason, the signal receiving apparatus frequently generates a reception error state even with a small amount of noise, and may not be able to perform data processing smoothly.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a signal transmission device that is not easily affected by noise and can perform data processing smoothly.

[0005]

Means for Solving the Problems and Functions / Effects <Invention of Claim 1> A signal receiving apparatus according to the invention of claim 1 is a signal receiving apparatus for receiving serial data from a partner via a data transmission line. In the serial data, a start pulse arranged at the head thereof, a plurality of clock pulses of a predetermined cycle based on the start pulse, and a timing corresponding to the output information of the other party and based on each clock pulse are generated. In the signal receiving apparatus which receives the data pulse while synchronizing with the other party by the start pulse and the clock pulse, the start pulse detecting means for detecting the start pulse and the start pulse detecting means for detecting the start pulse Upon receiving the result, a predetermined period corresponding to a plurality of clock pulses after the start pulse,
Means for generating a gate signal to be turned on, wherein a gate signal corresponding to a first clock pulse is generated at a timing based on a start pulse received earlier, and a gate signal corresponding to a second or later clock pulse is generated. A gate signal generating means for generating a signal at a timing based on either a clock pulse or a start pulse received earlier, and an edge of a clock pulse received during the period provided that the gate signal is on. Edge detection means for detecting an edge detection pulse, an actual synchronization pulse generation means for generating and outputting an actual synchronization pulse obtained by delaying the edge detection pulse by a predetermined delay time, When an edge detection pulse was not output in time, a clock pulse transmission error occurred. The error detection means for outputting an error detection signal, the actual synchronization pulse generation means and the error detection means, and when no error detection signal is output, the actual synchronization pulse output from the actual synchronization pulse generation means is output as it is. On the other hand, when the error detection signal is output, the synthesizing means for generating and outputting a pseudo sync pulse instead of the real sync pulse missing due to the transmission error, and the real sync pulse and the pseudo sync pulse output from the synthesizing means. It is characterized in that a data processing means for taking in and processing a data pulse at a reference timing is provided.

According to this configuration, when the start pulse detecting means detects the start pulse, the gate signal generating means generates a gate signal corresponding to a plurality of clock pulses. Then, the edge of the clock pulse transmitted while the gate signal is on is detected by the edge detection means, and an edge detection pulse is output. Then, the real synchronizing pulse generating means generates and outputs a real synchronizing pulse obtained by delaying the edge detection pulse by a predetermined delay time, and this is directly supplied to the data processing means via the synthesizing means. However, when the clock pulse is lost due to a transmission error, the error detection means outputs an error detection signal, and the synthesizing means receiving the error transmits a pseudo synchronization pulse to the data processing means in place of the actual synchronization pulse lost due to the transmission error. give.

As described above, according to the present invention, even if some of the clock pulses are lost, the data processing means can receive the synchronization pulse as in the case where there was no loss, and the data processing means can receive the synchronization pulse. Data processing operations can be performed smoothly.

<Invention of Claim 2> In the signal receiving apparatus according to Claim 1, the synthesizing means applies pseudo sync pulses to all the actual sync pulses regardless of whether or not the actual sync pulses are missing. A pseudo pulse generating means for generating is provided, and the synthesizing means invalidates the pseudo sync pulse when the error detection signal is not output, outputs the actual sync pulse, and only when the error detection signal is output, The pseudo synchronization pulse may be validated and output.

According to a third aspect of the present invention, in the signal receiving apparatus according to the first or second aspect, the synthesizing means outputs the previously output real synchronization pulse and an output before the actual synchronization pulse. The interval between the actual synchronization pulse and the normal cycle of the clock pulse is calculated and the amount is deviated from the normal period. Thus, a feature is that a pseudo sync pulse corresponding to the next actual sync pulse is generated.

According to this configuration, even if a clock pulse is lost immediately after being received with the transmission timing of the clock pulse shifted, the effect of the shift is suppressed and the pseudo-sync pulse is generated. can do. Thereby, more stable data processing can be performed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a network for transmitting data online in a system in which a sensor S, an actuator R and the like are connected to one controller C for control. This network is, for example, a bus in which a master unit 11 arranged in the controller C and a plurality of terminal units 12 arranged for each terminal such as the sensors S and the actuators R are commonly connected to one data transmission line 10. Make a formula. The present invention is applied to these terminal units 12.

FIG. 2 shows serial data transmitted and received between the units via the data transmission line 10. One frame, which is a transmission / reception unit of the serial data, has a fixed length, and at the beginning of the one frame,
A start pulse SP is provided. This start pulse SP causes the data transmission line 10 to output 12 [V] and 24
[V] is generated in reverse, and after serial data start pulse SP, 12 [V] is generated at a constant cycle.
And a clock pulse CP that reverses between 24 [V] and
A data pulse DP that reverses between 12 [V] and 0 [V] at a predetermined timing is connected. Note that the start pulse SP has a wider pulse width than the clock pulse CP and the data pulse DP.

FIG. 3 shows a pulse receiving section provided in the terminal unit 12. In the figure, reference numeral 30 denotes a start pulse detection circuit which compares a voltage of the data transmission line 10 with a preset reference voltage (for example, a value slightly smaller than 24 V), and adjusts the voltage of the data transmission line 10 to the reference voltage. Triggered by switching from a state lower than the voltage to a state higher than the voltage, the apparatus operates for a certain period of time, and detects a start pulse SP when the width of a pulse received during the certain period is equal to or greater than a predetermined value. The signal S1 (see FIG. 4) is output.

Reference numeral 31 denotes a gate signal generation circuit which generates a gate signal S2 (see FIG. 4) having a predetermined period T3 (see FIG. 4) corresponding to each clock pulse CP. Also,
The gate signal S2 forms a pulse signal that is turned on only for a gate period T1 (see FIG. 4) corresponding to the width of the clock pulse CP.

Reference numeral 32 denotes an edge detection circuit, which detects an edge of the clock pulse CP received during that time on condition that the gate signal S2 is on, and generates an edge detection pulse W1. More specifically, while the gate signal S2 is on, the edge detection circuit 32 changes the voltage of the data transmission line 10 from a state lower than a preset reference voltage (for example, a value slightly smaller than 24 V) to a state higher than the reference voltage. The edge detection signal is output at the timing of switching to.

Reference numeral 33 denotes an actual synchronization pulse generation circuit,
It takes in the edge detection pulse W1, generates and outputs an actual synchronization pulse W2 obtained by delaying the edge detection pulse W1 by a predetermined delay time T2 (see FIG. 4).

Reference numeral 34 denotes an error detection circuit which is connected to the gate signal generation circuit 31 and the edge detection circuit 32. For example, an edge detection pulse W1 is output from the edge detection circuit 32 during the gate period T1 when the gate signal S2 is turned on. If not, it is determined that a transmission error of the clock pulse CP has occurred, and an error detection signal is output.

Reference numeral 35 denotes a pseudo-pulse generation circuit, which generates pseudo-sync pulses W3 for all the real sync pulses W2 regardless of whether or not the real sync pulse W2 is missing. Specifically, the clock pulse CP is based on the synchronization pulses W2 and W3 output from the synthesis circuit 40 described later.
At a timing when a regular interval T3 (see FIG. 2) is left between them, the pseudo sync pulse W corresponding to the next actual sync pulse W2
3 has been generated.

Reference numeral 36 denotes a synthesizing circuit which receives outputs from the real synchronization pulse generation circuit 33, the error detection circuit 34, and the pseudo pulse generation circuit 35, and always outputs the real synchronization pulse from the real synchronization pulse generation circuit 33. While W2 is output as it is, when the error detection circuit 34 outputs an error detection signal, the pseudo synchronization pulse W3 from the pseudo pulse generation circuit 35 is output as it is. The pulse synthesizing circuit 36 and the pseudo pulse generating circuit 35 constitute a synthesizing circuit 40 as synthesizing means of the present invention.

Reference numeral 37 denotes a data processing circuit, which includes both real and pseudo synchronization pulses W2 and W2 output from the synthesis circuit 40.
The data pulse DP is fetched and processed while synchronizing based on W3.

Next, the operation of this embodiment having the above configuration will be described. When the master unit 11 switches the potential of the data transmission line 10 to generate a one-frame serial signal (see FIG. 2) on the data transmission line 10,
Start pulse SP arranged at the beginning of the serial signal
Is taken into each terminal unit 12. Then, the start pulse SP is supplied to the start pulse detection circuit 3
0, the start pulse detection signal S1 becomes
The signal is supplied to the gate signal generation circuit 31.

The gate signal generation circuit 31 generates a gate signal S2 for a clock pulse CP transmitted next to the start pulse SP based on the start pulse detection signal S1, and uses the gate signal S2 as a mask signal to detect an edge. To the circuit 32. Then, the edge detection circuit 32
Detects the edge of the clock pulse CP when the voltage of the data transmission line 10 exceeds a predetermined reference value during the period under the condition of the gate signal S2, and outputs the edge detection pulse W1 to the actual synchronization pulse generation circuit. 33 and an error detection circuit 34.

The actual synchronizing pulse generation circuit 33 delays the edge detection pulse W1 by a delay time T2 and outputs the same as an actual synchronizing pulse W2. The error detection circuit 34
Since the edge detection pulse W1 is received during the gate period T1 when the gate signal S2 is turned on, no error detection signal is output.

The real synchronizing pulse W2 output from the real synchronizing pulse generation circuit 33 is output to the pulse synthesizing circuit 3 of the synthesizing circuit 40.
6, the pulse synthesizing circuit 36 outputs the received actual synchronizing pulse W2 from the synthesizing circuit 40 as it is.

Then, the data processing circuit 37 receives the actual synchronizing pulse W2, and receives the actual synchronizing pulse W2.
3) In addition to counting the data, the data pulse DP is taken in based on the received timing, and processing such as discrimination between ON and OFF is performed. Then, predetermined data processing is performed by associating the address on the serial data specified by the count result of the synchronization pulse W2 (W3) with the on / off content of the data pulse.

The real synchronizing pulse W2 output from the synthesizing circuit 40 is also supplied to a pseudo pulse generating circuit 35 provided in the synthesizing circuit 40. Then, based on the received actual synchronization pulse W2, the circuit 35 generates a pseudo synchronization pulse corresponding to the next actual synchronization pulse W2 at a timing when a regular period T3 (see FIG. 4) between the clock pulses CP is opened. W
3 is generated.

Further, the actual synchronizing pulse W2 output from the synthesizing circuit 40 is also applied to the gate signal generating circuit 31.
Then, the circuit 31 generates and outputs a gate signal S2 corresponding to the next clock pulse CP at a timing when a regular period T3 between the clock pulses CP is opened with reference to the received actual synchronization pulse W2.

Next, on condition that the gate signal S2 is turned on, the edge of the next captured clock pulse CP is detected by the edge detection circuit 32, and the edge detection pulse W1 is output to the circuit 33 and the circuit similarly to the above. 34, the synchronizing circuit 40 outputs the actual synchronization pulse W2 in the same manner as described above. At this time, the pulse synthesizing circuit 36 of the synthesizing circuit 40 outputs the real synchronizing pulse W
2 as well as the pseudo-sync pulse W3 generated by the pseudo-pulse generation circuit 35, but since no error detection signal is output from the error detection circuit 34, the pseudo-sync pulse W3 is invalidated and the actual synchronization pulse W2 is Synthesis circuit 4
Output from 0.

Now, as shown in FIG. 4, when one of the plurality of clock pulses CP cannot be received due to the influence of noise or the like, the following occurs.

If the clock pulse CP is not received, the edge detection pulse W1 is not output even though the gate signal S2 is turned on.
Outputs an error detection signal due to the lack of the clock pulse CP. Then, the pulse synthesizing circuit 36 receiving this error detection signal validates the pseudo synchronizing pulse W3 from the pseudo pulse generating circuit 35 and outputs it from the synthesizing circuit 40. As a result, the data processing circuit 37 receives the pseudo synchronization pulse W3 from the synthesis circuit 40 in the same manner as the real synchronization pulse W2, and takes in the data pulse DP based on the pseudo synchronization pulse W3 for processing. Further, the pseudo-sync pulse W3 is also captured by the gate signal generation circuit 31 and the pseudo-pulse generation circuit 35, and the circuits 31 and 35 operate in the same manner as when the real synchronization pulse W2 is captured.

As described above, according to the present embodiment, even when some of the clock pulses CP are missing, the data processing circuit 37 outputs the synchronization pulse as if there was no lack of the clock pulse CP. I can receive it. Thereby, the data processing operation of the data processing circuit 37 can be performed smoothly. Note that, when the error detection circuit 34 continuously outputs the error detection signal for a predetermined number of times or more, for example, a warning light may be turned on or data communication may be performed in a middle stage.

<Second Embodiment> This embodiment is shown in FIG. 5, and is different from the first embodiment mainly in the configuration of the pseudo pulse generation circuit. That is, the pseudo pulse generation circuit 35 of the first embodiment generates the pseudo synchronization pulse W3 for all the real synchronization pulses W2 regardless of the presence or absence of the real synchronization pulse W2. The pseudo pulse generation circuit 35X is configured to generate and output a pseudo synchronization pulse W3 in place of the missing actual synchronization pulse W2 only when the error detection circuit 34 outputs an error detection signal. With such a configuration, the same operation and effect as those of the first embodiment can be obtained.

<Third Embodiment> This embodiment is shown in FIG. 6, and is different from the first embodiment mainly in the configuration of the combining circuit. That is, the synthesizing circuit 40Y of the present embodiment includes the count circuit 38 and the correction circuit 39. The count circuit 38 measures the time (see T5 in FIG. 4) from the start of the gate period T1 when the gate signal S2 is turned on (see P1 in FIG. 4) to the timing when the edge detection circuit 32 outputs the edge detection pulse W1. . Here, for example, when the clock pulse CP is transmitted at regular timing, the gate signal generation circuit 31 of the present embodiment operates in the gate period T.
At the timing when half of 1 has elapsed, the edge detection pulse W
The gate signal S2 is generated so that 1 is output.
The correction circuit 39 calculates the amount of deviation between the normal output timing of the edge detection pulse W1 and the output timing of the actually output edge detection pulse based on the measurement result of the count circuit 38, and generates a pseudo pulse generation circuit. 35Y. Then, the same circuit 35X performs the next actual timing at the timing when the regular cycle T3 is opened from the previously output actual synchronization pulse W2 and at the timing when the deviation amount detected by the count circuit 38 is corrected. A pseudo sync pulse W3 corresponding to the sync pulse W2 is generated.

With this configuration, even if the clock pulse CP is lost immediately after being received with the transmission timing of the clock pulse CP shifted,
It is possible to generate and output the pseudo sync pulse W3 in which the influence of the shift is suppressed. Thereby, more stable data processing can be performed.

<Fourth Embodiment> This embodiment is a modification of the second and third embodiments shown in FIG. 7, and is a pseudo-pulse generation circuit 35Z of this embodiment.
Is similar to the pseudo pulse generation circuit 35X of the second embodiment, and generates and outputs a pseudo synchronization pulse W3 in place of the missing actual synchronization pulse W2 only when the error detection circuit 34 outputs an error detection signal. The output of the correction circuit 39 of the third embodiment is given to the pseudo pulse generation circuit 35Z. With such a configuration, the same operation and effect as those of the second and third embodiments can be obtained.

<Other Embodiments> The present invention is not limited to the embodiments. For example, the embodiments described below are also included in the technical scope of the present invention. Various changes can be made without departing from the scope of the invention.

(1) In the first embodiment, an example is shown in which the data transmission apparatus according to the present invention is connected to a bus-type network, but the data transmission apparatus according to the present invention is connected to a star-type, tree-type, or loop-type network. A transmission device may be connected.

(2) In the first embodiment, the gate signal generation circuit 31 generates the gate signal S2 based on the output of the synthesis circuit 40. However, the gate signal generation circuit receives the output from the synthesis circuit. Instead, based on only the start pulse detection signal from the start pulse detection circuit, the protocol may be such that the gate signal is generated in correspondence with the transmission timing of each clock pulse obtained with reference to the start pulse. .

[Brief description of the drawings]

FIG. 1 is a wiring diagram of a network according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram of serial data transmitted and received.

FIG. 3 is a block diagram illustrating a configuration of a signal receiving device.

FIG. 4 is a time chart showing serial data, an edge detection pulse, and the like.

FIG. 5 is a block diagram illustrating a configuration of a signal receiving apparatus according to a second embodiment.

FIG. 6 is a block diagram illustrating a configuration of a signal receiving device according to a third embodiment.

FIG. 7 is a block diagram illustrating a configuration of a signal receiving apparatus according to a fourth embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Data transmission line 12 ... Terminal unit (signal receiving apparatus) 30 ... Start pulse detection circuit (start pulse detection means) 31 ... Gate signal generation circuit (gate signal generation means) 32 ... Edge detection circuit (edge detection means) 33 ... Real synchronization pulse generation circuit (real synchronization pulse generation means) 34 ... Error detection circuit (error detection means) 35, 35X, 35Z ... Pseudo pulse generation circuit (pseudo pulse generation means) 36 ... Pulse synthesis circuit 37 ... Data processing circuit (Data Processing means) 38 count circuit 39 correction circuit 40, 40Y synthesis circuit (synthesis means) CP clock pulse DP data pulse S2 gate signal SP start pulse T1 gate period T2 delay time W1 edge detection pulse W2: actual synchronization pulse W3: pseudo synchronization pulse

Claims (3)

[Claims] 1. A signal receiving apparatus for receiving serial data from a partner via a data transmission line, wherein the serial data includes a start pulse arranged at a head thereof and a predetermined pulse based on the start pulse. A plurality of clock pulses having a period and a data pulse corresponding to the output information of the other party and generated at a timing based on each clock pulse are included, and the start pulse and the clock pulse synchronize with the other party. In a signal receiving device for receiving the data pulse while aiming, a start pulse detecting means for detecting the start pulse, receiving a detection result from the start pulse detecting means, corresponding to the plurality of clock pulses after the start pulse Means for generating a gate signal to be turned on for a predetermined period, The gate signal corresponding to the clock pulse is generated at a timing based on the start pulse received earlier, and the gate signal corresponding to the second and subsequent clock pulses is generated based on the clock pulse received earlier or the start signal. A gate signal generating means for generating at a timing based on one of the pulses, and an edge detection for outputting an edge detection pulse by detecting an edge of a clock pulse received during the gate signal on condition that the gate signal is on. Means for generating and outputting an actual synchronization pulse obtained by delaying the edge detection pulse by a predetermined delay time; and the edge detection means not outputting an edge detection pulse within a predetermined allowable time. When the clock pulse transmission error occurs, an error detection signal is output. Error detecting means, which is connected to the real synchronization pulse generating means and the error detecting means, and outputs the real synchronization pulse output from the real synchronization pulse generating means as it is when the error detection signal is not output. When the error detection signal is output, synthesizing means for generating and outputting a pseudo sync pulse in place of the real sync pulse missing due to the transmission error, and the real sync pulse output from the synthesizing means and And a data processing means for receiving and processing the data pulse at a timing based on the pseudo sync pulse. 2. The synthesizing unit includes a pseudo pulse generating unit that generates the pseudo synchronizing pulse for all the real synchronizing pulses regardless of whether or not the real synchronizing pulse is missing. When the error detection signal is not output, the pseudo synchronization pulse is invalidated, the actual synchronization pulse is output, and only when the error detection signal is output, the pseudo synchronization pulse is enabled and output. The signal receiving device according to claim 1, wherein the signal receiving device is configured to perform the following. 3. The method according to claim 1, wherein the synthesizing unit calculates an amount by which an interval between the previously output real synchronization pulse and the previously output real synchronization pulse deviates from a normal cycle of the clock pulse. A pseudo-sync pulse corresponding to the next real sync pulse is generated at a timing at which the regular cycle is opened from the previously output real sync pulse, and at a timing at which the correction for the shift amount is performed. The signal receiving device according to claim 1 or 2, wherein