JP2001285271A - Signal receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal receiver that can surely detect a synchronizing signal. SOLUTION: On the occurrence of a noise pulse NP just before a start pulse SP, a 1st discrimination circuit 32 having been in a standby state is active only for a fixed period with an edge detection signal W11 relating to the noise pulse NP. However, since the pulse width of the noise do not reach a prescribed width or over, no synchronous pulse detection signal is outputted. Then a 2nd discrimination circuit 35 reaching a standby state next receives an edge detection signal W12 relating to the start pulse SP and is activated to provide an output of a synchronous pulse signal. Then an OR circuit 37 detects timing when the synchronous pulse detection signal is outputted as a synchronous timing to be synchronized with the timing of an opposite party.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for receiving serial data from a partner via a data transmission line.
The present invention relates to a signal receiving apparatus that synchronizes with a partner based on a synchronization pulse included in the serial data.

[0002]

2. Description of the Related Art For example, as an example of a synchronizing signal included in serial data, 1 which is a structural unit of serial data is used.
At the beginning of the frame, a start pulse is provided.
Further, the conventional signal receiving apparatus includes, for example, an edge detection circuit and a start pulse discrimination circuit. When the edge detection circuit detects the leading edge of the pulse, the start pulse discrimination circuit operates for a predetermined period. When the width of the pulse received during that period is equal to or greater than a predetermined value, the detection signal is output as a start pulse is detected. Then, based on this detection signal, synchronization with the other party is achieved. Further, when the start pulse judging means ends the judging operation for the predetermined period, the start pulse judging unit enters a pause period in order to perform a reset operation.

By the way, in the above-mentioned conventional signal receiving apparatus, once the start pulse discriminating circuit detects an edge, the start pulse discriminating circuit must continue the discriminating operation for the predetermined period from that point in time. Therefore, even if a new edge is detected during the discrimination operation, the discrimination operation based on the edge cannot be performed. Therefore, as shown in FIG.
If a pulse NP due to noise (hereinafter, referred to as “noise pulse NP”) is applied immediately before P, the start pulse determination circuit performs the determination operation by detecting the edge of the noise pulse NP (see P10 in FIG. 7). Is started, and during the determination operation (see T10 in FIG. 7), the edge detection (refer to P11 in FIG. 7) relating to the start pulse SP is performed. Therefore, the determination operation for the start pulse SP is not performed. There is a problem that the start pulse SP cannot be detected.

[0003] The present invention has been made in view of the above circumstances, and has as its object to provide a signal receiving apparatus capable of reliably detecting a synchronization signal.

[0004]

In order to achieve the above object, a signal receiving apparatus according to the first aspect of the present invention, when receiving serial data from a partner via a data transmission line, In the signal receiving device for synchronizing with the other party based on the synchronization pulse included in the serial data, the signal is transmitted from the other party based on the reversal of the magnitude relationship between the voltage of the data transmission line and a preset reference voltage. Edge detecting means for detecting an edge of the detected pulse and outputting an edge detection signal; and a plurality of determining means connected to the edge detecting means, wherein the plurality of determining means wait for the edge detection signal at different timings. The determination means that has received the edge detection signal in the standby state operates only for a certain period corresponding to the width of the synchronization pulse and detects the synchronization pulse. The synchronization pulse detection signal is output when a synchronization pulse is detected, and the timing at which one of the plurality of determination means outputs the synchronization pulse detection signal is determined by the other party. It is characterized in that a synchronization detecting means for detecting as a synchronization timing with the control signal is provided.

According to this configuration, when a pulse is transmitted on the data transmission line and the edge detection signal is output from the edge detection means, one of the determination means in the standby state at this time is used for a predetermined period. And the next one of the determination means is set in the standby state. If the pulse received here is a pulse for synchronization, the discriminating means that operates first,
A synchronization pulse is detected by detecting a synchronization pulse, and in response to this, the synchronization detection means detects a synchronization timing. Then, synchronization with the other party is achieved at this synchronization timing.

[0006] When a pulse due to noise occurs immediately before the pulse for synchronization, the discriminating means in the standby state uses the edge detection signal relating to the pulse due to noise to generate a signal.
Operate only for a certain period. However, since the pulse width of the noise does not exceed a predetermined value, no synchronization pulse detection signal is output. However, the discriminating unit that has entered the standby state after the next operates in response to the edge detection signal related to the synchronization pulse, detects the synchronization pulse, and outputs the synchronization pulse detection signal. Then, the timing at which the synchronization pulse detection signal is output is detected by the synchronization detection means as the synchronization timing, and synchronization with the other party is achieved. Therefore, even if a pulse due to noise occurs immediately before the synchronization pulse, the recognition of the synchronization pulse does not fail as in the related art.

[0007] Further, the discriminating means is provided for a predetermined period of time.
A configuration may be adopted in which a synchronizing pulse detection signal is output when the time when the pulse peak value exceeds a predetermined value is longer than half of a certain period (invention of claim 2).

Further, a gate means is provided between the edge detecting means and the plurality of discriminating means, and the gate means is always open so that an edge detection signal is supplied to the discriminating means. When the means detects the synchronization timing, if it is configured to close for a pause period corresponding to a predetermined interval between synchronization pulses (the invention of claim 3), after the determination means detects the synchronization pulse, It is possible to prevent a situation in which the determination unit operates one by one based on the edge of a pulse due to noise or the like.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIG. FIG. 1 shows a network for transmitting data online in a system in which a sensor S, an actuator R and the like are connected to one controller C for control. This network includes, for example, the master unit 11 arranged in the controller C.
And a plurality of terminal units 12 arranged for each terminal such as each sensor S, actuator R, and the like, in a bus system in which one data transmission line 10 is commonly connected. And
The present invention is applied to these terminal units 12.

FIG. 2 shows serial data transmitted and received between the units via the data transmission line 10. One frame, which is a transmission / reception unit of the serial data, has a fixed length, and at the beginning of the one frame,
A start pulse SP is provided. The start pulse SP corresponds to the synchronization pulse of the present invention, and the interval between the start pulses SP is inevitably equal to or longer than the time required to transmit at least one frame. This corresponds to the period (T2). Also,
The start pulse SP sets the data transmission line 10 to 12
A clock pulse CP which is generated by inverting between [V] and 24 [V] and which is inverted between 12 [V] and 24 [V] at a constant period after the start pulse SP in the serial data. And 12 [V] and 0 [V] at predetermined timing
And a data pulse DP that is inverted between the two. Note that the start pulse SP is the clock pulse C
P, the pulse width is wider than the data pulse DP.

FIG. 3 shows a pulse receiving section provided in the terminal unit 12. In the figure, reference numeral 30 denotes an edge detection circuit, which is connected to a voltage of the data transmission line 10 and a preset reference voltage (for example, 12
V is slightly smaller than V), and the data transmission line 1
When the voltage of 0 is switched from a state smaller than the reference voltage to a state larger than the reference voltage, the edge of the pulse transmitted from the other party is detected.

Reference numeral 31 denotes a gate circuit, which constantly outputs an ON signal, and receives a turn-on of an output of an OR circuit 37 to be described later, and receives a pause period T2 (corresponding to an interval between start pulses SP). Only the output signal is turned off (see FIG. 4).

Reference numeral 32 denotes a first discriminating circuit, which receives the outputs of the edge detecting circuit 30 and the gate circuit 31 through the first AND circuit 33, and provides the edge signal on condition that the output of the gate circuit 31 is on. When the detection circuit 30 outputs the edge detection signal W1 (see FIG. 4), the first discrimination circuit 32 uses this as a trigger to cause the first discrimination circuit 32 to perform a predetermined period T1 (see FIG. 4).
Only works. Then, the first discriminating circuit 32, when the time during which the peak value of the received pulse exceeds the predetermined value in the certain period T1 is equal to or more than half of the certain period T1,
The synchronization pulse detection signal W2 (see FIG. 4) is output to an OR circuit 37 described later.

Reference numeral 34 denotes a delay circuit, which is always
The output signal is off, and the output is turned on for a predetermined period T4 after a predetermined delay time T3 (see FIG. 4) from the start timing of the first determination circuit 32. In the present embodiment, the period T4 is set to end at the same time as the certain period T1 of the first determination circuit 32.

Numeral 35 denotes a second discriminating circuit which receives the outputs of the edge detecting circuit 30 and the delay circuit 34 through the second AND circuit 36, and provides an edge signal on condition that the output of the delay circuit 34 is on. When the detection circuit 30 outputs the edge detection signal W1 (see FIG. 4), the second discrimination circuit 35 operates only for a certain period by using this as a trigger. Then, the second determination circuit 35 is provided with the first determination circuit 3.
Similarly to 2, the time when the peak value of the pulse exceeds the predetermined value,
When the period becomes equal to or more than half of the certain period T1, the synchronization pulse detection signal W4 (see FIG. 4) is output to the OR circuit 37 described later.

Reference numeral 37 denotes an OR circuit serving as a synchronization timing detecting means, which calculates and outputs the logical sum of the output of the first discriminating circuit 32 and the output of the second discriminating circuit 35.

Next, the operation of this embodiment having the above configuration will be described. Before a pulse is generated on the data transmission line 10, the gate circuit 3
Since the output from 1 to the first AND circuit 33 is on and the output from the delay circuit 34 to the second AND circuit 36 is off, only one of the first discriminating circuits 32 of the two discriminating circuits 32 and 35 detects an edge. It is in a standby state in which the signal W1 can be taken. At this time, both discriminating circuits 32,
Since both outputs of the circuit 35 are off, the output of the OR circuit 37 receiving these outputs is also off.

Next, when a pulse is generated on the data transmission line 10, the edge detection circuit 30 is generated based on the pulse.
Output the edge detection signal W1. Where the pulse is
Instead of an ideal rectangular wave as shown in FIG. 5, a rectangular wave distorted as shown in FIG. 6 due to the influence of noise is taken into the terminal unit 12, and the rising portion of the pulse and the reference Cross point P1 with voltage VRF
At the timing shown in FIG. 6, the edge detection signal W1 is output.

Then, the edge detection signal W1 is fetched only through the first AND circuit 33 to the first determination circuit 32 in the standby state, and the output timing of the edge detection signal W1 is changed as shown in FIG. The first discriminating circuit 32 operates only for a certain period T1 at the start. Here, the first determination circuit 32 obtains the total time (S1 + S2 + S3) in which the peak value of the pulse captured during the certain period T1 exceeds the reference value VRF, and this total time is more than half of the certain period T1. At this time, it is determined that the start pulse SP has been received. Then, a synchronization pulse detection signal W2 (see FIG. 4) is output at the end timing of the certain period T1. In the present embodiment, in the first determination circuit 32, the reference voltage VRF to be compared with the peak value of the pulse and the reference voltage VRF for the edge detection circuit 30 to detect an edge are the same, but both are the same. It may be different.

When the output of the first determination circuit 32 is turned on, the output of the OR circuit 37 receiving the output is turned on (W31 in FIG. 4).
), And the terminal unit 12 synchronizes with the master unit 11 based on the output of the OR circuit 37. In response to the output of the OR circuit 37 being turned on, the gate circuit 31 pauses T2 until the next start pulse SP is sent according to the protocol (see FIG. 4).
Just turn off the output. Thereby, the first AND circuit 3
3 is closed, the edge detection signal W1 is not supplied to the first discriminating circuit 32, and further to the second discriminating circuit 35, and after detecting the start pulse SP, it is determined based on the clock pulse and the edge of the pulse due to the data pulse or noise. Thus, it is possible to prevent a situation in which the determination circuits 32 and 35 operate one by one.

Now, as shown on the left side of FIG. 4, the case where the noise pulse NP occurs immediately before the start pulse SP is as follows. First, when the edge detection signal W11 (see FIG. 4) relating to the noise pulse NP is output, the first discriminating circuit 32, which was in the standby state at this time, operates for a certain period T1.
Only works. However, the time during which the noise pulse NP received during the certain period T1 exceeds the reference voltage VRF does not become more than half of the certain period T1 and the first determination circuit 3
2 does not output a synchronization pulse detection signal.

Here, the delay circuit 34 turns on the output signal after a delay time T3 from the start of the first determination circuit 32. Thus, the second determination circuit 35 enters a standby state. Then, when the edge detection signal W12 (see FIG. 4) relating to the start pulse SP is output next to the noise pulse NP, the edge detection signal W12 is taken into the second determination circuit 35 in the standby state, and the circuit 35 is operated for a certain period. It operates only for T1.
The time during which the peak value of the start pulse SP exceeds the reference voltage VRF is more than half of the fixed period T1, and at the end of the fixed period T1, the synchronization pulse detection signal W4
Is output. Then, the OR circuit 37 outputs the detection signal W
4 and turns on the output. Based on the output of the OR circuit 37, the terminal unit 12
1 is synchronized with

As described above, according to the present embodiment, even if the noise pulse NP occurs immediately before the start pulse SP, the noise pulse NP is not affected by the noise pulse NP.
The start pulse SP for synchronization can be reliably detected.

<Other Embodiments> The present invention is not limited to the above embodiments. For example, the following embodiments are also included in the technical scope of the present invention.
In addition to the following, various changes can be made without departing from the scope of the invention. (1) In the first embodiment, an example in which the data transmission device according to the present invention is connected to a bus network is described. However, the data transmission device according to the present invention is connected to a star, tree, or loop network. May be connected.

(2) In the above-described embodiment, the configuration provided with the two discriminating circuits 32 and 35 is shown. However, a configuration provided with three or more discriminating circuits may be used so that they are sequentially activated. Good. By doing so, even if a plurality of noise pulses are generated before the start pulse, the start pulse can be reliably detected.

(3) If the plurality of discriminating circuits are set to the standby state at different timings, it is not necessarily required that
A plurality of discriminating circuits need not be sequentially activated,
For example, a configuration in which two determination circuits alternately enter a standby state is also included in the technical scope of the present invention.

(4) In the above-described embodiment, the configuration in which the synchronization timing of the start pulse SP is used as the synchronization pulse is exemplified. However, for example, in order to achieve the synchronization timing of the clock pulse CP, the present invention is applied. Is also good.

[Brief description of the drawings]

FIG. 1 is a wiring diagram of a network according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram of serial data transmitted and received.

FIG. 3 is a block diagram illustrating a configuration of a signal receiving device.

FIG. 4 is a time chart showing received pulses, edge detection signals, and the like.

FIG. 5 is a conceptual diagram showing an ideal pulse.

FIG. 6 is a conceptual diagram showing an actual pulse.

FIG. 7 is a conceptual diagram illustrating a conventional process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Data transmission line 12 ... Terminal unit (signal receiving apparatus) 30 ... Edge detection circuit (edge detection means) 31 ... Gate circuit (gate means) 32 ... 1st discrimination circuit (discrimination means) 33 ... 1st AND circuit (gate means) 34 ... Delay circuit 35 ... Second discriminating circuit (discriminating means) 36 ... Second AND circuit (gate means) 37 ... OR circuit (synchronous timing detecting means) SP ... Start pulse (pulse for synchronization) T1 ... Constant period T2 ... Rest period VRF: Reference voltage W1: Edge detection signal W2, W4: Synchronous pulse detection signal

Claims (3)

[Claims] 1. A signal receiving apparatus which, upon receiving serial data from a partner via a data transmission line, synchronizes with the partner based on a synchronization pulse included in the serial data. A line voltage, based on inversion of a magnitude relationship between a preset reference voltage, edge detection means for detecting an edge of a pulse transmitted from the other party and outputting an edge detection signal, and the edge detection means A plurality of judging means connected to each other, wherein the plurality of judging means are in a standby state for waiting for the edge detection signal at different timings, and the judging means having received the edge detection signal in the standby state is used for the synchronization. It operates only for a certain period corresponding to the width of the pulse, determines whether or not the synchronization pulse is detected, and detects the synchronization pulse. A synchronization pulse detection signal; and a synchronization detection unit configured to detect a timing at which one of the plurality of determination units outputs the synchronization pulse detection signal as a synchronization timing with the other party. A signal receiving apparatus characterized in that: 2. The method according to claim 1, wherein the determining unit includes:
2. The signal receiving device according to claim 1, wherein the synchronizing pulse detection signal is output when the time when the peak value of the pulse exceeds a predetermined value is longer than half of the predetermined period. 3. A gate means is provided between the edge detecting means and the plurality of discriminating means, and the gate means is always opened so that the edge detecting signal is supplied to the discriminating means. 3. The signal receiving apparatus according to claim 1, wherein when the synchronization detecting means detects a synchronization timing, the signal is closed only during a pause period corresponding to a predetermined interval between the synchronization pulses. .