JP2001274777A - Digital signal transmission method, device and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal transmission method, a device and a system with superior response performance. SOLUTION: Data blocks B are provided to one frame, that is a component of transmitted/received serial data, and bit groups of the first half and the latter half of each data block B are mutually inverted to each other. Then a prescribed unit 31 of a receiver side receives prescribed bits of the first half of the data block B and also receives bits corresponding to the received bits, after a lapse of a transmission time T4 equivalent to a half period of the data block B and compares them and whether the unit 31 receives information of the data correctly is detected. Thus, the time required to detect whether the information is correctly sent/received can be reduced to the transmission time of the data blocks B included in one frame or below from the transmission time of one frame that has been required for the conventional system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital signal transmission system, apparatus and system.

[0002]

2. Description of the Related Art As a method of transmitting a digital signal between a plurality of data transmission devices, for example, information on each device is divided by time, and as shown in FIG. There is a method of forming one frame of serial data by connecting information I in a predetermined order. Conventionally, in such a serial digital signal transmission method, as shown in FIG. 1, after transmitting one frame of serial data, one frame of serial data for checking corresponding to the serial data is transmitted. The receiving side compares the two serial data to check whether the data has been transmitted correctly. Specifically, since the input / output data of the predetermined device is allocated to the predetermined address of the serial data, the receiving side fetches the data of the predetermined address A of the first serial data as shown in FIG. Then, after the transmission time T3 of one frame, the data at the predetermined address A of the check serial data is fetched, and it is checked whether both data correspond correctly.

[0003]

However, in recent years,
There is a tendency for data transmission to be performed between more devices. For this reason, one frame of serial data specified by the communication protocol is becoming longer. In the above-described conventional digital signal transmission method, a transmission time T3 of one frame is required for checking data. Therefore, a response time from transmission of one device to activation of the other device is required. However, there is a tendency that the number of points increases with the increase in the number of points, and a decrease in responsiveness has been a problem.

The serial data includes a clock pulse for synchronization (not shown) in addition to a data pulse for information transmission (not shown). In a conventional data transmission system, the clock pulse is not used. The clock pulse occupies approximately half of one frame length of the serial data because the data pulse is distributed in the serial data so as to have a high period and the data pulse is arranged between the clock pulses. Data transmission efficiency was poor.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital signal transmission method, apparatus, and system having excellent responsiveness.

[0006]

<Means for Solving the Problems and Functions / Effects><Invention of claim 1> A digital signal transmission system according to the invention of claim 1 is a unit of serial data for performing multiplex communication between a plurality of transmission devices. In a digital signal transmission system in which a plurality of input / output data groups corresponding to a plurality of transmission devices are arranged for each frame, the input / output data group is divided into a data bit string having a predetermined number of bits, and A feature is that a plurality of data blocks including a data bit string and check bits are provided in one frame by connecting a check bit string for checking whether or not the data bit string has been transmitted correctly to each data bit string.

According to this configuration, it is checked whether the data has been correctly transmitted by comparing the first half data bit string and the second half check bit string in each of the plurality of data blocks provided in one frame of serial data. can do. Thereby, the time required to check whether or not the data has been transmitted correctly can be calculated from the conventional transmission time of one frame (see time T3 in FIG. 6).
The transmission time of a plurality of data blocks included in one frame (see time T1 in FIG. 5A) can be shortened. Therefore, responsiveness of data transmission is improved.

A digital signal transmission device according to a second aspect of the present invention is a digital signal transmission device which is connected to a plurality of data transmission lines in common, and wherein the potential of the data transmission line is changed. By switching, serial data is generated, and an input / output data group of each digital signal transmission device is placed for each frame which is a constituent unit of the serial data. Is divided into a data bit string of a predetermined number of bits to generate a data pulse string corresponding to the data bit string, and a check pulse string for checking whether or not the data pulse string has been transmitted correctly. A check pulse generation circuit;
Timing control means for controlling the operation timing of the data pulse generation circuit and the check pulse generation circuit so that a plurality of data blocks each comprising a data pulse train and a check pulse train corresponding to each other are provided in one frame. However, it has features.

According to this structure, the timing control means controls the operation timing of both the data and check pulse generation circuits, and a plurality of data blocks are provided in one frame of the serial data. , A data pulse train and a check pulse train are arranged. Accordingly, in each data block, after receiving the data pulse train in each data block, the corresponding check pulse train is received after a lapse of half the transmission time of the data block, and the data train is correctly transmitted by comparing them. Is detected. Therefore, the time required to detect whether or not data has been correctly transmitted is determined by comparing the conventional transmission time of one frame (see time T3 in FIG. 7) with the transmission of a plurality of data blocks contained in one frame. The time can be reduced to the time (see time T1 in FIG. 5A). Therefore, responsiveness of data transmission is improved.

According to the third aspect of the present invention, the timing of operation is controlled by the timing control means, and a clock pulse for synchronizing with each digital signal transmission device is generated on the data transmission line. A clock pulse generation circuit is provided, and the timing control means causes the clock pulse generation means to generate a clock pulse immediately before the data block, and prevents the clock pulse from being generated in the middle of the data block. The number of clock pulses included in one frame of serial data is reduced as compared with the conventional one in which one data pulse is generated between clock pulses. As a result, the length of one frame of serial data can be reduced, and the data transmission efficiency can be improved.

Further, the check pulse generation circuit includes:
The check pulse may be generated by inverting the data pulse (the invention of claim 4).

A digital signal transmission system according to a fifth aspect of the present invention includes two or more digital signal transmission devices commonly connected to a data transmission line, and controls the potential of the data transmission line. By switching, serial data is generated, input / output data groups of each digital signal transmission device are arranged for each frame which is a unit of the serial data, and multiplex communication is performed between digital signal transmission devices on the other side. In the digital signal transmission system, one digital signal transmission device includes: a data pulse generation circuit configured to divide an input / output data group into a data bit string having a predetermined number of bits and generate a data pulse string corresponding to the data bit string; Generates a check pulse train to check whether or not Timing for controlling the operation timing of the data pulse generation circuit and the check pulse generation circuit so that a check pulse generation circuit and a plurality of data blocks each having a data pulse train and a check pulse train corresponding to each other are provided in one frame. The digital signal transmission apparatus on the other end calculates exclusive OR of the receiving means for receiving the data pulse and the check pulse, and the data pulse train and the check pulse train received by the receiving means. It is characterized in that it is provided with an EXOR means for performing the operation and a data signal judging means for judging whether or not a data signal transmission error has occurred based on the operation result of the EXOR means.

According to this configuration, the timing control means provided in one digital signal transmission device controls the operation timing of both the data and check pulse generation circuits,
A plurality of data blocks are provided in one frame of the serial data, and a data pulse train and a check pulse train are arranged in each data block.

On the other hand, the digital signal transmission device of the other party
When the data pulse train and the check pulse train are received by the receiving means, the exclusive OR of the data pulse train and the check pulse train is calculated by the EXOR means.
Here, if the data is received correctly, since the data pulse train and the check pulse train are in an inverse relationship to each other, the exclusive OR of these pulse trains becomes “true”, but the data is not correctly received. Becomes "false". Then, based on the result of the calculation, the data signal determining means determines whether or not a data signal transmission error has occurred. As described above, according to the invention of claim 5, the receiving side receives the corresponding check pulse after a predetermined data pulse has been received, and after a half of the transmission time of the data block, receives the corresponding check pulse. Since it is detected whether or not transmission / reception has been performed, the responsiveness of data transmission is improved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIG. FIG. 1 shows a network for transmitting data online in a system in which a sensor S, an actuator R and the like are connected to one controller C for control. This network includes, for example, the master unit 11 arranged in the controller C.
And a plurality of terminal units 31 arranged for each terminal such as each sensor S, actuator R, and the like, in a bus system in which one data transmission line 10 is commonly connected.

FIG. 2 shows the configuration of the master unit 11. In FIG. 2, reference numeral 12 denotes a gate array as timing control means according to the present invention. Outputs a value signal.

Reference numeral 13 denotes a clock pulse receiving circuit, which is connected to the data transmission line 10 and has a value of "1" depending on whether the potential of the data transmission line 10 is above or below a threshold slightly smaller than 24 [V]. A binary signal of “0” is given to a data pulse output circuit 15 and a short circuit detection circuit 20 described later.

Reference numeral 14 denotes a data pulse receiving circuit,
It is connected in series between the data transmission line 10 and the input terminal of the gate array 12. Then, the data pulse receiving circuit 14 sets the potential of the data transmission line 10 to 0 [V].
The signal is turned on when the voltage falls below a slightly larger threshold, and turned off when the voltage exceeds the threshold, and a binary signal of “1” or “0” is given to the gate array 12.

Reference numeral 15 denotes a data pulse output circuit,
A switch element that is controlled to be turned on and off in response to a binary signal from the gate array 12, and that the data transmission line 10 is connected to the ground and the data transmission line 10 is separated from the ground by the on / off operation of the switch element And switch to

Reference numeral 16 denotes a 12 V constant current power supply, which is turned on and off in response to a binary signal from the gate array 12. When turned on, the data transmission line 10 is supplied to the data transmission line 10 while supplying a constant current of a predetermined value. A voltage of 12 [V] is applied.

Reference numeral 18 denotes a 24V constant-voltage power supply, which is turned on / off by receiving a binary signal from the gate array 12, and when turned on, applies a voltage of 24 [V] to the data transmission line 10. .

Reference numeral 19 denotes a drop-in circuit, for example, a Zener diode (not shown) and a switch element which are connected in series between the ground and the data transmission line 10 and are provided.
Upon receiving the binary signal from the gate array 12, the switch element is turned on, and the data transmission line 10
Drop from [V] to 12 [V].

Reference numeral 20 denotes a short-circuit detecting circuit which receives a binary signal from the gate array 12 to the pull-in circuit 19 and a binary signal from the clock pulse receiving circuit 13, and compares these binary signals. Detect short circuit.

Reference numeral 21 denotes a CPU provided in the controller C, which exchanges digital data with the gate array 12.

FIG. 3 shows the configuration of the terminal unit 31 connected to the actuator, and FIG. 4 shows the configuration of the terminal unit 31 connected to the sensor. 3 and 4, reference numeral 32 denotes a gate array, which is different from the gate array 12 of the master unit 11 in logic. Further, an address setting SW 36 is connected to the gate array 32. Further, the gate array 32 includes an EXOR circuit therein, and divides a sequentially captured 16-bit signal into a first half 8 bits and a second half 8 bits as described later.
The exclusive OR of each of these 8-bit data is sequentially obtained for each bit from the head side.

The clock pulse receiving circuit 33, the data pulse receiving circuit 34, and the data pulse output circuit 35 are provided with the circuits 13 to 15 of the master unit 11,
It has basically the same configuration. The gate array 32
Transmits / receives data to / from the sensor S or the actuator R via a photocoupler.

In the network protocol of this embodiment, frames of serial data to be transmitted and received are defined as follows, for example.

That is, in the frame F, as shown in FIG. 5A, a header H is formed by connecting two start pulses SP. These start pulses SP are obtained by inverting the data transmission line 10 between 12 [V] and 24 [V], and have a wider pulse width than a clock pulse CP described later.

After the header H, as shown in FIG. 5B, a plurality of data blocks B having the same length are connected, and one clock pulse for synchronization is provided immediately before each data block B. Have been. These clock pulses CP
Means that the data transmission line 10 is inverted between 12 [V] and 24 [V].
[V] corresponds to the OFF state of the clock pulse CP, and 24 [V] corresponds to the ON state of the clock pulse CP.

Each data block B is formed by inverting the data transmission line 10 between 0 [V] and 12 [V], as shown in detail in FIG.
It is composed of a 6-bit binary signal, the first 8 bits of which correspond to information exchanged between the units, and the latter 8 bits are obtained by inverting the former 8 bits. Further, when the data transmission line 10 becomes 0 [V], it corresponds to a state where the pulse in the data block corresponding to each bit is turned on, and the pulse corresponding to the first 8 bits of the data block according to the present invention. The pulse corresponding to the pulse P1 and corresponding to the latter 8 bits of 8 bits corresponds to the check pulse P2.

The data blocks B are classified according to their uses as follows. That is, in FIG. 5B, the control command block 40, the control data block 41, the output stop request block 42, the extension block 43, and a plurality of input / output Blocks 44, 44, 44,...

The input / output block 44 is provided for each unit 31.
This is a block for transmitting detection data of a sensor or the like connected to the above, an operation command to the actuator, and the like, and the number of blocks also changes according to the number of input / output points of the entire system.
More specifically, the first eight bits of each input / output block 44 correspond to the input / output data of the eight units 31, and each input / output block 44 is specified by an address ADD in the serial data. You.

The control command block 40 and the control data block 41 are used in combination. When the master unit 11 places a control command on the control command block 40, the predetermined terminal unit 31 specified by the control command is The response to the control command is
Put on the control data block.

The output stop request block 42 is for designating the address ADD of the input / output block 44 so that the unit 31 relating to the input / output block 44 does not output the data pulse DP. . Further, the extension block 43 is provided in preparation for extension of a future use.

Next, the operation of this embodiment having the above configuration will be described. First, the address setting circuit 36 provided in each terminal unit 31 causes each terminal unit 31
Set the address of As a result, the input / output signal of each unit 31 is changed to the data block B of which address ADD.
Is specified. Then, the controller C, the sensor S, and the actuator R
Is started, and the master unit 11 and each terminal unit 31 are started. Then, the master unit 11 controls the gate array 12 to turn on and off the constant voltage power supply 18 of 24 V and the pull-in circuit 19 to generate two start pulses SP and one clock pulse CP on the data transmission line 10. . Thereafter, at a predetermined period, one clock pulse CP is generated on the data transmission line 10 one by one, and each unit 1
1, 31 sets the data transmission line 10 to 12 [V] and 0
[V] to generate the pulses P1 and P2 related to the data block B.

Specifically, of the data block B, for example, the pulses P1 and P2 related to the control command block 40 are:
Generated by the master unit 11. That is, the gate array 12 of the master unit 11
A predetermined signal of bits is received, and based on the received signal, the data pulse output circuit 15 is turned on / off to generate a predetermined group of data pulses P1 on the data transmission line 10 and, following the data pulse P1 group, A group of check pulses P2, which is the inverse of the group of data pulses P1, is generated on the data transmission line 10.

Then, each terminal unit 31 takes in the data pulse P1 group and the check pulse P2 group of the control command block 40. And each unit 31
The EXOR circuit 31A (see FIG. 6) built in the gate array 32 of FIG.
The exclusive OR is sequentially calculated for each bit from the head of the two groups, and when the calculation result is “true” (“1”), it is determined that the data pulse P1 group has been correctly captured. Move to the next process. Also, the calculation result is “false”
When it becomes ("0"), it is determined that the data pulse P1 group has not been correctly captured, and the data is invalidated.

Here, the unit 31 on the receiving side receives a predetermined bit of the first half of each data block B, and then, after receiving a predetermined bit of the transmission time T1 of the block B, a time T4
After passing through (see FIG. 6), the data of the corresponding check bit is received, and it is checked whether or not the information has been correctly transferred. Therefore, the time required to detect whether or not the information has been correctly transmitted and received is determined by the transmission time of a plurality of data blocks included in one frame from the conventional transmission time of one frame (see time T3 in FIG. 7). The time is reduced to the time T1 or less.

Each unit 31 takes in the data of the control command block 40, and, for example, each of the eight units 31 specified by the control command generates a data pulse P1 on the data transmission line 10 in a predetermined order. Thus, a data pulse P1 group related to the first eight bits in the continuous control data block 41 following the control command block 40 is generated. At this time, each unit 31
Waits for a predetermined time from the clock pulse CP immediately before the block 41, so that data can be reflected in predetermined bits in the first half of the block 41. Next, the eight units 31 invert the data pulse P1 corresponding to the latter eight bits in the control data block 41 to generate a group of check pulses P2. Also at this time, each unit 31 waits for a predetermined time from the clock pulse CP immediately before the block 41, so that the check data can be reflected in a predetermined bit in the latter half of the block 41. The control data block 41 generated in this manner is stored in the master unit 11.
And the connection status of the eight units 31 is checked.

In the conventional digital signal transmission apparatus, only the connection state of each terminal unit can be checked with one frame F of serial data.
However, in the present embodiment, as described above, one frame F
, The connection status of every eight units 31 can be checked, so that the number of frames transmitted and received for checking the connection status is reduced by 1 /
8 can be reduced. However, the number of units whose connection status is checked is not limited to eight per frame, but may be set to a plurality other than eight.

The data blocks (42, 43, 44) other than the control command blocks 40, 41 are basically generated based on the same principle.

As described above, in the present embodiment, the time required to detect whether or not information has been correctly transmitted / received is determined from the conventional transmission time of one frame by the data block of a plurality of data blocks included in the one frame. The transmission time can be reduced to less than or equal to the transmission time, so that the responsiveness of data transmission can be improved. In this embodiment, 16-bit data and check pulses P1 and R2 can be output each time one clock pulse CP is output. Pulses are reduced, thereby improving data transmission efficiency.

<Other Embodiments> The present invention is not limited to the above embodiments. For example, the following embodiments are also included in the technical scope of the present invention.
In addition to the following, various changes can be made without departing from the scope of the invention. (1) In the above embodiment, the bus network
Although the example in which the data transmission device according to the present invention is connected has been described, the data transmission device according to the present invention may be connected to a star, tree, or loop network.

(2) Contrary to the above embodiment, the clock pulse is generated so as to be inverted between 0 [V] and 12 [V], while the data pulse is generated between 12 [V] and 24 [V].
It may be generated to be inverted between [V].

(3) The present invention is not limited to transmitting serial data using ternary signals of 0 [V], 12 [V], and 24 [V] as in the above-described embodiment. The present invention may be applied to a device that transmits serial data using a signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a network according to an embodiment of the present invention.

FIG. 2 is a block diagram of a master unit.

FIG. 3 is a block diagram of a terminal unit.

FIG. 4 is a block diagram of a terminal unit.

FIG. 5 is a conceptual diagram showing a frame configuration.

FIG. 6 is a time chart showing one of data blocks.

FIG. 7 is a conceptual diagram showing a conventional frame configuration.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Data transmission line 11 ... Master unit (digital signal transmission device) 12, 32 ... Gate array (EXOR means, timing control means) 15 ... Data pulse output circuit (reception means) 16 ... Constant current power supply (data and check pulse) Generating circuit, clock pulse generating circuit 18 constant voltage power supply (clock pulse generating circuit) 19 pull-in circuit (clock pulse generating circuit) 31 terminal unit (digital signal transmission device) 35 data pulse output circuit (data and check) Pulse generation circuit) 40: control command block (data block) 41: control data block (data block) 42: output stop request block (data block) 43: expansion block (data block) 44: input / output block (data block) ) B: Data Lock CP ... clock pulse P1 ... data pulse P2 ... check pulse

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K014 AA01 DA04 DA05 EA01 HA01 5K028 AA11 KK01 MM09 NN23 NN31 RR04 5K033 AA02 CA11 CB03 CB15 DA13 DA14 DA15 DB11 5K047 AA02 CC02 GG02 GG09 LL15 MM53

Claims (5)

[Claims] 1. A digital signal transmission in which a plurality of input / output data groups of a plurality of bits corresponding to a plurality of transmission devices are arranged for each frame which is a unit of serial data for performing multiplex communication between the plurality of transmission devices. In the method, the input / output data group is divided into a data bit string having a predetermined number of bits, and a check bit string for checking whether or not each of the data bit strings is correctly transmitted is connected to each data bit string. A digital signal transmission system, wherein a plurality of data blocks each including a data bit string and the check bit are provided in the one frame. 2. A digital signal transmission device which is commonly connected to a plurality of data transmission lines, wherein serial data is generated by switching a potential of the data transmission line, and one frame is a unit of the serial data. In each digital signal transmission device performing multiplex communication by placing the input / output data group of each digital signal transmission device, the input / output data group is divided into a data bit sequence of a predetermined number of bits and corresponds to the data bit sequence. A data pulse generation circuit that generates a data pulse train, a check pulse generation circuit that generates a check pulse train for checking whether the data pulse train has been transmitted correctly, and a data pulse train and the check pulse train that correspond to each other. So that a plurality of data blocks consisting of And a timing control means for controlling the operation timing of the data pulse generation circuit and the check pulse generation circuit. 3. A clock pulse generator for controlling a timing of an operation by said timing control means to generate a clock pulse for synchronizing with each of said digital signal transmission devices on said data transmission line. A circuit, wherein the timing control means causes the clock pulse generation means to generate the clock pulse immediately before the data block, and prevents the clock pulse from being generated in the middle of the data block. The digital signal transmission device according to claim 2, wherein: 4. The digital signal transmission device according to claim 2, wherein the check pulse generation circuit generates the check pulse by inverting the data pulse. 5. It is provided with two or more digital signal transmission devices commonly connected to a data transmission line, and generates serial data by switching the potential of the data transmission line, and is a constituent unit of the serial data. In a digital signal transmission system in which input / output data groups of each digital signal transmission device are arranged for each frame and multiplex communication is performed between digital signal transmission devices on the other side, one digital signal transmission device includes: A data group is divided into a data bit string having a predetermined number of bits, and a data pulse generation circuit that generates a data pulse string corresponding to the data bit string, and a check pulse string for checking whether the data pulse string has been transmitted correctly. A check pulse generating circuit that inverts and generates the data pulse; And a timing control means for controlling the operation timing of the data pulse generation circuit and the check pulse generation circuit so that a plurality of data blocks each comprising a data pulse train and the check pulse train are provided in one frame. A receiving means for receiving the data pulse and the check pulse; and an EXOR for calculating an exclusive OR of the data pulse train and the check pulse train received by the receiving means.
And a data signal judging means for judging whether or not a transmission error of the data signal has occurred, based on an operation result of the EXOR means.