JP2001285110A - Broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of not capable of suppressing the offset quantity of an intermediate frequency signal unless an expensive oscillator is used. SOLUTION: The receiver is provided with a first frequency divider 42 which frequency-divides a reference signal, a local oscillator 44 generating an oscillation signal in accordance with a control voltage, a second frequency divider 45 which frequency-divides the oscillation signal based on a setting frequency dividing ratio, a phase comparator 46 comparing the phases of the output signals of the first frequency divider and the second frequency divider and outputting a phase difference signal, an LPF 47 generating the control voltage based on the phase difference signal, a first mixer 13 generating the intermediate frequency signal by mixing the oscillation signal and a DAB broadcast signal, an offset quantity detection circuit 31 detecting the offset quantity of the intermediate frequency signal and a control circuit 33 which variably sets the setting frequency dividing ratio of the second frequency divider 45 until offset quantity falls within a permission range and stores the setting frequency dividing ratio after variable setting into a memory 35 when the offset quantity of the intermediate frequency signal is judged to be not within the permission range by an offset judgment circuit 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a broadcast receiving apparatus such as a DAB receiver having a function of suppressing an offset amount of an intermediate frequency signal by adjusting a set frequency division ratio of a PLL circuit.

[0002]

2. Description of the Related Art Conventionally, as such a broadcast receiving apparatus,
One example is a DAB receiver as shown in FIG. FIG. 3 is a block diagram showing a schematic configuration inside a conventional DAB receiver.

[0003] A DAB receiver 50 shown in FIG. 3 includes a receiving antenna 51 for receiving an incoming DAB broadcast signal, a first amplifier 52 for amplifying the DAB broadcast signal received by the receiving antenna 51, and a DAB broadcast signal. Mixer 53 for frequency-converting the first intermediate frequency signal into a first intermediate frequency signal, and converting the first intermediate frequency signal frequency-converted by the first mixer 53 to D
A SAW filter 54 for limiting to the AB bandwidth,
A second amplifier 55 that amplifies the first intermediate frequency signal band-limited by the W filter 54; and a second amplifier 55 that frequency-converts the first intermediate frequency signal amplified by the second amplifier 55 into a second intermediate frequency signal. The mixer 56 and the second mixer 56
A filter 57 for cutting a noise component of the second intermediate frequency signal frequency-converted by the filter 57, and a third amplifier 5 for amplifying the second intermediate frequency signal cut by the filter 57
An A / D converter 59 for digitally converting the second intermediate frequency signal amplified by the third amplifier 58;
From the digitally converted second intermediate frequency signal, DA
A DAB decoder 60 for decoding B data;
An MPEG audio decoder 61 for decoding audio data from DAB data by a decoder 60, a D / A converter 62 for converting the audio data into an analog signal and outputting it as an audio signal, and a microcomputer 63 for controlling the entire DAB receiver 50 are provided. are doing.

[0004] The first mixer 53 converts the DAB broadcast signal into a PL signal.
By mixing the oscillation signals from the L circuit 70, the DAB broadcast signal is frequency-converted into a first intermediate frequency signal.

The PLL circuit 70 includes a crystal oscillator 71
And a fixed frequency dividing ratio n
, A local oscillator 74 that generates an oscillation signal having a local oscillation frequency in accordance with a control voltage, and divides the oscillation signal based on a set division ratio N. The second frequency divider 75 compares a phase of an output signal of the first frequency divider 73 with a phase of an output signal of the second frequency divider 75, and outputs a phase difference signal of these output signals. An LPF 77 that generates a control voltage based on the phase difference signal, and a multiplier 78 that multiplies the reference signal to generate an oscillation signal for generating a second intermediate frequency signal.

In order for the first mixer 53 to obtain a desired first intermediate frequency signal, the microcomputer 63 appropriately changes the set frequency division ratio N of the second frequency divider 75 in accordance with the frequency. .

The DAB decoder 60 decodes DAB data from the second intermediate frequency signal. The DAB decoder 60 can decode the DAB data from the second intermediate frequency signal. An allowable range of the frequency shift (offset amount) of the signal is defined.

Therefore, in the DAB receiver 50, if the offset amount of the second intermediate frequency signal exceeds the allowable range in the DAB decoder 60, DAB data cannot be decoded from the second intermediate frequency signal.
In order to suppress the offset amount of the second intermediate frequency signal, it is necessary to suppress the offset amount of the first intermediate frequency signal.

Therefore, the conventional DAB receiver 5 shown in FIG.
According to 0, by using a crystal oscillator 71 with high frequency accuracy or a temperature-compensated oscillator as the reference oscillator 72 of the PLL circuit 70, the set frequency dividing ratio N of the second frequency divider 75 is appropriately changed to obtain the first frequency. The offset amount of the intermediate frequency signal can be reduced, and as a result, the offset amount of the second intermediate frequency signal can be within an allowable range.

[0010] There is also the following conventional DAB receiver. FIG. 4 is a block diagram showing a schematic configuration inside a conventional DAB receiver. The conventional DAB receiver 5 shown in FIG.
The same reference numerals are given to components overlapping with the configuration of 0, and the description of the configuration and operation is omitted.

A difference between the conventional DAB receiver 80 shown in FIG. 4 and the DAB receiver 50 shown in FIG. 3 is that a voltage control for controlling a reference oscillator 72 instead of a crystal oscillator 71 for generating a reference signal is performed. Crystal oscillator (VCXO) 8
1 is provided.

The voltage controlled crystal oscillator 81 controls the reference oscillator 72 based on the offset detection signal relating to the second intermediate frequency signal from the DAB decoder 60, thereby adjusting the reference signal from the reference oscillator 72. it can.

According to the DAB receiver 80, the voltage control crystal oscillator 81 that controls the reference oscillator 72 based on the offset detection signal relating to the second intermediate frequency signal from the DAB decoder 60 uses the first intermediate frequency signal. Is reduced, and as a result, the offset amount of the second intermediate frequency signal can be set within an allowable range.

[0014]

However, according to the conventional DAB receiver 50 shown in FIG. 3, there is almost no frequency error even in an external environment such as a low temperature, and the crystal oscillator 71 or the temperature compensator having a high frequency accuracy. Although the offset amount of the first intermediate frequency signal is suppressed by using a type oscillator, such a crystal oscillator 71 or a temperature compensated oscillator is expensive, and as a result, the cost of the entire DAB receiver 50 is reduced. There was a problem that it became expensive.

A conventional DAB receiver 80 shown in FIG.
According to the first embodiment, the voltage controlled crystal oscillator 81 that adjusts the reference oscillator 72 based on the offset detection signal from the DAB decoder 60 so that the offset amount of the second intermediate frequency signal is within a permissible decoding range is used. (1) The offset amount of the intermediate frequency signal is suppressed, but such a voltage controlled crystal oscillator is expensive, and as a result,
Since the cost of the entire DAB receiver 80 is increased, and the adjustment operation of the reference oscillator 72 is performed every time the power is turned on, the adjustment operation increases the time required from the power on to the audio output. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a broadcast capable of quickly suppressing an offset amount of an intermediate frequency signal without using an expensive oscillator. A receiving device is provided.

[0017]

In order to achieve the above object, a broadcast receiving apparatus according to the present invention comprises: a PLL circuit for changing a frequency of an output signal by controlling a frequency division ratio of a frequency divider; A mixing circuit that generates an intermediate frequency signal by mixing an output signal from the broadcast signal and a broadcast signal, an offset amount detection circuit that detects an offset amount of the intermediate frequency signal, and an offset detected by the offset amount detection circuit. And a memory for storing information relating to the frequency division ratio when the amount is within the allowable range.

Therefore, according to the broadcast receiving apparatus of the present invention,
Since information related to the frequency division ratio of the frequency divider when the offset amount of the intermediate frequency signal is within the allowable range is stored in the memory, even if an inexpensive crystal is used as the reference oscillator inside the PLL circuit, The offset amount of the intermediate frequency signal can be suppressed based on the information stored in the memory.

Further, according to the broadcast receiving apparatus of the present invention,
Since the information related to the frequency division ratio of the frequency divider when the offset amount of the intermediate frequency signal is within the allowable range is stored in the memory, even if the power is turned on again after the storage in the memory, the information is stored in the memory. By setting the frequency division ratio of the frequency divider based on the information stored in the memory, the time required for the operation from power-on to audio output in a state where the offset amount of the intermediate frequency signal is suppressed is reduced. Can be.

The broadcast receiving apparatus according to the present invention has a control means for controlling a frequency division ratio of the frequency divider based on information stored in the memory.

Therefore, according to the broadcast receiving apparatus of the present invention,
Since the frequency division ratio of the frequency divider is controlled based on the information stored in the memory, even if an inexpensive crystal is used for the reference oscillator in the PLL circuit, the offset amount of the intermediate frequency signal is suppressed. be able to.

A broadcast receiving apparatus according to the present invention includes a reference oscillator for generating a reference signal, a first frequency divider for dividing the reference signal based on a fixed frequency division ratio, and a local oscillation frequency according to a control voltage. A local oscillator circuit that generates an oscillation signal of the following, a second frequency divider that divides the oscillation signal based on a set frequency division ratio,
A phase comparator that compares the phases of the output signal of the first frequency divider and the output signal of the second frequency divider, and outputs a phase difference signal between the output signals; and the control voltage based on the phase difference signal. A broadcast receiving apparatus comprising: a control voltage generating circuit that generates the intermediate frequency signal; and a mixing circuit that generates the intermediate frequency signal by mixing the oscillation signal and the broadcast signal of the local oscillation circuit. An offset amount detection circuit for detecting an offset amount; an offset determination circuit for determining whether or not the offset amount detected by the offset amount detection circuit is within an allowable range; If it is determined that the offset amount is not within the allowable range, the second frequency division is performed until the offset determination circuit determines that the offset amount of the intermediate frequency signal is within the allowable range. When the offset determination circuit determines that the offset amount of the intermediate frequency signal is within an allowable range, the set frequency division ratio after the variable setting is stored in a memory. Circuit.

Therefore, according to the broadcast receiving apparatus of the present invention,
When it is determined that the offset amount of the intermediate frequency signal is not within the allowable range, the frequency division set by the second frequency divider is performed until the offset determination circuit determines that the offset amount of the intermediate frequency signal is within the allowable range. When the ratio is variably set and the offset amount of the intermediate frequency signal is determined to be within the allowable range, the set dividing ratio after the variable setting is stored in the memory, so that an inexpensive crystal can be used as the reference oscillator. Even if used, the offset amount of the intermediate frequency signal can be suppressed.

According to the broadcast receiving apparatus of the present invention, the set frequency division ratio after variable setting is stored in the memory. Therefore, even if the power is turned on again after storing in the memory.
By directly setting the set frequency division ratio stored in the memory as the set frequency division ratio of the second frequency divider, the operation from power-on to audio output is required in a state where the offset amount of the intermediate frequency signal is suppressed. The required time can be shortened.

In the broadcast receiving apparatus according to the present invention, the control circuit stores an initial value of a division ratio set by the second frequency divider in a memory, and the offset determination circuit determines an offset amount of the intermediate frequency signal. Is determined to be not within the allowable range,
The set dividing ratio of the second frequency divider is variably set by sequentially adding a change amount to the initial value until the offset judging circuit judges that the offset amount of the intermediate frequency signal is within the allowable range. When the offset determination circuit determines that the offset amount of the intermediate frequency is within the allowable range, the change amount sequentially added to the initial value of the set division ratio after the variable setting is changed. As a memory.

Therefore, according to the broadcast receiving apparatus of the present invention,
In addition to the initial value, the change in the set dividing ratio after the variable setting is stored in the memory, so after storing in the memory,
Even if the power is turned on again, the change amount and the initial value stored in the memory are directly set as the set division ratio of the second frequency divider, so that the offset amount of the intermediate frequency signal is suppressed. The time required for the operation from power-on to audio output can be reduced.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a DAB receiver showing an embodiment in a broadcast receiving apparatus of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration inside the DAB receiver shown in the present embodiment.

The DAB receiver 1 shown in FIG.
A receiving antenna 11 for receiving an AB broadcast signal, a first amplifier 12 for amplifying a DAB broadcast signal received by the receive antenna 11, and a first mixer 13 for frequency-converting the DAB broadcast signal to a first intermediate frequency signal; The first intermediate frequency signal frequency-converted by the first mixer 13 is
A SAW filter 14 for limiting to B bandwidth,
A second amplifier for amplifying the first intermediate frequency signal band-limited by the filter, and a second mixer for frequency-converting the first intermediate frequency signal amplified by the second amplifier to a second intermediate frequency signal 16, a filter 17 for cutting a noise component of the second intermediate frequency signal frequency-converted by the second mixer 16, and a third amplifier 18 for amplifying the second intermediate frequency signal cut by the filter 17
An A / D converter 19 for digitally converting the second intermediate frequency signal amplified by the third amplifier 18, and a DAB from the digitally converted second intermediate frequency signal.
A DAB decoder 20 for decoding data, an MPEG audio decoder 21 for decoding audio data from DAB data by the DAB decoder 20, a D / A converter 22 for converting the audio data into an analog signal and outputting it as an audio signal, and a DAB receiver 1
And a microcomputer 30 for controlling the whole.

The first mixer 13 converts the DAB broadcast signal into a PL
By mixing the oscillation signals from the L circuit 40, the DAB broadcast signal is frequency-converted into the first intermediate frequency signal.

The PLL circuit 40 includes an inexpensive crystal 41.
And a first frequency divider 43 for dividing the reference signal based on a fixed frequency division ratio, and a local oscillator 44 for generating an oscillation signal having a local oscillation frequency according to the control voltage. A second frequency divider 45 for dividing the oscillation signal based on the set frequency division ratio, an output signal of the first frequency divider 43, and a second
A phase comparator 46 that compares the phases of the output signals of the frequency divider 45 and outputs a phase difference signal of these output signals, an LPF 47 that generates a control voltage based on the phase difference signal, and a reference signal from the reference oscillator 42 And a multiplier 48 for generating an oscillation signal for generating a second intermediate frequency signal by multiplying the frequency.

The microcomputer 30 appropriately changes the set frequency division ratio N of the second frequency divider 45 in accordance with the frequency so that the first mixer 13 obtains a desired first intermediate frequency signal. The initial value of the set frequency division ratio N of the second frequency divider 45 is stored in the memory 35.

The DAB decoder 20 decodes DAB data from the second intermediate frequency signal. The DAB decoder 20 can decode the DAB data from the second intermediate frequency signal. The allowable range of the signal offset amount is determined.

The microcomputer 30 detects an offset amount of the second intermediate frequency signal of the DAB decoder 20 by an offset amount detection circuit 31 and determines whether or not the offset amount detected by the offset amount detection circuit 31 is within an allowable range. When the offset determination circuit 32 determines whether the offset amount of the second intermediate frequency signal is not within the allowable range, the offset determination circuit 32 determines whether the offset amount of the second intermediate frequency signal is not within the allowable range. The set division ratio N of the second frequency divider 45 is variably set by sequentially adding the change amount ΔN to the initial value until it is determined that the second intermediate frequency is within the allowable range. If it is determined that the offset amount of the signal is within the allowable range, the change amount sequentially added to the initial value among the set division ratios N after the variable setting is regarded as the change amount. And a control circuit 30 to be stored in the memory 35.

It is assumed that the DAB receiver 1 sets the dividing ratio N of the second divider 45 as an initial value at the time of shipment, and stores the initial value in the memory 35.

The DAB receiver 1 shown in this embodiment
However, the configuration differs from the DAB receiver of the prior art in that an inexpensive crystal 41 is used, and further, a function for controlling a reference oscillator 42 is not used.

Next, the operation of the DAB receiver 1 according to the present embodiment will be described. FIG.
5 is a flowchart illustrating a processing operation of an offset amount control process in a microcomputer 35 inside the B receiver 1.

The offset amount control processing shown in FIG.
This is a process of suppressing the offset amount of the first intermediate frequency signal within a predetermined allowable range so as to suppress the offset amount of the second intermediate frequency signal to the AB decoder 20 within an allowable range.
Here, the case where the DAB receiver 1 is turned on for the first time after shipment will be described as an example.

The microcomputer 30 shown in FIG.
The initial value stored in the memory 35 is read (step S1).
1) The initial value is set as the set frequency division ratio N of the second frequency divider 45 (step S12), and the oscillation signal from the PLL circuit 40 is locked (step S13).

By locking the oscillating signal from the PLL circuit 40, the first mixer 13 converts the frequency into a first intermediate frequency signal based on the oscillating signal from the PLL circuit 40. The intermediate frequency signal is frequency-converted by the second mixer 16 into a second intermediate frequency signal,
This second intermediate frequency signal is input to the DAB decoder 20.

The offset detecting circuit 31 detects the offset of the second intermediate frequency signal (step S1).
4), the offset determination circuit 32 outputs the detected second
It is determined whether or not the offset amount of the intermediate frequency signal is within an allowable range (Step S15).

If it is determined that the offset amount of the second intermediate frequency signal is not within the allowable range, the predetermined change amount ΔN is read out (step S16), and the predetermined change amount ΔN is added to the initial value (step S17). The process proceeds to step S12 in order to set the value as the set dividing ratio N of the second divider 45. In other words, until the offset amount of the second intermediate frequency signal falls within the allowable range in step S15, step S16 is performed.
, The predetermined change amount ΔN is sequentially added to the initial value.

If it is determined in step S15 that the offset amount of the second intermediate frequency signal is within the allowable range, the current set dividing ratio N is obtained by adding the change ΔN * α to the initial value. It is determined whether or not it is (step S18).

The current set dividing ratio N is changed to the initial value by an amount ΔN
If * α has been added, the change ΔN * α is stored in the memory 35 (step S19), and the processing operation ends to start the normal reception operation. Note that the coefficient α of the change ΔN * α is equivalent to the number of times the process proceeds to step S16, that is, the number of times the change amount ΔN is added to the initial value.

In step S17, unless the current set dividing ratio N is obtained by adding the change ΔN * α to the initial value, the set dividing ratio N of the second frequency divider 45 remains at the initial value. Is determined, and the processing operation ends to start the normal reception operation.

In step S18, the change amount is changed by ΔN *
When the power is turned on next time, the change ΔN * stored in the memory 35 is stored as α in the memory 35.
A value obtained by adding α and the initial value can be set as the set frequency division ratio N.

According to the present embodiment, the second frequency divider 4 operates until the offset amount of the second intermediate frequency signal falls within the allowable range.
Since the set dividing ratio N of 5 is variably set, even if an inexpensive crystal 41 is used without providing a voltage controlled crystal oscillator for controlling the reference oscillator 42,
The offset amount of the intermediate frequency signal can be suppressed within an allowable range.

Further, according to the present embodiment, in addition to the initial value, the change in the set dividing ratio N after the variable setting is stored in the memory 35.
Even if the power is turned on again, the change ΔN * α and the initial value stored in the memory 35 are directly set as the set frequency division ratio N of the second frequency divider 45, so that the second intermediate frequency signal In a state where the offset amount is suppressed, the time required for the operation from power-on to audio output can be reduced.

[0048]

According to the broadcast receiving apparatus of the present invention configured as described above, information relating to the frequency division ratio of the frequency divider when the offset amount of the intermediate frequency signal is within the allowable range is stored in the memory. Therefore, even if an inexpensive crystal is used as the reference oscillator in the PLL circuit, the offset amount of the intermediate frequency signal can be suppressed based on the information stored in the memory.

Further, according to the broadcast receiving apparatus of the present invention,
Since the information related to the frequency division ratio of the frequency divider when the offset amount of the intermediate frequency signal is within the allowable range is stored in the memory, even if the power is turned on again after the storage in the memory, the information is stored in the memory. By setting the frequency division ratio of the frequency divider based on the information stored in the memory, the time required for the operation from power-on to audio output in a state where the offset amount of the intermediate frequency signal is suppressed is reduced. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration inside a DAB receiver showing an embodiment in a broadcast receiving apparatus of the present invention.

FIG. 2 is a flowchart showing a processing operation related to an offset amount control process in a microcomputer inside the DAB receiver shown in the present embodiment.

FIG. 3 is a block diagram showing a schematic configuration inside a conventional DAB receiver.

FIG. 4 is a block diagram showing a schematic configuration inside a conventional DAB receiver.

[Explanation of symbols]

 Reference Signs List 1 DAB receiver (broadcast receiving device) 13 First mixer (mixing circuit) 40 PLL circuit 42 Reference oscillator 43 First frequency divider 44 Local oscillator 45 Second frequency divider 46 Phase comparator 47 Low-pass filter (Control voltage generation circuit) ) 30 microcomputer 31 offset detection circuit 32 offset determination circuit 33 control circuit 35 memory

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 PP03 QQ09 RR18 5K020 AA08 BB04 DD11 DD22 DD26 EE01 EE04 EE05 GG09 GG10 GG11 GG12 GG25 LL09

Claims (4)

[Claims] 1. A PLL circuit for changing a frequency of an output signal by controlling a frequency division ratio of a frequency divider, and an intermediate frequency signal is generated by mixing an output signal from the PLL circuit and a broadcast signal. A mixing circuit; an offset amount detection circuit for detecting an offset amount of the intermediate frequency signal; and a memory for storing information relating to a frequency division ratio when the offset amount detected by the offset amount detection circuit is within an allowable range. A broadcast receiving device comprising: 2. The broadcast receiving apparatus according to claim 1, further comprising control means for controlling a frequency division ratio of said frequency divider based on information stored in said memory. 3. A reference oscillator for generating a reference signal, a first frequency divider for dividing the reference signal based on a fixed frequency division ratio, and an oscillation signal having a local oscillation frequency according to a control voltage. The local oscillator circuit compares a phase of an output signal of the first frequency divider with a phase of an output signal of the second frequency divider based on a set frequency division ratio. A phase comparator for outputting a phase difference signal of these output signals, a control voltage generation circuit for generating the control voltage based on the phase difference signal, and mixing an oscillation signal and a broadcast signal of the local oscillation circuit. A broadcast receiving apparatus comprising: a mixing circuit that generates the intermediate frequency signal; an offset amount detection circuit that detects an offset amount of the intermediate frequency signal; and an offset amount detected by the offset amount detection circuit. Is within acceptable range An offset determination circuit for determining whether or not the offset amount of the intermediate frequency signal is not within the allowable range when the offset determination circuit determines that the offset amount of the intermediate frequency signal is not within the allowable range. Until it is determined, the set frequency division ratio of the second frequency divider is variably set. If the offset determination circuit determines that the offset amount of the intermediate frequency signal is within an allowable range, the variable setting is performed. And a control circuit for storing a later set division ratio in a memory. 4. The control circuit stores an initial value of a division ratio set by the second frequency divider in a memory, and determines that an offset amount of an intermediate frequency signal is not within an allowable range in the offset determination circuit. If determined, the offset determination circuit sequentially adds a change amount to the initial value until it is determined that the offset amount of the intermediate frequency signal is within the allowable range, thereby setting the second frequency divider. The frequency division ratio is variably set, and when the offset determination circuit determines that the offset amount of the intermediate frequency is within the allowable range, the frequency division ratio is sequentially added to the initial value in the set frequency division ratio after the variable setting. 4. The broadcast receiving apparatus according to claim 3, wherein the change amount is stored in a memory as a change amount.