JPH09186947A - Automatic frequency control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a center frequency of automatic frequency control due to mis-count of a frequency of a 2nd intermediate frequency signal at a weak electric field strength. SOLUTION: A video processing circuit 13 detects a C/N of a satellite broadcast signal from an error rate of a PCM audio digital signal c1 and generates a C/N voltage e1 at a weak electric field strength based on the C/N and gives the voltage to a DC correction circuit 15. A channel selection PLL circuit 16 shifts a frequency of a reference oscillation in circuit having a frequency shift indicated by a control data signal i1 from a microcomputer 14 and corrects a frequency of the reference oscillation circuit based on a C/N voltage h1 from the DC correction circuit 15 and generates a control voltage k1 so that a frequency obtained by frequency-dividing the frequency of the oscillation signal j1 from a local oscillation circuit 17 and a frequency of the reference oscillation circuit are coincident with each other and provides the control voltage to the local oscillation circuit 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite broadcasting receiver 2
The present invention relates to an automatic frequency control circuit used in an nd converter, and particularly to an automatic frequency control circuit capable of preventing truncation noise from being generated in a weak electric field.

[0002]

2. Description of the Related Art Conventionally, as a frequency modulation demodulation (hereinafter referred to as FM demodulation) of a 2nd converter of a satellite broadcast receiver, a phase locked loop demodulation system (hereinafter referred to as PLL demodulation) system is generally used. Automatic frequency control system (hereinafter referred to as A
In many cases, it is configured as an FC system). This method has an advantage that the circuit configuration can be simplified. However, because the demodulation output is used, the stability against temperature change is determined by the temperature drift of the voltage controlled oscillator (hereinafter referred to as VCO). The stability of the tank circuit becomes important. Further, since the offset voltage of the AFC output due to the variation of the integrated circuit (hereinafter referred to as IC) is absorbed, there is a drawback that adjustment is required. Therefore, a so-called digital AFC of a method of directly reading the frequency of a second intermediate frequency signal (hereinafter, referred to as a second IF signal) input to the IC instead of using the demodulation output
The system has begun to be adopted in recent years. Since this method uses the oscillation signal of the crystal oscillation circuit for the reference frequency of the counter circuit, it is possible to construct an AFC system with a very high accuracy in a normal electric field.

However, in the case of a weak electric field, the counter circuit miscounts the frequency of the second IF signal due to the influence of noise,
As a result, although the frequency of the second IF signal is not actually deviated, it is determined that it is deviated, and the center frequency of the AFC is deviated. As a result, the second IF frequency input to the PLL-FM demodulation circuit shifts, truncation noise (tailing noise) due to the lock release of the PLL-FM demodulation circuit easily occurs, and when a weak electric field is generated, normal operation (IF frequency (If there is no deviation), the lock range width is narrowed and the input level of the satellite broadcast signal that causes truncation noise increases.

[0004]

In the above-mentioned conventional digital automatic frequency control system for directly reading the second intermediate frequency signal, a miscount operation occurs due to the influence of noise when the electric field is weak, and the center frequency of the automatic frequency control shifts. As a result, the input level of the satellite broadcast signal in which truncation noise occurs due to the shift of the second intermediate frequency signal increases.

The present invention eliminates the above problems and provides an automatic frequency control circuit capable of preventing the center frequency of automatic frequency control from shifting by miscounting the frequency of the second intermediate frequency signal in a weak electric field. For the purpose of provision.

[0006]

According to the structure of claim 1, the frequency of the oscillation signal from the local oscillation circuit becomes the center frequency of the automatic frequency control, and the video processing circuit causes the phase lock loop-frequency modulation demodulation circuit. A weak electric field is detected by the demodulation signal from the device, and the detection voltage of this detection result is output. While shifting the frequency of the reference oscillation circuit that has, while correcting the frequency of the reference oscillation circuit based on the detection voltage from the video processing circuit, the divided output of the frequency of the oscillation signal from the local oscillation circuit is divided. Since the local oscillation circuit is controlled so that the frequency matches the frequency of the reference oscillation circuit, the frequency of the second intermediate frequency signal is miscounted when the electric field is weak. That the center frequency of the automatic frequency control is shifted can be prevented Ri.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an invention of an automatic frequency control circuit according to the present invention.

In FIG. 1, reference numeral 11 denotes a second intermediate frequency signal (hereinafter referred to as a second IF signal) a1 output from the second intermediate frequency conversion section of the 2nd converter of the satellite broadcast receiver.
The second IF signal a1 led to the input terminal 11 is supplied to a phase lock loop-frequency modulation demodulation circuit (hereinafter referred to as PLL-FM demodulation circuit) 12. The PLL-FM demodulation circuit 12 demodulates the supplied second IF signal a1 and extracts the baseband video signal b1 and the PCM digital audio signal c1 which are demodulated signals and supplies them to the video processing circuit 13 and at the same time the second I signal.
The F signal a1 is read by a built-in counter, an automatic frequency control voltage (hereinafter referred to as AFC voltage) d1 is generated and supplied to the microcomputer 14.

The video processing circuit 13 separates the supplied baseband video signal b1 and the PCM digital audio signal c1 from the error rate of the PCM audio digital signal c1 and determines the ratio between the received signal power and the noise power of the satellite broadcast signal. (C / N
Ratio) is detected, based on this C / N ratio, a weak electric field is detected, and a C / N voltage e1 is created as this detection voltage and supplied to the DC correction circuit 15. Also, the video processing circuit 13
The noise of the video signal b1 is removed and the video signal f1 is guided to the video signal output terminal 21, and the PCM audio digital signal c1 is digitally decoded and digital-analog converted to create an analog audio signal g1 and the analog signal is guided to the output terminal 22. .

The DC correction circuit 15 is a video processing circuit 13.
The C / N voltage e1 from is corrected and supplied as the C / N voltage h1 to the tuning PLL circuit 16.

The microcomputer 14 is a PLL-F
When the AFC voltage d1 from the M demodulation circuit 12 indicates an AFC error, a control data signal i1 that shifts the frequency so as to correct this error is created to select the tuning PLL circuit 16
To supply.

The tuning PLL circuit 16 shifts the frequency of the internal reference oscillation circuit by the shift value of the frequency indicated by the control data signal i1 from the microcomputer 14, and the C / N from the DC correction circuit 15 Voltage h1
The control voltage k1 is generated so that the frequency of the reference oscillation circuit is corrected based on the above, and the frequency of the divided output obtained by dividing the frequency of the oscillation signal j1 from the local oscillation circuit 17 matches the frequency of the reference oscillation circuit. Then, the local oscillation circuit 17 is supplied. The local oscillation circuit 17 oscillates the center frequency of the AFC, the oscillation frequency is controlled by the control voltage k1, and supplies the oscillation signal j1 to the channel selection mixer of the second intermediate frequency conversion unit. The channel selection mixer of the second intermediate frequency conversion unit extracts a beat component of the BS-IF signal from the satellite broadcast converter (BS converter) and the oscillation signal j1 to perform channel selection and creates a second IF signal a1. .

The operation of the embodiment of the invention will be described below.

In the digital AFC operation by the PLL-FM demodulation circuit 12, when a weak electric field is generated, a miscount occurs and A
The center frequency of FC shifts. Therefore, the PLL-F
Even when the second IF signal a1 which is not actually deviated is supplied, the M demodulation circuit 12 outputs AF as the AFC voltage d1.
The C error voltage is supplied to the microcomputer 14 via the AFC voltage line, and the microcomputer 14 supplies the frequency shift data as the control data signal i1 to the tuning PLL circuit 16. As a result, the PLL
-Only the digital AFC operation by the FM demodulation circuit 12 stabilizes when the IF frequency is shifted. In order to correct this, the frequency of the reference oscillation circuit of the tuning PLL circuit 16 is corrected based on the C / N voltage h1 supplied from the video processing circuit 13 via the DC correction circuit 15, and the center frequency deviation of AFC is corrected. The influence of is not shown in the local oscillation frequency of the local oscillation circuit 17. For example, the center frequency of AFC is I
When F is shifted to the lower side, the control data i1 from the microcomputer 14 becomes the data for lowering the local oscillation frequency. That is, the frequency division output of the internal programmable counter of the PLL circuit 16 for tuning becomes higher than the reference frequency. If the C / N voltage h1 is not supplied here, the PLL circuit 16 for tuning operates so as to correct the error as it is, so that the local oscillation frequency is lowered. At this time, if the reference frequency of the reference oscillation circuit is increased by an error based on the C / N voltage h1 as in the embodiment of the invention shown in FIG.
The error correction operation of the tuning PLL circuit 16 is not performed, and the AF
The local oscillation frequency, which is the center frequency of C, can maintain a normal oscillation frequency.

As described above, according to the embodiment of the present invention, it is possible to prevent the center frequency of the AFC from shifting by miscounting the frequency of the second intermediate frequency signal in the weak electric field. The input level of the satellite broadcast signal in which truncation noise occurs can be lowered, and the user can be given a high impression.

FIG. 2 shows the DC correction circuit 15 and the tuning P of FIG.
6 is a circuit diagram showing a circuit system of a LL circuit 16 and a reference oscillator. FIG.

In FIG. 2, the DC correction circuit 15 is a buffer and is composed of a comparator 31 and a resistor R1. The tuning PLL circuit 16 is a tuning PL.
It is composed of an L-IC 32, a crystal oscillator 33, a capacitor C1 and a variable capacitance diode 34. Crystal oscillator 33, capacitor C1 and variable capacitance diode 34
Form a reference oscillation circuit.

In the DC correction circuit 15, the C / N voltage e1 from the video processing circuit 13 of FIG. 1 is led to the non-inverting input terminal (+) of the comparator 31. The output terminal of the comparator 31 is connected to the comparator 3 via the resistor R1.
It is connected to the inverting input terminal (-) of 1 and to the cathode of the variable capacitance diode 34 of the PLL circuit 16 for tuning.

In the tuning PLL circuit 16, a tuning P
The LL-IC 32 includes a crystal oscillator 33 and a capacitor C1.
Are connected in series. The variable capacitance diode 34 is connected in parallel to the capacitor C1. in this case,
The cathode of the variable capacitance diode 34 is connected to the connection point between the crystal oscillator 33 and the capacitor C1.

C / N voltage e1 from the video processing circuit 13
Is amplified by the DC correction circuit 15 and the C / N voltage h1
Is applied to the cathode of the variable capacitance diode 34.

When the C / N voltage h1 increases, the capacitance of the variable capacitance diode 34 decreases, and the oscillation frequency of the crystal oscillator 33 (oscillation frequency of the reference oscillation circuit) is finely adjusted to the higher side. When the C / N voltage h1 decreases, the capacitance of the variable capacitance diode 34 increases and the oscillation frequency of the crystal oscillator 33 is finely adjusted to the lower side.

With such a circuit configuration, the reference oscillator of the DC correction circuit 15 and the tuning PLL circuit 16 of FIG. 1 can be realized.

FIG. 3 shows the C / N from the video processing circuit 13.
The characteristic of the voltage e1 is different from that of FIG.
5 is a circuit diagram showing a configuration example when 5 is configured by inverting connection. FIG.

Reference numeral 41 is C from the video processing circuit 13.
The input terminal 41 is connected to the inverting input terminal (-) of the comparator 43 via the resistor R11.

On the other hand, a constant voltage + B is applied to the terminal 42. The terminal 42 is connected to the reference potential point through the series connection of the resistors R12 and R13. Resistance R12, R
The connection point of 13 is connected to the non-inverting input terminal (+) of the comparator 43. The output terminal of the comparator 43 is
It is connected to the inverting input terminal (−) of the comparator 43 and the output terminal 44 via the resistor R14. As a result, the C / N voltage h1 is output from the output terminal 44.

FIG. 4 is a graph showing the relationship between the input and output of the DC correction circuit 15 of FIG. 3, where the horizontal axis represents the C / N voltage e1 on the input side and the vertical axis represents the C / N voltage h1 on the output side. Is shown.

The C / N voltage h1 output from the DC correction circuit 15 is inverted and decreases with a slope of -1 with respect to the increase of the input C / N voltage e1.

In FIG. 5, the characteristic of the C / N voltage e1 from the video processing circuit 13 is different from that of FIG.
FIG. 3 is a circuit diagram showing a configuration example in the case where is configured by expansion connection for expanding a certain voltage range.

Reference numeral 51 is C from the video processing circuit 13.
The input terminal 41 is connected to the non-inverting input terminal (+) of the comparator 52.

On the other hand, the output terminal of the comparator 52 is connected to the reference potential point via the series connection of the resistors R21 and R22, and is also connected to the output terminal 53.

The connection point of the resistors R21 and R22 is connected to the inverting input terminal (-) of the comparator 52. As a result, the C / N voltage h1 is output from the output terminal 53.

FIG. 6 is a graph showing the relationship between the input and output of the DC correction circuit 15 of FIG. 5, where the horizontal axis shows the C / N voltage e1 on the input side and the vertical axis shows the C / N voltage h1 on the output side. Is shown.

The C / N voltage h1 output from the DC correction circuit 15 increases with a slope of 2 with respect to the increase of the C / N voltage e1 when the input C / N voltage e1 is below a predetermined level. When the input C / N voltage e1 is higher than the predetermined level, the level becomes constant.

FIG. 7 shows the DC correction circuit 15 and the tuning P of FIG.
FIG. 3 is a circuit diagram showing a configuration example of a circuit system of a reference oscillator of the LL circuit 16 and shows a simplified operation as compared with the case of FIG. 2.

In FIG. 7, the DC correction circuit 15 is composed of a comparator 71, a variable resistor R31 and a resistor R32. The tuning PLL circuit 16 is a tuning PLL-
IC81, crystal oscillator 82, capacitors C31, C
32 and an NPN transistor Tr31. Crystal oscillator 82 and capacitors C31 and C32
And the NPN transistor Tr31 form a reference oscillation circuit. In addition, capacitors C31 and C32 and N
The PN transistor Tr31 constitutes a switching means for switching the frequency of the crystal oscillator 82.

In the DC correction circuit 15, the C / N voltage e1 from the video processing circuit 13 of FIG. 1 is led to the non-inverting input terminal (+) of the comparator 71.

On the other hand, a constant voltage + B is applied to the terminal 72. The terminal 72 is connected to the reference potential point via the variable resistor R31. The sliding contact of the variable resistor R31 is
It is connected to the non-inverting input terminal (+) of the comparator 71. The output terminal of the comparator 71 is connected to the NPN transistor Tr31 of the tuning PLL circuit 16 via the resistor R32.
Connected to the base.

In the tuning PLL circuit 16, a tuning P
The LL-IC 81 includes a crystal oscillator 82 and a capacitor C3.
1 series connection is connected. A series connection of the capacitor C32 and the anode / cathode path of the NPN transistor Tr31 is connected in parallel to the capacitor C31.

C / N voltage e1 from the video processing circuit 13
Is less than the sliding contact voltage V31 of the resistor R31,
The C / N voltage h1 of the DC correction circuit 15 becomes a low level, and when the C / N voltage e1 exceeds the voltage V31, the C / N voltage h1 of the DC correction circuit 15 becomes a high level,
The C / N voltage e1 has a characteristic that it is proportional to the reception input level of the satellite broadcast signal. When the C / N voltage h1 is low level, the NPN transistor Tr31 is turned off,
No current flows through the capacitor C32, and the oscillation frequency of the crystal oscillator 33 (oscillation frequency of the reference oscillation circuit) is set to the higher frequency. When the C / N voltage h1 is at a high level, the NPN transistor Tr31 is turned on and a current also flows through the capacitor C32, and the crystal oscillator 33
Is set to a lower frequency.

In the case of such a circuit example, the sliding contact R31 of the variable resistor is adjusted so that the frequency of the reference oscillator is switched at a certain weak electric field. As a result, when the input voltage falls below a certain weak electric field input level, the oscillation frequency of the crystal oscillator 33 (oscillation frequency of the reference oscillation circuit) is set to the higher frequency so that the local oscillation frequency becomes a normal oscillation frequency. Since the correction can be performed, the reception input level at which the center frequency of the AFC shifts when the electric field is weak can be suppressed low.

With such a configuration example, the operation of the circuit system of the reference oscillator can be simplified as compared with the case of FIG.

In the embodiment of the invention shown in FIGS. 1 to 7, when the input level of the C / N voltage decreases and the noise component cannot be ignored, the C / N voltage operates with this noise component. Although the C / N voltage is used as the detection voltage, a signal level voltage, an AGC voltage or the like having the same function can also be used.

[0044]

As described above, according to the present invention, the center frequency of the automatic frequency control is performed by miscounting the frequency of the second intermediate frequency signal in the weak electric field. Since the deviation can be prevented, the input level of the satellite broadcast signal in which the truncation noise occurs can be lowered, and the user can be given a high impression.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an invention of an automatic frequency control circuit according to the present invention.

FIG. 2 is a circuit diagram showing the DC correction circuit of FIG. 1 and a circuit system of a reference oscillator of a tuning PLL circuit.

FIG. 3 is a circuit diagram showing a configuration example when the DC correction circuit of FIG. 1 is configured by inverting connection.

4 is a graph showing the relationship between the input and output of the DC correction circuit of FIG.

5 is a circuit diagram showing a configuration example in the case where the DC correction circuit of FIG. 1 is configured by expansion connection for expanding a certain voltage range.

6 is a graph showing the relationship between input and output of the DC correction circuit of FIG.

FIG. 7 is a circuit diagram showing a configuration example in which the operations of the DC correction circuit of FIG. 1 and the circuit system of the reference oscillator of the tuning PLL circuit are simplified.

[Explanation of symbols]

 12 PLL-FM demodulation circuit 13 Video processing circuit 14 Microcomputer 15 DC correction circuit 16 PLL circuit for channel selection 17 Local oscillation frequency

Claims (3)

[Claims] 1. A second intermediate frequency signal supplied from a second intermediate frequency converter of a 2nd converter of a satellite broadcast receiver is demodulated, the demodulated signal is taken out, and the second intermediate frequency signal is read by a built-in counter. Phase lock loop-frequency modulation / demodulation circuit that generates automatic frequency control voltage, and video processing that detects the weak electric field by the demodulation signal from this phase lock loop-frequency modulation / demodulation circuit and outputs the detection voltage of this detection result Circuit and the phase-locked loop-if the automatic frequency control voltage from the frequency modulation and demodulation circuit indicates an error in automatic frequency control, control data creating means for creating a control data signal that corrects this error, and an oscillation signal A local oscillation circuit to be supplied to the mixer for channel selection of the second intermediate frequency conversion unit, and control data from the control data creating means. The frequency of the internal reference oscillation circuit is shifted by the shift value of the frequency indicated by the signal, and the frequency of the reference oscillation circuit is corrected based on the detected voltage from the video processing circuit to oscillate from the local oscillation circuit. An automatic frequency characterized by comprising a tuning phase-lock loop circuit for controlling the local oscillation circuit so that the frequency of the divided output obtained by dividing the frequency of the signal and the frequency of the reference oscillation circuit match. Control circuit. 2. The reference oscillation circuit is composed of a crystal oscillator and a variable capacitance diode for adjusting the frequency of the crystal oscillator, and the detection voltage from the video processing circuit is applied to the variable capacitance diode to thereby form the crystal. 2. The automatic frequency control circuit according to claim 1, wherein the frequency of the oscillator is corrected based on the detected voltage. 3. The reference oscillation circuit comprises a crystal oscillator and switching means for switching the frequency of the crystal oscillator,
2. The automatic frequency control according to claim 1, wherein the switching means is controlled based on the detected voltage from the video processing circuit to correct the frequency of the crystal oscillator based on the detected voltage. circuit.