JP2001284814A - Method of forming wiring for signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in circuit characteristic and realize simple circuit design having high degree of freedom by reducing impedance step and parasitic capacitance in a viahole part. SOLUTION: A dielectric film 14 is formed moreover on a first wiring 13 formed on a substrate 11, and a viahole 16 is formed. A wall surface of the viahole 16 is partially metallized, a second wiring 19 is formed, and a viahole structure is obtained wherein an upper wiring and a lower wiring are electrically connected by the same width as wiring width. As a result, viahole structure which does not have impedance step and parasitic capacitance can be obtained, circuit characteristic is improved, design is simplified, and the degree of freedom can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a signal wiring used in a circuit board manufacturing process and the like.

[0002]

2. Description of the Related Art Conventionally, as a method for forming a signal wiring which has been used for manufacturing a circuit board, a method performed in steps shown in FIGS. 4 and 5 is known.

[0003] First, as shown in FIG.
A sheath metal layer 42 required for electrolytic plating in forming a wiring is formed thereon, and is patterned in a region where a first wiring is to be formed. Then, the first wiring 43 is formed on the sheath metal layer 42 by electrolytic plating or the like. As shown in FIG. 5A, a pad 43a is provided at a position where the via hole is arranged on the first wiring 43.

Then, as shown in FIG. 4B, a dielectric film 44 is formed on the substrate 41 on which the first wiring 43 is formed, a resist film 45 is formed thereon, and the resist film 45 is formed on the dielectric film 44. A via hole pattern 45a is formed.

Then, as shown in FIG. 4C, the patterned resist film 45 is used as an etching mask.
After the dielectric film 44 is subjected to via hole processing by dry etching, the resist film 45 is removed. On this occasion,
The formed via hole 46 is located on the pad 43a provided in the first wiring 43 as shown in FIG. 5B, and is designed such that the opening of the via hole 46 does not protrude from the pad 43a. You.

Next, as shown in FIG. 4D, a sheath metal layer 47 is formed on the dielectric film 44 on which the via hole processing has been performed, and a resist film 48 is formed thereon, and the resist film 48 is formed. Then, a second wiring pattern 48a is formed.

Finally, as shown in FIG. 4E, a second wiring 49 is formed on the sheath metal layer 47 by electrolytic plating using the resist film 48 as a mask, and the unnecessary sheath metal layer 47 is wetted. It is removed by etching. Thus, the formation of the second wiring 49 is completed.

At this time, as shown in FIG. 5C, a pad 50 is provided on the via hole 46 in the second wiring 49 similarly to the first wiring 43, and the pad 50
Is designed to completely cover the opening of the via hole 46.

[0009]

In the conventional wiring structure, the pads 43a, 5 located above and below the via hole are not provided.
0 is designed to completely cover the opening of the via hole 46. This is because the side wall of the via hole 46 is entirely metallized to ensure conduction and to improve the mechanical strength of the via hole.

In addition, the minimum diameter of the via hole is specified due to a restriction in a manufacturing process such as dry etching. As a result, the pad width is generally larger than the width of the wiring connected to the via hole. In such a structure,
An impedance step occurs in the via hole, resulting in a mismatch loss. For this reason, there is a possibility that the circuit characteristics may deteriorate. For this reason, it is necessary to extra estimate circuit characteristics such as signal levels in circuit design.

Further, since the pad itself has an area and has a parallel plate type capacitor structure with respect to the ground plane immediately below or directly above, a parasitic capacitance is attached to the via hole portion, and the circuit characteristics are affected. . For this reason, it is necessary to model a via hole in circuit design and then perform circuit design in consideration of parasitic capacitance.

As described above, the conventional via hole structure is
This causes mismatching loss and parasitic capacitance, thereby deteriorating circuit characteristics, complicating circuit design, and restricting the degree of freedom in design.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and by reducing impedance steps and parasitic capacitances in via holes, it is possible to prevent circuit characteristics from deteriorating and to make circuit design simple and highly flexible. The purpose is to.

[0014]

According to a method of forming a signal wiring of the present invention, a step of forming a patterned first wiring on a substrate and a step of forming a dielectric film so as to bury the first wiring are performed. Forming a via hole in the dielectric film, forming a second wiring having a width substantially equal to the first wiring partially along a side wall of the via hole, including.

According to this method, the second wiring having a width substantially equal to the first wiring is partially formed along the side wall of the via hole, so that the via having no impedance step and no parasitic capacitance is formed. A hole structure can be obtained.

In the signal wiring forming method of the present invention, in the above method, benzocyclobutene is used as a material of the dielectric film. According to this method, a low-loss signal wiring structure can be realized.

A circuit board according to the present invention is characterized by having a signal wiring manufactured by the above method. According to this configuration, it is possible to obtain a low-loss signal wiring board having a via hole structure having no impedance step and no parasitic capacitance.

In the signal wiring structure according to the present invention, a first wiring formed on a substrate and a via formed on the first wiring so as to expose the first wiring. A dielectric film having a hole, and a second wiring partially connected to the first wiring in the via hole, wherein the first and second wirings have substantially equal widths. In addition, the second wiring employs a configuration in which the second wiring is partially formed along a side wall of the via hole.

According to this structure, since the second wiring having a width substantially equal to the first wiring is partially provided along the side wall of the via hole, the via having no impedance step and no parasitic capacitance is provided. A hole structure can be obtained.

In the signal wiring structure of the present invention, in the above structure, the dielectric film is made of benzocyclobutene. According to this configuration, a low-loss signal wiring structure can be realized.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION The gist of the present invention is to reduce the impedance step and the parasitic capacitance by partially metallizing the wall surface of a via hole and forming a via hole in which the upper and lower wirings are conductive with a width equal to the wiring width. A via-hole structure having no via hole is obtained, thereby improving circuit characteristics, simplifying design, and increasing flexibility.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 are cross-sectional views for explaining steps of a method for forming a signal wiring according to an embodiment of the present invention.

First, as shown in FIG.
A sheath metal layer 12 required for electrolytic plating in forming a wiring is formed thereon, and is patterned in a region where a first wiring is to be formed. Then, the first wiring 13 is formed on the sheath metal layer 12 by electrolytic plating or the like. As shown in FIG. 2A, a pad 13a is provided at a position on the first wiring 13 where the via hole is arranged.

Next, as shown in FIG. 2B, a dielectric film 14 is formed on the substrate 11 on which the first wiring 13 has been formed, a resist film 15 is formed thereon, and the resist film 15 A via hole pattern 15a is formed.

Next, as shown in FIG. 1C, the patterned resist film 15 is used as an etching mask.
After subjecting the dielectric film 14 to via hole processing by dry etching, the resist film 15 is removed. On this occasion,
The formed via hole 16 is located on the pad 13a provided on the first wiring 13 as shown in FIG. 2B, and the size of the opening of the via hole 16 is larger than the size of the pad 13a. Is designed to be smaller.

Then, as shown in FIG. 1D, a sheath metal layer 17 is formed on the dielectric film 14 which has been subjected to the via hole processing, a resist film 18 is formed thereon, and the resist film 18 is formed. Then, a second wiring pattern 18a is formed.

At this time, the pattern 18a is formed so that the resist film 18 partially covers the via hole 16. As a result, a second wiring, which will be described later, is connected to the via hole 1.
6 will be partially formed. The pattern 18a is not particularly limited as long as the resist film 18 is formed so as to partially cover the via hole 16.

Finally, as shown in FIG. 1E, a second wiring 19 is formed on the sheath metal layer 17 by electrolytic plating using the resist film 18 as a mask.
After removing 8, the unnecessary sheath metal layer 17 is removed by wet etching or the like. Thus, the formation of the second wiring 19 is completed. In this case, the second
The wiring 19 has a width substantially equal to that of the first wiring 13 partially along the side wall of the via hole.

At this time, as shown in FIG. 2C, the second wiring 19 is formed in the via hole 1 provided in the dielectric layer 14.
6 partially covers the first wiring 13
The second wiring 19 conducts without changing the wiring width.

By repeating the above-described steps from FIG. 1A to FIG. 1E, a wiring board having a multilayer structure can be formed. At this time, the opening in the via hole formed by the above process is filled with a dielectric material and protected by a dielectric layer formed thereon.

In the multilayer wiring structure, the via hole located at the uppermost layer has a structure in which an opening surface is partially left. However, a dielectric layer is formed thereon and the via hole is filled. It is also possible to protect. At this time, with respect to a wiring portion such as a terminal that requires conduction in the uppermost layer wiring, conduction can be secured by partially removing the formed dielectric layer by dry etching or the like.

By using such a method for forming a signal wiring, the second wiring having a width substantially equal to the first wiring is partially formed along the side wall of the via hole. And a via-hole structure without parasitic capacitance are obtained, improving the circuit characteristics,
The design can be simplified and the degree of freedom can be increased.

Further, by using benzocyclobutene (BCB) having a small dielectric loss as a material of the dielectric film, it is expected that a circuit having a lower loss can be formed. BCB can form a film by spin coating and curing.
It is also possible to form a film having a thickness of about 30 μm, which is very effective for multi-layering and miniaturization of circuits. Therefore, B
By forming the wiring into multiple layers using the CB, it is possible to form a small-sized circuit board having a multilayer wiring structure with lower loss.

FIG. 3 shows an example of a device for a high-speed and large-capacity wireless system obtained by using the above-described signal wiring forming method. In this device, a wiring 34 is formed on a substrate 32 and each dielectric film 33 by using the above-described signal wiring forming method,
This is a multilayered circuit. Further, the uppermost layer includes Ga
The As active element 35 is mounted, and the filter 36 is formed (shielded in the figure). Reference numeral 31 in the figure is a shield case.

In such a device for a high-speed, large-capacity wireless system, since the frequency characteristics and the loss characteristics are particularly important, it is preferable to use the above-described signal wiring forming method. Performance can be enhanced.

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example, the material is not limited to the materials in the above embodiment. In the present invention, the thickness and width of the layer and the film, the depth of the groove and the pattern, and the like are not limited, and can be appropriately selected and implemented.

In the above embodiment, the case where the first wiring is provided directly on the substrate is described. However, in the present invention, a dielectric layer is provided on the substrate and the first wiring is provided thereon.
May be provided.

[0038]

As described above, according to the present invention, a dielectric film is formed so as to embed a patterned first wiring on a substrate, and a part of the dielectric film is formed with respect to a via hole formed in the dielectric film. Since the second wiring is formed, a via hole structure having no impedance step and no parasitic capacitance can be obtained, and the circuit characteristics can be improved, the design can be simplified, and the degree of freedom can be increased.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a first half of a method for forming a signal wiring according to an embodiment of the present invention;

FIG. 2 is a perspective view for explaining a latter half of a method for forming a signal wiring according to an embodiment of the present invention;

FIG. 3 is a diagram showing an example of a device for a high-speed large-capacity wireless system.

FIG. 4 is a cross-sectional view for explaining the first half of a conventional method for forming a signal wiring;

FIG. 5 is a perspective view for explaining the latter half of a conventional method for forming a signal wiring;

[Meaning of sign]

 DESCRIPTION OF SYMBOLS 11 Substrate 12 Sheath metal metal layer for 1st wiring formation 13 1st wiring 13a Pad for via hole in 1st wiring 14 Dielectric film 15 Resist film for via hole 16 Via hole 17 For 2nd wiring formation 18 metal wiring layer 18 second resist film 18a for forming second wiring 18a second wiring forming pattern 19 second wiring 31 shield case 32 substrate 33 dielectric film 34 wiring 35 GaAs active element 36 filter

Continuation of front page (72) Inventor Hiroshi Ogura F-term (reference) in Matsushita Communication Industrial Co., Ltd. 4-1, Tsunashimahigashi 4-3-1, Kohoku-ku, Yokohama-shi, Kanagawa 5E317 AA26 AA27 BB01 BB11 CC31 CC51 CD15 CD25 GG11 5E346 AA13 AA33 AA35 AA43 AA51 BB02 BB11 BB15 CC21 DD24 DD33 EE31 FF04 FF14 GG15 GG17 GG22 GG23 HH03 HH06

Claims (5)

[Claims] A step of forming a patterned first wiring on a substrate; a step of forming a dielectric film so as to bury the first wiring; and a step of forming a via hole in the dielectric film. Forming a second wiring having a width substantially equal to the first wiring partially along a side wall of the via hole. 2. The method according to claim 1, wherein benzocyclobutene is used as a material of the dielectric film. 3. A circuit board comprising a signal wiring formed by the method for forming a signal wiring according to claim 1. 4. A first wiring formed on a substrate, a dielectric film formed on the first wiring and having a via hole formed so as to expose the first wiring, And a second wiring partially connected to the first wiring in the via hole, wherein the first and second wirings have substantially equal widths, and the second wiring Is formed partially along the side wall of the via hole. 5. The signal wiring structure according to claim 4, wherein the dielectric film is made of benzocyclobutene.