JP2001284590A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a SOIMOSFET having a reduced short channel effect. SOLUTION: The SOIMOSFET comprises a semiconductor substrate of a first conductivity type, first insulation film (that is, a base oxide film) disposed on the semiconductor substrate, and SOI layer having a pair of source and drain of a second conductivity type which is disposed on the insulation film with a channel of a specified distance formed between the source and the drain. On the channel, a second insulation film (that is, a gate oxide film) and a gate electrode are formed. In the surface of the semiconductor substrate of a first conductivity type, there are an impurity region of a second conductivity type disposed below the channel and a high concentration impurity region of a first conductivity type which is disposed below the source and the drain and has a higher impurity concentration than that of the semiconductor substrate. Junctions between the high concentration impurity region of a first conductivity type and the impurity region of a second conductivity type are disposed just below the edges of the gate electrode or a little inside or outside of the edges.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor, and more particularly to a SOI (Silicion-On-Insulator) MOSF.
It relates to ET and its manufacturing method.

[0002]

2. Description of the Related Art With the development of semiconductor process technology, MO
The miniaturization of the gate length of the SFET is progressing. In the semiconductor process, the magnitude of the short channel effect is often used as one of the measures indicating the manufacturing margin of the channel length of the minimum design dimension. The short channel effect refers to a change in device characteristics caused by a decrease in the channel length, a decrease in the distance between the source and the drain, and an increase in the influence of the source and the drain on the electric field and potential distribution in the channel portion. Generally, the phenomenon is represented by a phenomenon in which the threshold voltage sharply decreases as the channel length decreases.

If the channel length is extremely short, a depletion layer extending from the source to the drain cannot be separated between the source and the drain, and the switching characteristics due to the gate voltage will be impaired. In response to the miniaturization of MOSFETs,
A device design that sufficiently suppresses the short channel effect is required.

An SOI (Silici) in which an element is formed on an insulating film
It is known that an on-on-insulator transistor has a smaller short channel effect than a MOSFET formed in a bulk. FIG. 7A shows such a SOIMOSF.
It is an example of ET.

[0005] The SOIMOSFET shown in FIG.
A second conductivity type (for example, n) is formed on the SiO ₂ insulating film 705 covering the semiconductor substrate 701 of the first conductivity type (for example, p-type).
Source) 706, drain 707, channel 708
Is formed on the SOI layer. The SOI layer is an insulating film 7
The minority carriers are likely to accumulate in the channel 808 because they are in an electrically floating state due to the presence of 05. Therefore, the sub-threshold current is steep, the switching characteristics are excellent, and the short channel effect can be relatively suppressed.

[0006]

However, such ability to prevent short channel effects is only a matter of degree,
Also in the OSFET, the short channel effect is always a problem when miniaturizing a device. So SOIMOS
In order to improve the short channel effect related to the FET, Japanese Patent Application Laid-Open No. 08-153880 discloses that the thickness of a base oxide film is reduced to affect the potential distribution in the SOI channel portion by the impurity distribution in the substrate region and to reduce the source distribution of the SOI layer. ,
Perform ion implantation on the substrate region corresponding to the drain position,
A method for optimizing the potential distribution of the channel is proposed. FIG. 7B shows such an improved SOIMOS.
1 shows a configuration of an FET.

In the SOI MOSFET of FIG. 7B, the thickness of the base oxide film 805 is set to be thinner than that of the conventional type shown in FIG. 7A, and the SOI MOSFET is formed just below the n-type source 806 and the drain 807 of the SOI layer. , P-type high-density impurity region 80
2, 803 are provided. By providing the high-density impurity region in the substrate, the potential distribution of the channel 808 of the SOI layer is controlled and optimized.

However, the SOIMOSF shown in FIG.
ET has an improved SOI, despite improved short channel characteristics.
There is no regulation on the impurity profile of the substrate region immediately below the channel 808 of the layer, leaving room for further improvement.

Also, a configuration is known in which only an impurity region of the conductivity type opposite to that of the substrate is formed in the substrate immediately below the channel of the SOI layer. However, this configuration is intended to prevent inversion. The impurity profile in the substrate immediately below the source and drain of the SOI layer is not mentioned.

Accordingly, the present invention provides an SOI MOSFET which can further improve the short channel characteristics and effectively prevent a decrease in threshold voltage even if the device is miniaturized.
And a method for manufacturing the same.

[0011]

In order to achieve the above object, an SOI MOSFET of the present invention has a thin insulating film (underlying oxide film) between a substrate and an SOI layer, and has an SOI MOSFET.
In the substrate located immediately below the channel of the I layer, there is a region of a conductivity type different from the high-density impurity region formed in the substrate immediately below the source and drain. With this configuration, the reverse short channel effect can be intentionally made obvious, and the short channel effect can be effectively suppressed. The reverse short channel effect refers to a phenomenon in which the threshold voltage jumps momentarily immediately before the threshold voltage sharply drops due to a decrease in channel length. For example, if the conductivity type of the high-density impurity region in the substrate corresponding to the source and drain of the SOI layer is p-type,
An n-type impurity region is formed in the substrate immediately below the channel of the SOI layer. Then, the potential difference at the pn junction in the substrate becomes S
The influence on the OI region can make the reverse short channel apparent. In the SOIMOSFET of the present invention, the SOI
It is important to reduce the thickness of the insulating film (base oxide film) between the layer and the substrate, and to have a pn junction in the substrate.

More specifically, the SOIMOSFET of the present invention
Is a semiconductor substrate of a first conductivity type, a first insulating film located on the semiconductor substrate, and a pair of source and drain of a second conductivity type located on the first insulating film and sandwiching a channel of a predetermined distance. A semiconductor layer formed at a position corresponding to the channel on the surface of the semiconductor substrate, and a semiconductor substrate formed at a position corresponding to the source and the drain on the surface of the semiconductor substrate A high-concentration impurity region of the first conductivity type having a higher impurity concentration, a second insulating film located on the channel, and a gate electrode located on the second insulating film.

The thickness of the first insulating film is not less than 10 nm and not more than 20 nm.
nm or less. By setting the thickness of the first insulating film to 20 nm or less, the potential difference at the pn junction formed on the surface of the semiconductor substrate below the first insulating film affects the semiconductor layer channel region on the first insulating film. be able to. As a result, the reverse short channel effect in the channel region becomes apparent, and a drop in the threshold voltage can be prevented even with an extremely small channel length. On the other hand, in the case where the first insulating film is extremely thin, there is a limitation due to process restrictions, such as the need to take into consideration the penetration of impurities through this region (the passage in a normal state other than ion implantation). Therefore, the thickness of the first insulating film is preferably 10 nm or more.

The thickness of the semiconductor layer located on the first insulating film is determined in consideration of the easiness of manufacturing and handling the device.
It is preferably from 20 nm to 30 nm.

The impurity concentration of the high-density impurity region of the first conductivity type source and drain under the semiconductor substrate surface is 10 ³ times or more the impurity concentration of the semiconductor substrate is preferably 10 ⁴ times or less. On the other hand, the impurity concentration of the impurity region of the second conductivity type located on the surface of the semiconductor substrate below the channel is 10 times or more the impurity concentration of the semiconductor substrate.
It is preferably not less than ^twice.

The method of manufacturing a semiconductor device according to the present invention comprises:
A first insulating film (base) is formed on a semiconductor substrate of a first conductivity type. A semiconductor layer (SOI layer) of the first or second conductivity type is formed on the first insulating film. Ions of the second conductivity type are implanted from the surface of the SOI layer so that the projected range reaches the surface of the semiconductor substrate below the first insulating film;
The layer and the surface of the semiconductor substrate are of the second conductivity type. A second insulating film (gate oxide film) and a gate electrode are formed on the SOI layer. Using the gate electrode as a mask, ions of the first conductivity type are ion-implanted so that the projection range reaches the surface of the semiconductor substrate, and both sides of the second conductivity type SOI layer and the semiconductor substrate correspond to both sides of the gate electrode. A high-density region of the first conductivity type is formed at the position where the first conductivity type is to be formed. Finally, the second gate electrode is used as a mask so that the projected range reaches the bottom of the SOI layer.
Conductive-type ions are ion-implanted to make the high-density region of the first conductivity type of the SOI layer a high-density region of the second conductivity type.

According to such a manufacturing method, the S having a high-density pn junction on the surface of the semiconductor substrate under the first insulating film.
OIMOSFETs can be manufactured.

The other features and effects of the present invention will become more apparent by the embodiments described below.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows an SOI MOSFET 100 according to a first embodiment of the present invention. SO
The IMOSFET 100 includes a p-type semiconductor substrate 101,
A first SiO ₂ insulating film (that is, a base oxide film) 105 located on a mold semiconductor substrate and a first SiO ₂ insulating film 10
5 (hereinafter referred to as “SOI layer”)
And a second SiO ₂ insulating film 109 located on the SOI layer
And a tungsten gate electrode 110 on the _second SiO ₂ insulating film 109. The SOI layer has a gate electrode 11
It includes a channel 108 of a predetermined length located below 0, and a pair of n ⁺ type source 106 and drain 107 sandwiching the channel 108.

The p-type semiconductor substrate 101 has an n-type impurity region 1 located below the channel 108 near its surface.
04 and p ⁺ -type impurity regions 102 and 103 located below the source and the drain. This n-type impurity region 1
04 and p ⁺ -type impurity regions 102 and 103 sandwiching the
Forms a pn junction on the surface of the semiconductor substrate 101 immediately below the end of the gate 110. p ⁺ -type impurity region 10
The impurity concentration of 2 and 103 is about 10 ¹⁸ cm ⁻³ , and the impurity concentration of n-type impurity region 104 is 10 ¹⁷ cm ^−3.
It is about ^-3 . Further, the impurity concentration of the p-type semiconductor substrate 101 is about 10 ¹⁶ cm ⁻³ .

The thickness of the first insulating film 105 is 10 nm to 2 nm.
The range is 0 nm. In this embodiment, the thickness is set to 20 nm.
And the thickness of the SOI layer including the source / drain is set to 3
It was set to 0 nm. The impurity concentration of the n-type channel 108 formed in the SOI layer is about 3 × 10 ¹⁶ cm ⁻³ .
By setting the thickness of the first insulating film 105 to about 20 nm, the threshold voltage of the MOS transistor can be controlled by the impurity profile on the semiconductor substrate 101 side. In particular, by using a region having a conductivity type opposite to that of the p ⁺ -type impurity regions 102 and 103 immediately below the source / drain immediately below the channel 108, the reverse short channel effect becomes apparent, and the threshold accompanying the miniaturization of the device is obtained. It is possible to suppress a sharp drop in voltage. SOIM of the present invention
The manifestation of the reverse short channel effect by the OSFET will be described later with reference to FIG.

FIG. 2 shows the SOI MOSFET 1 shown in FIG.
It is a figure which shows the manufacturing process of 00.

(I) First, as shown in FIG. 2A, a p-type semiconductor substrate 201 having an impurity concentration of about 10 ¹⁶ cm ^−3.
A first insulating film 205 made of a silicon oxide film and having a thickness of 20 nm is formed thereon.
A p-type SOI layer 208 of ¹⁶ cm ^-3 or less is deposited to a thickness of 30 nm. On the SOI layer 208, a sacrificial oxide film 211 is formed to a thickness of about 6 nm. In this structure, an n-type ion, for example, arsenic (As) is projected onto the first insulating film 2 with a projection range.
Ion implantation is performed so as to reach the surface of the p-type semiconductor substrate 201 below the substrate 05. In the first embodiment, As is represented by energy 1
Ion implantation was performed at 50 keV and a dose of 2 × 10 ¹² cm ⁻² .

(Ii) By such ion implantation, FIG.
As shown in FIG. ¹⁷cm^-3degree
N-type region 204 is formed on the surface of p-type semiconductor substrate 201
Is done. Activation of the n-type region 204 is performed by a gate oxidation
Or an additional annealing step.
No. This As implantation causes the SOI layer 208 to have a peak density.
Degree 3 × 10¹⁶cm^-3N-type region. As injection
Thereafter, the sacrificial oxide film 211 is peeled off.

(Iii) Next, as shown in FIG. 2C, a SiO ₂ gate oxide film 209 is formed to a thickness of about 6 nm by thermal oxidation, and a 400 nm thick film is formed thereon by a CVD method or the like.
A tungsten film of about m is deposited. After that, RIE
The gate electrode is patterned by (reactive ion etching) to obtain the shape shown in FIG. In this state, p-type ions are implanted using the gate electrode as a mask. Specifically, in the first embodiment, boron (B) is implanted at an energy of 60 keV and a dose of 2 × 10 ¹² cm ⁻² .

(Iv) As a result of boron implantation, as shown in FIG. 4D, high-density p ⁺ -type impurity regions 202 and 203 on the surface of the p-type semiconductor substrate 201 and high-density P ⁺ -type impurity regions 206 and 207 are formed. In this state, n-type ions are implanted so shallowly that the projected range reaches the bottom surface of the SOI layer. In the first embodiment, arsenic (As) is supplied at an energy of 20 keV and a dose of 1 × 10 ^14.
cm ^-2 was injected.

(V) As a result of As implantation, as shown in FIG. 4E, p ⁺ -type impurity regions 206 and 207 of the SOI layer are formed.
Becomes a high-density n ⁺ -type region, and the n-type channel 208
, A source 26 and a drain 207 are formed.

Thereafter, through a wiring step (not shown), the SO
Complete the IMOSFET. By such a manufacturing method, high-density channel p ⁺ -type impurity regions 202 and 203 are formed on the surface of the p-type semiconductor substrate 201 having the conductivity type opposite to that of the n-type source and drain, and the n-type regions are formed below the channel. 204 can be formed.

<Second Embodiment> FIG. 3 shows an SOIMOSFET 300 according to a second embodiment of the present invention. SO
The IMOSFET 300 is similar in structure to the SOI MOSFET according to the first embodiment shown in FIG. The difference is that in the SOI MOSFET 100 of FIG. 1, the pn junction on the surface of the p-type semiconductor
The SOIM shown in FIG.
In the OSFET 300, the p-type semiconductor substrate 301
The n-junction is approximately 20 nm from the position immediately below the end of the gate 310.
It is inside the gate. Assuming that the position immediately below the gate is 0, the outside of the gate is a plus (+) position and the inside of the gate is a minus (-) position. Therefore,
In the example of FIG. 3, the position of the pn junction is -20 nm. In order to make the pn junction position below the first insulating film 305 enter the inside of the gate end, thermal diffusion is used.
Therefore, about -20 nm is almost the limit.

The roll-off characteristic can be improved by changing the pn junction position. Therefore, the effect that the threshold voltage can be maintained relatively constant even when the channel width is considerably shortened appears. This will also be described later with reference to FIG.

In the SOI MOSFET 300 of FIG. 3, the impurity concentration of the n-type impurity region immediately below the channel on the surface of the p-type semiconductor substrate 301 is set to about 4 × 10 ¹⁷ cm ⁻³ .

<Third Embodiment> FIG. 4 is a view showing a manufacturing process of an SOI MOSFET 400 according to a third embodiment of the present invention. In the SOI MOSFET 400, the position of the pn junction on the surface of the semiconductor substrate is located outside the end of the gate 410 as compared with the first embodiment. SO
The manufacturing process of the IMOSFET 400 is the same as that of the first embodiment.
Similar to the manufacturing process of OIMOSFET 100, except that pn
In order to set the bonding position to the outside, a step of providing side walls on both sides of the gate is added.

The steps shown in FIGS. 4A and 4B correspond to the first step.
2A and 2B according to the embodiment;
Are identical. However, the impurity concentration of the n-type impurity region 404 immediately below the channel on the surface of the semiconductor substrate is 8 × 10
As ions are implanted so as to be about ¹⁶ cm ^-3 .

In the case of affirmation shown in FIG.
After patterning the gate electrode 410 in the same manner as described in (c), sidewalls 412 are formed on both sides of the gate electrode 410. The side wall 412 can be formed, for example, by depositing SiN (silicon nitride) by CVD and etching by RIE. Boron (B) is implanted through this side wall 412 at an energy of 60 keV and a dose of 2 × 10 ¹² cm ⁻² . Since the side wall 412 also functions as a mask, the junction position between the high-density p ⁺ -type impurity regions 402 and 403 formed on the surface of the p-type semiconductor substrate 401 and the n-type impurity region 404 can be determined even if thermal diffusion is taken into consideration. It will be located outside the position immediately below the end of the 410 end. In the third embodiment, the pn junction position is +20 nm when 0 is set immediately below the gate.

Thereafter, as shown in FIG.
12 is removed, As is ion-implanted in the same manner as described in the first embodiment, and an n ⁺ type source 40 is implanted in the SOI layer.
6 and the drain 407 are formed.

SOI MOSFET according to Third Embodiment
In 400, the position of the pn junction under the first insulating film 405 was shifted to the opposite side to the second embodiment, that is, outside the position immediately below the gate. Due to such a pn junction position and the impurity distribution in the p-type semiconductor substrate, a thickness of 20 n
channel 40 of the SOI layer via the first insulating film 405
8 short channel characteristics can be controlled. In particular, at the pn junction position in the third embodiment, even if the channel length is reduced to 0.1 μm, the short channel characteristics are improved to a state where a threshold voltage drop hardly occurs.

FIG. 5 shows an SOIMOSFET according to the first to third embodiments of the present invention and a conventional SOIMOSFET.
6 is a graph showing the change in the threshold voltage with respect to the channel length obtained by device simulation. In the drawing, a broken line A and a solid line B show the characteristics of the conventional SOI MOSFET shown in FIGS. 7A and 7B, respectively. on the other hand,
Lines C, D, and E correspond to the SOI MOSFETs of the first, second, and third embodiments, respectively, of the present invention.

As is clear from the graph, the conventional SOI
In the MOSFET, the threshold voltage sharply drops from a channel length of about 0.18 μm, and the short channel effect is large. This means that switching cannot be performed accurately with a design rule of 0.18 μm. On the other hand, the characteristics of the SOIMOSFET of the first embodiment indicated by the dotted line C are such that the reverse short channel effect appears remarkably from around 0.2 μm, and that the drop of the threshold voltage is prevented until the channel length becomes about 0.12 μm. Can be.

In the example in which the position of the pn junction formed on the surface of the semiconductor substrate via the first insulating film is changed, when the pn junction is set inside the position immediately below the gate (−20 nm), it is indicated by a chain line D. Thus, the inverse short channel effect and the short channel effect cancel each other, and the channel length is set to 0.1.
Even when approaching 2 μm, a stable threshold voltage can be maintained. Further, as in the third embodiment, pn
When the junction is set to the outside (+20 nm) immediately below the gate, the channel width is set to 0.1 μm as shown by the two-dot chain line E.
The threshold voltage can be kept stable even when approaching.

FIG. 6 is a table summarizing the configuration conditions of the five types of devices A to E shown in the graph of FIG. As described above, A and B have the conventional configuration shown in FIGS. 7A and 7B, and C, D, and E correspond to the first to third embodiments of the present invention, respectively. .

As described above, in the first to third embodiments, the n-channel SOI MOSFET has been described. However, it is needless to say that the present invention can be applied to the p-channel SOI MOSFET.

[0043]

According to the present invention, the thickness of the insulating layer located between the semiconductor substrate and the SOI layer is reduced to about 20 nm, and the impurity profile on the surface of the semiconductor substrate, particularly, the SOI is reduced by the pn junction on the substrate surface. The reverse short channel effect of the layer can be realized. As a result, the channel length is set to 0.1 μm
Even if it is narrowed down, the short channel effect can be prevented,
It is possible to maintain a stable threshold voltage.

[Brief description of the drawings]

FIG. 1 shows a SOIMOSFE according to a first embodiment of the present invention.
It is sectional drawing of T.

FIG. 2 is a diagram showing a manufacturing process of the SOIMOSFET shown in FIG.

FIG. 3 shows a SOIMOSFE according to a second embodiment of the present invention.
It is sectional drawing of T.

FIG. 4 shows a SOIMOSFE according to a third embodiment of the present invention.
It is a figure showing the manufacturing process of T.

FIG. 5 is a SOIM according to the first to third embodiments of the present invention.
4 is a graph showing threshold voltage as a function of channel length for OSFET and conventional SOIMOSFET.

FIG. 6 shows a SOI MOSFET according to the first to third embodiments of the present invention shown in a graph of FIG.
4 is a table showing a configuration condition with an FET.

FIG. 7 is a diagram showing a configuration of a conventional SOI MOSFET.

[Explanation of symbols]

100, 300, 400 SOIMOSFETs 101, 201, 301, 401 p-type semiconductor substrate 102, 202, 302, 402 p-type high-density impurity regions 103, 203, 303, 403 immediately below the source p-type high-density impurity regions immediately below the drain 104, 204, 304, 404 n-type impurity regions 105, 205, 305, 405 immediately below the channel first insulating film (underlying oxide film) 106, 206, 306, 406 n-type source regions 107, 207, 307, 407 n-type Drain region 108, 208, 308, 408 N-type channel region 109, 209, 309, 409 Second insulating film (gate insulating film) 110, 210, 310, 410 Gate electrode 211, 411 Sacrificial oxide film 412 Gate sidewall

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[Procedure amendment]

[Submission date] April 3, 2000 (200.4.3)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005] The SOIMOSFET shown in FIG.
A second conductivity type (for example, n) is formed on the SiO ₂ insulating film 705 covering the semiconductor substrate 701 of the first conductivity type (for example, p-type).
Source) 706, drain 707, channel 708
Is formed on the SOI layer. The SOI layer is an insulating film 7
The minority carriers are likely to accumulate in the channel 708 because they are in an electrically floating state due to the presence of the carrier 05. Therefore, the sub-threshold current is steep, the switching characteristics are excellent, and the short channel effect can be relatively suppressed.

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] Fig. 6

[Correction method] Change

[Correction contents]

FIG. 6

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F110 AA08 AA30 CC02 DD05 DD13 EE04 EE32 EE45 FF02 FF23 GG02 GG12 GG25 GG28 GG32 GG34 GG52 GG58 HJ01 HJ04 HJ12 QQ11

Claims (11)

[Claims] A first conductive type semiconductor substrate; a first insulating film located on the semiconductor substrate; and a pair of second conductive types located on the first insulating film and sandwiching a channel of a predetermined distance. A semiconductor layer having a source and a drain of: a second conductivity type impurity region located below the channel on the surface of the semiconductor substrate; and a semiconductor layer located below the source and drain on the surface of the semiconductor substrate. A first conductive type high-density impurity region having an impurity concentration higher than that of the substrate; a second insulating film located on the channel; and a gate electrode located on the second insulating film. Semiconductor device. 2. The method according to claim 1, wherein the first insulating film has a thickness of 10 nm or more.
2. The semiconductor device according to claim 1, wherein the thickness is 20 nm or less. 3. The semiconductor device according to claim 1, wherein the thickness of the semiconductor layer on the first insulating film is 2
3. The semiconductor device according to claim 2, wherein the thickness is not less than 0 nm and not more than 30 nm. Wherein the impurity concentration of the high-density impurity region of the first conductivity type located in said source and drain beneath the surface of the semiconductor substrate, the semiconductor substrate impurity concentration of 10 ³ times or more, is 10 ⁴ times or less, The impurity concentration of the second conductivity type impurity region located on the surface of the semiconductor substrate below the channel is 10 times or more the impurity concentration of the semiconductor substrate.
^2. The semiconductor device according to claim 1, wherein the number is twice or less. 5. A high-concentration impurity region of the first conductivity type located on the surface of the semiconductor substrate below the source and the drain,
2. The semiconductor device according to claim 1, wherein a junction with an impurity region of a second conductivity type located on a surface of the semiconductor substrate below the channel is located immediately below an edge of the gate electrode. 3. 6. A high-concentration impurity region of a first conductivity type located on a surface of the semiconductor substrate below the source and the drain,
2. The semiconductor according to claim 1, wherein the junction with the second conductivity type impurity region located on the surface of the semiconductor substrate below the channel is located inside the gate than immediately below the edge of the gate electrode. 3. apparatus. 7. A high-concentration impurity region of a first conductivity type located on a surface of the semiconductor substrate below the source and the drain,
2. The semiconductor according to claim 1, wherein the junction with the second conductivity type impurity region located on the surface of the semiconductor substrate below the channel is located outside the gate than immediately below an edge of the gate electrode. 3. apparatus. 8. The semiconductor device according to claim 1, wherein the channel is of a second conductivity type. 9. The semiconductor device according to claim 1, wherein the channel is of a first conductivity type. 10. A step of forming a first insulating film on a semiconductor substrate of a first conductivity type; a step of forming a semiconductor layer of a first or second conductivity type on the first insulating film; From the surface, ions of the second conductivity type are ion-implanted so that the projection range reaches the surface of the semiconductor substrate below the first insulating film, and the semiconductor layer and the surface of the semiconductor substrate are changed to the second conductivity type. Forming a second insulating film and a gate electrode on the semiconductor layer; and ion-implanting ions of the first conductivity type using the gate electrode as a mask so that a projected range reaches the surface of the semiconductor substrate. Forming high-density regions of the first conductivity type at positions corresponding to both sides of the gate electrode in both the semiconductor layer and the semiconductor substrate of the second conductivity type; As degree reaches the semiconductor layer bottom surface, the ions of the second conductivity type by ion implantation, a high-density region of the first conductivity type of the semiconductor layer and the second
Forming a conductive type high-density region. 11. The method according to claim 11, further comprising the step of providing side walls on both sides of the gate electrode after the step of forming the gate electrode, wherein the first conductivity type ion implantation step in which the projection range is performed on the surface of the semiconductor substrate includes the step of: The method of manufacturing a semiconductor device according to claim 10, wherein the method is performed via a semiconductor device.