JP2001284169A - Capacitor array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor array which can realize compactness in size and a large capacity. SOLUTION: This capacitor array is comprised of a pair of first leads, where a capacitor unit Na1 consisting of internal electrodes 2a and 3a and a capacitor unit Na2, consisting of inner electrodes 4a and 5a are laminated alternately and which are led out from the inner electrodes 2a and 3a of the first capacitor unit in one direction of a laminate 1, a pair of second leads which are led out from the internal electrodes 2a and 3a in the other direction, and a pair of third leads which are led out from the inner electrodes 4a and 5a of a second capacitor unit, and the one sides of the second and third leads or the other side thereof are respectively connected with each other in common, so as to form a pair of outside electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor array in which a plurality of capacitors are formed on a laminate formed by laminating a plurality of dielectric layers.

[0002]

2. Description of the Related Art With the spread of various electronic devices, the size and weight of these devices have been rapidly reduced. Especially in recent years,
There is an increasing demand for smaller and lighter electronic devices for portable use, such as a camera-integrated VTR, a mobile phone, a notebook personal computer, and a palmtop computer.

[0003] If the size and weight of such electronic devices are reduced, the circuit boards used for the electronic devices must be reduced in size and weight. From the mounting type, in which the pins of the electronic components are inserted into the through holes formed in the printed circuit board and soldered, the electronic components are placed and soldered on the conductive pattern lands provided on the printed circuit board to reduce the size and weight To surface mount technology (SMT).

The electronic components used in the SMT are collectively referred to as surface mount components (SMD). For example, a capacitor array having a plurality of built-in capacitors as disclosed in Japanese Patent No. 2657953 is a typical example. .

FIG. 5 shows an external view of a conventional capacitor array 30. In FIG. 5, (a) is an external perspective view, and (b)
Is a front view. 6A and 6B are cross-sectional views of the capacitor array 30 of FIG. 5, in which FIG. 6A is a partial cross-sectional view taken along line AA, and FIG. 6B is a cross-sectional view taken along line BB. FIG. As shown in the figure, the capacitor array 30 includes a plurality of internal electrodes 33 (33a, 33b) and 34 between each layer of the multilayer body 300 in which a plurality of dielectric layers 30a are stacked.
(34a, 34b)... Are formed. The internal electrodes 33 and 34 are led to different positions on the end face side of the multilayer body 300, and the external electrodes 35 (35a, 35b) and 36 (36a, 3) are provided on the end face side of the multilayer body 300.
6b). That is, the internal electrode 33a is connected to the external electrode 35a, the internal electrode 33b is connected to the external electrode 36a, the internal electrode 34a is connected to the external electrode 35b, and the internal electrode 34b is connected to the external electrode 36b.

The capacitor unit 38 is formed by the dielectric layer 30a, the internal electrode 33, and the external electrodes 35 and 36. This capacitor unit 38 (38a, 38b
..) indicates the surface of the internal electrode and the dielectric layer 3
A plurality of capacitor arrays h are formed in the lamination direction of the capacitor array 0a.

The use of such a capacitor array 30 makes it possible to combine individual capacitors into a single unit, suppress variations in the size and shape of each capacitor, and reduce the mounting work on a circuit board. It can be simplified.

Further, conventionally, when mounting a multilayer ceramic capacitor on a printed circuit board or the like, it is necessary to provide a land that is slightly larger than the capacitor element on the circuit board, and it is difficult to mount the capacitor at high density. However, the use of the capacitor array 30 enables high-density mounting, reduces the number of mountings, and can reduce mounting costs.

[0009]

However, it is often necessary to arrange capacitors on the mounting surface of the circuit board. In such a case, according to the capacitor array 30, since the capacitor arrays h are aligned only in one direction in the stacking direction, a plurality of capacitor arrays 30 must be used in order to further increase the density. However, there is a problem that it is insufficient for further high-density mounting.

According to the capacitor array 30, the external terminal electrodes 35a and 35b between the adjacent capacitor units 38a and 38b or the external terminal electrodes 36a and 36b are electrically connected to each other on the end surface of the laminate by soldering on the board mounting surface. It is necessary to provide a distance so that it does not occur.
Generally, the distance y between the external terminal electrodes is designed to be substantially the same as the diameter x of the external terminal electrode, or in order to form a further high-density capacitor as shown in FIG. The distance y between the terminal electrodes is formed short. At this distance y between external terminal electrodes, it is necessary to intervene a large number of dielectric layers 30a not interposing the internal electrodes between the adjacent internal electrodes 33b-34a, and since this portion 37 does not generate a capacitance, it is merely an insulating layer. In addition, there is a problem that there is a possibility that a product size may be increased in response to a product request for a small size and a large capacity.

Furthermore, with the miniaturization and high capacity, when the capacitor array 30 is mounted on a circuit board, there is a possibility that a connection failure between the terminals of the circuit board and the external electrodes 35 and 36 of the capacitor array 30 may occur. In some cases, a small chip may make it difficult to determine the size of the chip.

The present invention has been achieved in view of the above problems, and an object of the present invention is to provide a capacitor array capable of realizing high-density mounting.

Another object of the present invention is to provide a capacitor array which can easily determine the electrical connection between the terminals of the circuit board and the external electrodes of the capacitor array even if the size is reduced.

[0014]

In order to solve the above-mentioned problems, a capacitor array according to the present invention has a structure in which a plurality of dielectric layers are laminated in a rectangular laminated body having potentials different from each other across the dielectric layer. The first in which a plurality of internal electrodes are arranged facing each other,
A capacitor array in which a plurality of second capacitor units are alternately arranged in the direction in which the dielectric layers are stacked, and the internal electrodes of the first capacitor unit are respectively provided on one main surface of the stacked body. And a second lead-out portion leading out to the other main surface side of the laminate, and each internal electrode of the second capacitor unit is provided with a first lead-out portion leading to the other side. A third lead-out portion leading out to the other main surface side of the body, and a second lead-out portion having the same electric potential among the second lead-out portions on the other main surface of the laminate; The deriving unit and a third deriving unit having the same potential are commonly connected.

According to the structure of the present invention, each of the second lead-out portions having the same potential among the second lead-out portions and the third lead-out portion having the same potential as the second lead-out portion are provided on the other main surface of the laminate. Since the lead-out section is connected in common, the capacitance of both the first and second capacitor units is generated simply by connecting to the first lead-out section. Can be provided.

In the case of forming a pair of first external electrodes connected to the first lead-out portion of the first capacitor unit, for example, when one of the main surfaces is a mounting surface,
Since only the pair of first external electrodes connected to the capacitor unit are exposed on the mounting surface (the external electrodes of the second capacitor unit are not exposed on one main surface), the distance between the pair of first external electrodes And a capacitor array in which connection failures are prevented can be provided.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. FIGS. 1A and 1B are diagrams illustrating the configuration of a capacitor array 10 according to the present invention. FIG. 1A is an external perspective view of the capacitor array 10, FIG. 1B is a plan view thereof, and FIG. , The shaded area indicates the same pole). FIGS. 2A and 2B are diagrams for explaining the internal electrodes and the external electrodes of the capacitor array 10 of the present invention. FIG. 2A shows the positional relationship of the external electrodes of the present invention, and FIG. 2B shows the positional relationship of a pair of external terminal electrodes. (In FIG. 2, a dotted line indicates an internal electrode, and a colored portion indicates a connecting portion between the internal electrode and the external electrode.) FIG. 3 is a partial cross-sectional view in the lateral direction of the capacitor array 10 of the present invention (in FIG. 3, dashed lines indicate external electrodes perpendicular to the plane of the paper). FIG. 4 is a partial longitudinal sectional view of the capacitor array 10 of the present invention. In FIG. 4, a colored portion indicates a portion connected to the internal electrode and the external electrode, and a dashed line indicates an external electrode in a direction perpendicular to the paper surface. Also, a pair of first external electrodes formed on one main surface of the laminate will be referred to as external terminal electrodes, and a common external electrode formed on the other main surface will be referred to as an external connection electrode.

Referring to FIG. 1, a capacitor array 1 according to the present invention is shown.
Numeral 0 denotes, for example, a rectangular laminated body 1 formed by laminating a plurality of dielectric layers 1a.
Are formed in the stacking direction. The capacitor unit N includes capacitor units Na ₁ and Nb _{1 that} are first capacitor units and capacitor units Na ₂ and Nb ₂ that are second capacitor units.
The first and second capacitor units are formed alternately with each other.

The dielectric layer 1 is made of a green sheet formed in a strip shape, and is made of a dielectric material such as barium titanate or strontium titanate.

The capacitor unit Na _1, which is the first capacitor unit, sandwiches the dielectric layer 1 of the laminate 1,
It has at least two internal electrodes 2a and 3a facing each other, and as shown in FIG. 3A, one of the internal electrodes 2a is led out to one principal surface side on which the stacked body 1 is mounted ( 1 leading portion), which is connected to the external terminal electrode 6 formed on one main surface of the multilayer body 1, and the other of the internal electrodes 2 a is led to the other main surface side facing the one main surface of the multilayer body 1 ( The second lead portion) is connected to an external connection electrode 8a formed on the other main surface of the multilayer body 1. Similarly, the internal electrode 3a is connected to each of the external terminal electrode 7 and the external connection electrode 8b. The capacitor unit Nb ₁ also capacitor unit Na ₁ similarly to the internal electrodes 2b, 3b are external terminal electrodes 6 and 7, the external connection electrodes 8b, are respectively connected to 9b.

As shown in FIG. 2, a capacitor unit Na _{2 as a second} capacitor unit has at least two internal electrodes 4a and 5a opposed to each other with a dielectric layer 1a interposed between the capacitor units Na ₁ and Nb _2. Formed. Further, as shown in FIG. 3B, each of the internal electrodes 4a, 5
a leads out from different positions only to the other main surface side of the laminate 1 (third lead portion), and the third connection portion of the internal electrode 4a and the external connection electrode formed on the other main surface of the laminate 1 8
a, and to the third lead-out portion of the internal electrode 5a and the external connection electrode 9a formed on the other main surface of the multilayer body 1, respectively. The capacitor unit Nb ₂ also capacitor unit Na ₂ similarly to the internal electrode 4b, 5b are respectively connected to the external connection electrodes 8b, the 9b.

The internal electrodes 2 (2
a, 2b), 3 (3a, 3b) and the internal electrode 4 (4a,
4b) and 5 (5a, 5b) face each other to form a capacitance component.

The capacitor units Na ₁ and Na ₂ are combined to form a capacitor unit group N
a, capacitor unit Nb ₁ and capacitor unit N
The combined b ₂ are the capacitor unit group Nb.

Therefore, the feature of the present invention is, for example, the capacitor unit N of the capacitor unit group Na.
common external connection electrode 8 connected to internal electrodes 2a and 3a of a ₁ and internal electrodes 4a and 5a of capacitor unit Na _2.
a, 9a. Thereby, the capacitor units Na ₁ and Nb ₁ (first capacitor unit)
And the capacity of the capacitor units Na ₂ and Nb ₂ (second capacitor unit) can be obtained at the same time. Moreover,
Since only the external terminal electrodes 6 and 7 of the capacitor units Na ₁ and Nb ₁ (first capacitor unit) are formed on the mounting surface, the external electrodes may interfere with each other on the mounting surface similar to the conventional one. Can be prevented.

However, the external terminal electrodes 8a, 8b, 9 of the capacitor unit group Na and the capacitor unit group Nb formed on the surface facing the mounting surface which is one main surface of the laminate 1
a and 9b are formed so as not to interfere with each other. That is, the leading portions of the internal electrodes 2a, 4a and the internal electrodes 2b, 4
The lead-out portion of b is led out at a position shifted in the direction perpendicular to the laminating direction on that surface, and as a result, the external connection electrodes 9a and 9b to be formed are arranged in a staggered relationship with each other.
The internal electrodes 3a and 5a and the internal electrodes 3b and 5b are also connected to the external connection electrodes 8a and 8b.

The external electrodes 6 (6a, 6b), 7 (7
a, 7b), 8 (8a, 8b), 9 (9a, 9b) contain noble metals such as silver and palladium, or base metals such as nickel and copper, or alloys thereof, and have low melting point materials such as glass. To improve the adhesion strength of the laminate 1 to the ceramics. In particular, the external electrodes 6 and 7 formed on one main surface of the multilayer body 1 are formed by a conventional dipping method or the like, and the external electrodes 8 and 9 formed on the other main surface side of the multilayer body 1 are The conductive paste is applied by a method such as screen printing and baked, or is formed by a conductive film forming method such as an electroless plating method or a sputtering method.

The capacitor unit N includes a first capacitor unit Na ₁ , Nb ₁ and a second capacitor unit Na 1
₂ and Nb ₂ may be alternately stacked in the stacking direction of the dielectric layers 1a to form a capacitor M, thereby forming a capacitor array. Further, the capacitor M may be formed in a direction orthogonal to the stacking direction of the dielectric layers 1a. To form a capacitor array. As a result, it is possible to mount the capacitors more densely with respect to the mounting of the circuit board, and when arranging the capacitors, it is possible to reduce the number of capacitor arrays to be used and to simplify the mounting work on the circuit board.

Next, a method for manufacturing the capacitor array 1 of the present invention will be described. From a slip in which a solvent, a dispersant, a binder, and the like are mixed with a dielectric powder and a sintering aid, a ceramic green sheet to be a dielectric layer 1a is formed by a doctor blade method. For the molding method, another method, a pulling method, a die coater, a gravure roll coater, or the like may be used. The dielectric layer 1a is made of a dielectric material such as barium titanate and strontium titanate.

The internal electrodes 2 to 5 (2a
5b) is printed by a screen printing method. The internal electrodes 2 to 5 (2a to 5b) are made of a noble metal material such as Pd, Ag-Pd alloy or N
A dielectric layer 1 on which a base metal such as i, Cu or the like is used, and thereafter, eight types of internal electrodes 2a to 5a and 2b to 5b are printed
a are laminated in this order, and then thermocompression bonded to obtain a block-shaped capacitor block.

Next, the capacitor block is cut into a laminate 1 including the capacitor unit N by a pushing blade. When the capacitor block is thick, it is desirable to cut by a dicing method. At this time, the lead portions of the internal electrodes 2 to 5 (2a to 5b) in each capacitor unit N are exposed.

Next, the cut laminate 1 is heated at 250 ° C. to 4 ° C.
After preliminarily firing in a furnace at 00 ° C. to remove the binder component, the material is put into a main firing furnace to simultaneously sinter the dielectric ceramic and the internal electrode at an appropriate temperature of the ceramic material at 1250 to 1300 ° C. at a high temperature.

Thereafter, in order to electrically connect each capacitor unit N to the outside, the external electrodes 6 and 7 are provided on one main surface of the sintered body, and the external electrodes 8 and 9 are provided on the upper and lower surfaces of the sintered body. It is formed by a suitable electrode forming method. In this way,
A capacitor array 10 as shown in FIG. 1 is obtained.

The cutting step may be performed in the state of a block or immediately after firing.
By performing the process after the formation of the external connection electrodes 8 and 9, the formation of the external terminal electrodes 6 and 7 and the external connection electrodes 8 and 9 becomes easy, and there is an effect that the characteristics can be measured at one time.

In addition, the inspection of the connection between the external terminal electrodes 6 and 7 and the circuit board at the time of mounting can be confirmed by applying a probe to the external connection electrodes 8 and 9 on the side opposite to the mounting surface. There is also the effect of becoming. This effect is due to the fact that, when the capacitor array 10 is mounted on a circuit board, the connection failure between the terminals of the circuit board and the external terminal electrodes 6 and 7 of the capacitor array 10 becomes remarkable as the size and capacity are increased. However, since the connection failure can be inspected from the opposite side of the mounting surface by the probe, the number of defective products can be reduced.

It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.

[0036]

As described above, according to the structure of the present invention,
Since the external electrodes formed on the other main surface of the laminate are connected to both the internal electrodes in the first capacitor unit and the internal electrodes of the second capacitor unit, the external electrodes can be simply connected to the first lead-out section. Since the capacities of both the first and second capacitor units are generated, a compact and large-capacity capacitor array can be provided by a simple mounting method.

In addition to the capacitance generated between the internal electrodes of the first capacitor unit, the capacitance is generated also between the internal electrodes of the second capacitor unit. Capacity can be realized.

Furthermore, since only a pair of external electrodes connected to the first lead-out portion of the first capacitor unit are formed on only one main surface of the laminate, the mounting surface of the capacitor array is formed on one main surface. In addition, the solder on the board mounting surface allows a sufficient space between the pair of external electrodes, thereby preventing conduction. Therefore, the conventional method of mounting the capacitor array can be used as it is, and the conventional method of manufacturing the multilayer ceramic capacitor element can be used, so that a simple and inexpensive manufacturing method can be realized.

[Brief description of the drawings]

1A and 1B are diagrams illustrating a configuration of a capacitor array according to the present invention, in which FIG. 1A is a diagram illustrating an arrangement relationship of external connection electrodes viewed from the other main surface side of the capacitor array, and FIG.
FIG. 3 is a diagram for explaining the arrangement relationship of external terminal electrodes as viewed from one main surface side, and FIG. 3C is a plan view thereof.

FIGS. 2A and 2B are main part explanatory diagrams for explaining a relationship between an internal electrode connected to an external terminal electrode and an external connection electrode of the capacitor array of the present invention, wherein FIG. ) Relates to the connection between the internal electrode and the external terminal electrode.

FIGS. 3A and 3C are partial cross-sectional views of the capacitor array of the present invention as viewed from the plane. FIGS. 3A and 3C show a first capacitor unit, and FIGS. 3B and 3D show a second capacitor unit. Show.

FIG. 4 is a partial cross-sectional view of the capacitor array of the present invention when cut in a vertical direction.

5A and 5B are diagrams illustrating a configuration of a conventional capacitor array, in which FIG. 5A is an external perspective view of the capacitor array, and FIG.
Is a front view thereof.

FIG. 6 is an explanatory diagram illustrating an arrangement relationship between internal electrodes and external electrodes of a conventional capacitor array.

[Explanation of symbols]

10 Capacitor array 1 Laminated body 1a ... Dielectric layer 2 (2a, 2b) Internal electrode 3 (3a, 3b) Internal electrode 4 (4a, 4b) ... Internal electrode 5 (5a, 5b) ... Internal electrode 6 ... ... External terminal electrode (first external electrode) 7... External terminal electrode (first external electrode) 8. ........................... External connection electrode 9 ........... External connection electrode

Claims (1)

[Claims] 1. A first and a second capacitor unit in which a plurality of internal electrodes having different potentials are opposed to each other across a dielectric layer in a rectangular laminate in which a plurality of dielectric layers are laminated. And a capacitor array in which a plurality of the dielectric layers are arranged in the laminating direction, wherein the internal electrodes of the first capacitor unit are led out from each of them to one main surface side of the multilayer body. And a second lead-out portion leading out to the other main surface side of the laminate, and each internal electrode of the second capacitor unit is led out from each of them to the other main surface side of the laminate. A second lead-out portion having the same potential as the second lead-out portion, and a second lead-out portion having the same potential as the second lead-out portion, on the other main surface of the laminate. And a lead-out part connected in common. I.