JP2001283538A - Data reproducing circuit of recording and reproducing device and its error correcting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data reproducing circuit of a recording and reproducing device which can suppress the power consumption and also securely correct an error even in continuous sector processing. SOLUTION: This circuit is equipped with a demodulating circuit 13 which demodulates the signal reproduced from a recording medium, an error correcting circuit 16 which performs an error correcting process for the data demodulated by the demodulating circuit 13, and a frequency dividing circuit 20 which divides a reference clock based upon the signal reproduced from the recording medium into a clock allowing the error correcting circuit 16 to complete the error correction in the passage time of one sector of the recording medium; and the error correcting circuit 16 performs the error correcting process with the clock having its frequency divided by the frequency dividing circuit 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing circuit of a recording / reproducing apparatus for recording and reproducing data on a disk-shaped recording medium such as an optical disk or a magnetic disk, and an error correction method thereof. The present invention relates to ensuring operation of a correction circuit and reducing power consumption.

[0002]

2. Description of the Related Art Conventionally, a magneto-optical disk used in a magneto-optical disk drive, which is a recording / reproducing apparatus, for example, forms a track by spirally cutting a groove, and a recording sector is arranged along the track with an ID area at the head. When the magneto-optical disk is formed and inserted into the recording / reproducing apparatus, the disk is fixed to the spindle motor and rotated at a rotation speed of, for example, about 3600 rpm, and a light spot is formed along a track on the rotating optical disk. Reproduction is performed by reading the light spot with a pickup.

FIG. 8 shows a data reproduction circuit which processes a reproduction signal read by a pickup and outputs the data as reproduction data. FIG. 8 is a diagram showing a configuration of a data reproducing circuit of a conventional recording / reproducing apparatus. In the figure, 11 is a pickup, 12 is an analog signal processing circuit, 13 is a demodulation circuit, 14 is a buffer, 15 is a data transfer control circuit, 16 is an error correction circuit, 17 is a reproduction signal from the pickup 11, 18 is a data clock, 19
Is demodulated data demodulated by the demodulation circuit 13.

Next, the operation of the conventional data reproducing circuit will be described. First, the reproduction signal 1 from the pickup 11
7 is transmitted to the analog signal processing circuit 12, and the analog signal processing circuit 12 amplifies the reproduced signal 17 to an appropriate amplitude, removes noise components by a filter, shapes the waveform, and forms a data window from the waveform-shaped signal. The data is discriminated by this window, output, and input to the demodulation circuit 13.

In the magneto-optical disk, (1, 7)
Since the modulation method of the RLL modulation code or the (2,7) RLL modulation code is used, the demodulation circuit 13 performs demodulation based on these modulation methods, and the demodulated demodulated data 19 is temporarily stored in the buffer 14. At the same time, it is input to the error correction circuit 16. Magneto-optical disk data includes
An error correction code (Reed-Solomon code) based on a Reed-Solomon code is added for each sector. The error correction circuit 16 detects data errors based on this code and corrects the data in the buffer 14. . Then, the error-corrected data in the buffer 14 is output to the outside via the data transfer control circuit 15.

In the conventional data reproducing circuit, the demodulation circuit 13 and the error correction circuit 16 operate in accordance with the transfer speed of data read from the magneto-optical disk. 18 is supplied to the demodulation circuit 13 and the error correction circuit 16, and the data clock causes the demodulation circuit 13 and the error correction circuit 16 to operate.

[0007]

However, in the conventional data reproducing circuit as described above, the data clock 18
Frequency depends on the data transfer rate, which is the main performance index of the magneto-optical disk,
It is set as high as possible. For example, ISO
For a standard 3.5-inch 540 MB disk, if the disk rotation speed is 4500 rpm, the data clock is 59
Mhz, and the error correction circuit 16 also operates with this data clock.

The error correction circuit 16 is a large-scale circuit for performing a complicated correction operation, and there is a problem that the power consumption increases when operated with such a high-speed clock. In order to suppress power consumption, it is conceivable to operate the error correction circuit 16 with a low clock. However, if the clock is simply lowered, there is a possibility that the error correction processing cannot be performed in time for processing of a continuous sector. There was a point.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is possible to reduce power consumption and to perform data reproduction of a recording / reproducing apparatus capable of reliably performing error correction even in continuous sector processing. It is intended to provide a circuit.

[0010]

A data reproducing circuit of a recording / reproducing apparatus according to the present invention comprises a data reproducing circuit for recording / reproducing data on / from a recording medium. A demodulation circuit for demodulating the data; and an error correction circuit for performing an error correction process on the demodulated data demodulated by the demodulation circuit. An error correction process is performed. Further, the data reproducing circuit of the recording / reproducing apparatus according to the present invention is a data reproducing circuit for recording / reproducing data on / from a recording medium, wherein the data reproducing circuit demodulates a signal reproduced from the recording medium; An error correction circuit that performs error correction processing on demodulated data demodulated by the circuit, and a reference clock based on a signal reproduced from a recording medium,
An error correction circuit that includes a frequency divider that divides the clock into a clock that completes error correction with a passage time of one sector of the recording medium; and the error correction circuit performs error correction using the clock divided by the frequency divider. Things.

Further, the frequency dividing circuit of the data reproducing circuit of the recording / reproducing apparatus according to the present invention changes the frequency dividing ratio based on the method of modulating the data on the recording medium. Also,
A frequency dividing circuit of a data reproducing circuit of a recording / reproducing apparatus according to the present invention varies a frequency dividing ratio based on a method of modulating data on a recording medium such that clocks after frequency division are the same. . Further, in the frequency dividing circuit of the data reproducing circuit of the recording / reproducing apparatus according to the present invention, when the modulation method of the data on the recording medium is (1, 7) RLL modulation, the frequency dividing ratio is set to divide by 3,
When the modulation method of the data on the recording medium is (2, 7) RLL modulation, the frequency division ratio is set to 4 frequency division.

A data reproducing circuit of a recording / reproducing apparatus according to the present invention is a data reproducing circuit in a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, wherein the demodulating circuit demodulates a signal reproduced from the recording medium. An error correction circuit that performs error correction processing on demodulated data demodulated by the demodulation circuit; a frequency division circuit that divides a reference clock based on a signal reproduced from a recording medium; and error correction performed by the error correction circuit. Monitoring means for monitoring the processing status and varying the frequency division ratio of the frequency dividing circuit based on the monitoring result, wherein the error correction circuit performs error correction processing with the clock divided by the frequency dividing circuit It is. Further, the monitoring means of the data reproducing circuit of the recording / reproducing apparatus according to the present invention increases the frequency division ratio of the frequency dividing circuit when the number of error correction processes is small as a result of monitoring the correction processing status, and If the number is large, the frequency division ratio of the frequency dividing circuit is reduced.

A data reproducing circuit of a recording / reproducing apparatus according to the present invention is a data reproducing circuit for recording / reproducing data on / from a recording medium, wherein the data reproducing circuit demodulates a signal reproduced from the recording medium. A first error correction circuit for performing a small number of error correction processes on the demodulated data demodulated by the demodulation circuit, and a second error correction process for performing a large number of error correction processes on the demodulated data demodulated by the demodulation circuit.
An error correction circuit, a frequency dividing circuit for dividing a reference clock based on a signal reproduced from a recording medium, and monitoring the error correction processing status by the first error correction circuit or the second error correction circuit. Monitoring means for varying the frequency division ratio of the frequency dividing circuit based on the monitoring result, wherein the first error correction circuit and the second error correction circuit perform error correction processing on the clock divided by the frequency dividing circuit. Is what you do. The monitoring means of the data reproducing circuit of the recording / reproducing apparatus according to the present invention, as a result of monitoring the error correction processing status, increases the frequency division ratio of the frequency dividing circuit when the number of error correction processing is small, and If the number is large, the frequency dividing ratio of the frequency dividing circuit is reduced.

The monitoring means of the data reproducing circuit of the recording / reproducing apparatus according to the present invention increases the frequency division ratio of the frequency dividing circuit when the number of error correction processing is small as a result of monitoring the error correction processing status. An error correction process is performed by a first error correction circuit. If the number of error correction processes is large, the frequency division ratio of the frequency divider circuit is reduced, and an error correction process is performed by the second error correction circuit. . Further, the monitoring means of the data reproducing circuit of the recording / reproducing apparatus according to the present invention accumulates the history of the number of errors during the previous reproducing operation and sets the frequency division ratio of the frequency dividing circuit based on the accumulated result. Things. Further, the monitoring means of the data reproducing circuit of the recording / reproducing apparatus according to the present invention calculates the number of errors based on the error correction polynomial and the error position polynomial used in the error correction processing, and based on the calculation result, the frequency dividing circuit Is set.

Further, the error correction method for a recording / reproducing apparatus according to the present invention is an error correction method for a recording / reproducing apparatus for recording / reproducing data on / from a recording medium. When the error correction process is performed, the error correction process is performed using a clock in which the error correction is completed in a passage time of one sector of the recording medium. Further, the error correction method for a recording / reproducing apparatus according to the present invention is an error correction method for a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, wherein the error correction is performed on demodulated data of a signal reproduced from the recording medium. When performing the processing, the error correction processing status is monitored, the clock is varied based on the monitoring result, and the error correction processing is performed using the clock. Further, the error correction method for a recording / reproducing apparatus according to the present invention is an error correction method for a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, wherein the error correction is performed on demodulated data of a signal reproduced from the recording medium. When performing the processing, the error correction processing status is monitored, the clock is varied based on the monitoring result, the error correction processing is performed with the clock, and the first error correction processing for performing a small number of error correction processing or a large number of error correction processing is performed. The error correction process is performed by switching the second error correction process for performing the error correction process.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing a configuration of a data reproducing circuit of a recording / reproducing apparatus according to one embodiment of the present invention. In the figure, 11 is a pickup, 12 is an analog signal processing circuit, 13 is a demodulation circuit,
14 is a buffer, 15 is a data transfer control circuit, 16 is an error correction circuit, 17 is a reproduced signal from the pickup 11,
Reference numeral 18 denotes a data clock, 19 denotes demodulated data demodulated by the demodulation circuit 13, 20 denotes a frequency dividing circuit for dividing the data clock 18 output from the analog signal processing circuit 12, 21
Is a clock divided by the frequency dividing circuit 20.

Next, the operation of the data reproducing circuit of this embodiment will be described. First, a reproduction signal 17 from the pickup 11 is transmitted to the analog signal processing circuit 12,
In the analog signal processing circuit 12, the reproduced signal 17 is amplified to an appropriate amplitude, a noise component is removed by a filter, the waveform is shaped, and a data window is created from the waveform-shaped signal, and data is determined based on the window. And output to the demodulation circuit 13.

Here, the modulation method used in the demodulation circuit 13 will be described. For magneto-optical disks,
A (1,7) RLL modulation code or a (2,7) RLL modulation code modulation method is used. For example, a 3.5-inch disk has a (2,7) RLL modulation code for a 128 MB or 230 MB disk. The used modulation is used, and the modulation using the (1,7) RLL modulation code is used for the 540 MB, 640 MB, and 1.3 GB discs.

The (1,7) RLL modulation code is converted into a recording signal of 12 bits per 1-byte data by the conversion as shown in FIG. 2A in the modulation at the time of recording on the magneto-optical disk. In demodulation at the time of reproduction from a magneto-optical disk, 1-byte data is output from a 12-bit signal by the conversion shown in FIG. Also, (2,
7) In the modulation at the time of recording on the magneto-optical disk, the RLL modulation code is converted into a 16-bit recording signal per 1-byte data by the conversion as shown in FIG. In demodulation during reproduction, 1-byte data is output from a 16-bit signal by conversion as shown in FIG. FIG. 4 shows an example of original data and modulated data modulated by each of these modulation methods. As shown in FIG. 4, as the data clock, one cycle is generated for one bit of the recording signal.

The demodulation circuit 13 recognizes the modulation method used, performs demodulation based on the recognized modulation method, and temporarily stores the demodulated demodulated data 19 in the buffer 14 and performs error correction. Input to the circuit 16. An error correction code (Reed-Solomon code) using a Reed-Solomon code is added to the data on the magneto-optical disk in sector units. The error correction circuit 16 detects an error in the data based on this code, and Error correction is performed on the data. And the buffer 14
The error-corrected data in is output to the outside via the data transfer control circuit 15.

Here, the error correction using the Reed-Solomon code will be described. FIG. 5 is an explanatory diagram for explaining the format of the error correction code, and shows data of one sector stored in the buffer 14. In the following description, an example in which 512 bytes of user data are recorded per sector as a disc standard as shown in FIG. 5 is used. The correction method is the same.

As shown in FIG. 5, the user data recorded in the data field is represented by numbers D1 to D512 from the beginning, and the user data with additional data such as CRC added to the five data Each is divided into 5 interleaves. For example, the user data forming the first interleave is D1, D6,.
11, FF. Then, 16 bytes of redundant bytes are added to each of the interleaved segments. For example, for the first interleave,
The added redundant bytes are E11 to E161. The data field data is 600 bytes for all user data, CRC, redundant data and undefined data.

The Reed-Solomon code is a correction code in units of symbols. In many cases, data in units of bytes is used as a symbol. In the Reed-Solomon code, each element of a code word is treated as an element of a Galois field. Performs a correction operation. The redundant byte regards the user data as a coefficient of a polynomial, and records the remainder of the polynomial obtained by dividing the polynomial by a code generation polynomial as a redundant byte. At the time of playback, user data, added data,
The redundant bytes are regarded as polynomial coefficients, and the remainder after division by the same generator polynomial as at the time of recording is obtained.

If the coefficients of the remaining polynomials are all zero, no error has occurred, so there is no need to perform error correction. If any of the coefficients is not zero, error correction is performed according to the following procedure. The error correction procedure consists of three steps. The first procedure is to convert the remainder data into a syndrome, the second procedure is to find an error position polynomial and an error numerical polynomial from the syndrome, and the third procedure Is to determine the position and numerical value of the error from the error locator polynomial and the error numerical polynomial.

If one symbol is one byte, the error position is from 0 to 255. Therefore, a code cannot be assigned to a data set of 256 bytes or more.
As shown in FIG. 5, a data set is divided into 256 bytes or less by dividing data by interleaving. Therefore, error correction is performed on an interleave basis.

Next, the number of steps required for the error correction operation will be described. First, in the first procedure, since the primary conversion is performed on 16-byte division data, the calculation step can be performed by 16 product-sum operations. Typical arithmetic algorithms for performing the second procedure include the Euclidean algorithm and the Berlekamp algorithm. For example, if the Euclidean algorithm is used, the division of a polynomial of degree 16 or less is performed about eight times. Therefore, about 128 calculation steps are required. The number of operations is the maximum. If the number of errors is small, a result can be obtained with a smaller number of steps.

In the following third procedure, a Chien search is often used as a method for obtaining an error position and a numerical value from an error locator polynomial and an error numerical polynomial. This is a method of sequentially checking the above-mentioned error locator polynomial for all of them. In this embodiment, the number of data per interleave is 120 including redundant bytes, so the number of operation steps is 120. Assuming that there are 16 calculation steps and other calculation steps, the error correction calculation step is 280 steps per interleave, and the calculation step of one entire sector is 5 times 280, which is 1400 steps. The number of steps is the number of steps at which error correction operation can be completely performed on data of one sector.

By the way, the read operation for the disk is performed so as to continuously read a plurality of sectors arranged continuously. At this time, the error correction time given to one sector passes through one sector. Time.
Therefore, if the error correction process is slower than this time, all the data stored in the buffer 14 can be corrected and output from the buffer 14 to the data transfer control circuit 15, so that the data is stored in the buffer 14. The inconvenience of doing so occurs.

That is, the above-described 1400-step error correction operation must be completed within one sector time.
When this is converted into one byte of the data field, 1
In 400/600, it is necessary to perform 2.3 steps per byte. The clock for operating the error correction circuit 16 that performs the error correction operation is a clock generated by the analog signal processing circuit 12 and having a frequency proportional to the data transfer speed from the magneto-optical disk and divided by the frequency dividing circuit 20. Has become.

Actually, the clock 18 output from the analog signal processing circuit 12 differs depending on the modulation method. As shown in FIG. 4, in the (1, 7) RLL modulation method used in the ISO standard magneto-optical disk, the clock 18 is not changed. A clock of 12 cycles is generated per byte data, and a clock of 16 cycles is generated per byte data in the (2,7) RLL modulation method used in the ISO standard magneto-optical disk.

Here, since one operation step can be performed in one clock, in order to perform the operation of 2.3 steps per byte, in the case of the (1,7) RLL modulation method, the frequency is divided by 5 or less. The clock 21 divided by the frequency division ratio of (2) may be supplied to the error correction circuit 16, and (2,7) R
In the case of the LL modulation method, the clock 21 divided at a division ratio of 6 or less may be supplied to the error correction circuit 16.

In this embodiment, the output from the analog signal processing circuit 12 is set so that the operation clock of the error correction circuit 16 is the same in both the (1, 7) RLL modulation method and the (2, 7) RLL modulation method. The clock 18 is divided by 3 by the (1, 7) RLL modulation method and divided by 4 by the (2, 7) RLL modulation method by the frequency dividing circuit 20, and is used as the operation clock 21 of the error correction circuit 16, The clock 21 for error correction has four cycles per byte. As a result, the error correction circuit 16 operates with a clock of 2.3 steps or more per byte, which can perform error correction of all data in the data field in the time required to pass one sector. Since the error correction processing is completed before the operation is completed, and the operation is performed with the minimum required clock, the power consumption of the error correction circuit 16 is low.

Next, the variation of the frequency division ratio in the frequency dividing circuit 20 will be described. The frequency dividing circuit 20 recognizes a modulation method such as the (1, 7) RLL modulation method and the (2, 7) RLL modulation method, and varies the frequency division ratio. The data recognized by the demodulation circuit 13 or a control unit that controls the entire magneto-optical disk drive by a method of sequentially switching the modulation method or a method of switching the clock to read out the data is transmitted to the frequency dividing circuit 20. The modulation method is recognized based on the input data.

As described above, in this embodiment, the frequency dividing circuit 20 sets the optimum frequency dividing ratio according to the modulation method of the magneto-optical disk to be reproduced, and uses the clock divided by the frequency dividing ratio to generate the error correction circuit. 16 is operated to perform the error correction operation, so that even if the modulation method changes, the error correction operation is performed using the clock divided by the optimum division ratio in the modulation method, and the continuous sector Even in the processing of (1), error correction can be surely completed within the transit time within one sector, and power consumption in the error correction circuit 16 can be suppressed as much as possible.

Embodiment 2 FIG. 6 is a block diagram showing a configuration of a data reproducing circuit of a recording / reproducing apparatus according to another embodiment of the present invention. In the figure, 11 is a pickup,
12 is an analog signal processing circuit, 13 is a demodulation circuit, 14 is a buffer, 15 is a data transfer control circuit, 16 is an error correction circuit, 17 is a reproduced signal from the pickup 11, 18 is a data clock, and 19 is a demodulation circuit 13. Demodulated data, 20 is a frequency dividing circuit for dividing the data clock 18 output from the analog signal processing circuit 12, 21 is a clock divided by the frequency dividing circuit 20, and 22 is an error correction circuit 1.
6 is monitoring means for monitoring the processing status of the error correction in 6.

Next, the operation of the data reproducing circuit of this embodiment will be described. First, a reproduction signal 17 from the pickup 11 is transmitted to the analog signal processing circuit 12,
In the analog signal processing circuit 12, the reproduced signal 17 is amplified to an appropriate amplitude, a noise component is removed by a filter, the waveform is shaped, and a data window is created from the waveform-shaped signal, and data is determined based on the window. And output to the demodulation circuit 13.

In the demodulation circuit 13, the first embodiment
Similarly to the above, the used modulation method is recognized, demodulation is performed based on the recognized modulation method, and the demodulated demodulated data 19 is temporarily stored in the buffer 14 and input to the error correction circuit 16. . An error correction code (Reed-Solomon code) based on a Reed-Solomon code is added to the data on the magneto-optical disk in sector units. The error correction circuit 16 detects a data error based on this code and outputs the data to the buffer 14. Error correction is performed on the data of. Then, the error-corrected data in the buffer 14 is output to the outside via the data transfer control circuit 15.

Next, the operation of the frequency dividing circuit 20 and the monitoring means 22 of this embodiment will be described. First, in the initial state, the frequency dividing circuit 20 recognizes a modulation method such as the (1, 7) RLL modulation method or the (2, 7) RLL modulation method, and varies the frequency division ratio. The recognition is performed by, for example, a method of sequentially switching the modulation method or a method of switching between clocks and reading by a control unit that controls the entire demodulation circuit 13 and the magneto-optical disk drive. Is input to the frequency dividing circuit 20, and the modulation method is recognized based on the input data. Then, in the initial state, the frequency divider 20 divides the clock 18 output from the analog signal processing circuit 12 into three by the (1, 7) RLL modulation method, as in the first embodiment, and (2, 7) In the RLL modulation method, the frequency is divided by four and the operation clock 21 of the error correction circuit 16 is used, and the division ratio in the initial state operates at the minimum division ratio.

The monitoring means 22 performs the error correction processing in the error correction circuit 16 (for example, the error number polynomial obtained by the Euclidean mutual division method and the error number polynomial obtained from the error position polynomial in the second error correction means 24). ) Is monitored, and if the number of error corrections performed is small, the frequency division ratio in the frequency divider 20 is increased and the operation clock 21 of the error correction circuit 16 is reduced. Conversely, if the number of error corrections performed is large, the frequency division ratio in the frequency dividing circuit 20 is set to the frequency division ratio in the initial state.

As described above, in this embodiment, when the reproduced data has few errors and the error can be corrected even if the error correction processing in the error correction circuit 16 is small, the frequency dividing circuit 2
Increase the frequency division ratio at 0 and operate with the minimum clock,
When the power consumption in the error correction circuit 16 is minimized and the reproduced data has a large number of errors, the frequency division ratio in the frequency division circuit 20 is such that the error correction processing in the second error correction means 24 requires one sector. Since the operation is performed with the minimum clock capable of performing error correction for all data in the data field during the passing time, error correction can be surely completed within the passing time within one sector even in the processing of continuous sectors. In addition, the power consumption of the error correction circuit 16 can be suppressed as much as possible, and when the number of error corrections is small, the power consumption can be further suppressed.

Embodiment 3 FIG. 7 is a block diagram showing a configuration of a data reproducing circuit of a recording / reproducing apparatus according to another embodiment of the present invention. In the figure, 11 is a pickup,
Reference numeral 12 denotes an analog signal processing circuit, reference numeral 13 denotes a demodulation circuit, reference numeral 14 denotes a buffer, reference numeral 15 denotes a data transfer control circuit, reference numeral 16 denotes an error correction circuit, and a first error correction means 23 for correcting a small number of errors; The second error correcting means 24 corrects the error. The first of the error correction circuit 16
The processing by the error correcting means 23 is, for example, capable of processing a high-speed correction of a small number of errors using the Peterson method in the algorithm. The processing by the second error correcting means 24 is the same as that of the first embodiment. The same error correction as that of the error correction operation of the error correction circuit 16 is performed.

Reference numeral 17 denotes a reproduced signal from the pickup 11,
Reference numeral 18 denotes a data clock, 19 denotes demodulated data demodulated by the demodulation circuit 13, 20 denotes a frequency dividing circuit for dividing the data clock 18 output from the analog signal processing circuit 12, 21
Reference numeral 22 denotes a clock frequency-divided by the frequency dividing circuit, and reference numeral 22 denotes monitoring means for monitoring the processing status of error correction in the error correction circuit 16.

Next, the operation of the data reproducing circuit of this embodiment will be described. First, a reproduction signal 17 from the pickup 11 is transmitted to the analog signal processing circuit 12,
In the analog signal processing circuit 12, the reproduced signal 17 is amplified to an appropriate amplitude, a noise component is removed by a filter, the waveform is shaped, and a data window is created from the waveform-shaped signal, and data is determined based on the window. And output to the demodulation circuit 13.

In the demodulation circuit 13, the first embodiment
Similarly to the above, the used modulation method is recognized, demodulation is performed based on the recognized modulation method, and the demodulated demodulated data 19 is temporarily stored in the buffer 14 and input to the error correction circuit 16. . An error correction code (Reed-Solomon code) based on a Reed-Solomon code is added to the data on the magneto-optical disk in sector units. The error correction circuit 16 uses the first error correction means 23 or the second error correction code based on this code. The error of the data is detected and error correction is performed on the data in the buffer 14 using one of the two error correction means 24. Then, the error-corrected data in the buffer 14 is output to the outside via the data transfer control circuit 15.

Next, the operation of the frequency dividing circuit 20 and the monitoring means 22 of this embodiment will be described. First, in the initial state, the frequency dividing circuit 20 recognizes a modulation method such as the (1, 7) RLL modulation method or the (2, 7) RLL modulation method, and varies the frequency division ratio. The recognition is performed by, for example, a method of sequentially switching the modulation method or a method of switching between clocks and reading by a control unit that controls the entire demodulation circuit 13 and the magneto-optical disk drive. Is input to the frequency dividing circuit 20, and the modulation method is recognized based on the input data. Then, in the initial state, the frequency divider 20 divides the clock 18 output from the analog signal processing circuit 12 into three by the (1, 7) RLL modulation method, as in the first embodiment, and (2, 7) In the RLL modulation method, the frequency is divided by four and the operation clock 21 of the error correction circuit 16 is used, and the division ratio in the initial state operates at the minimum division ratio.

Then, the monitoring means 22 performs the error correction processing in the error correction circuit 16 (for example, the error number polynomial obtained by the Euclidean mutual division method and the error number polynomial obtained from the error position polynomial in the second error correction means 24). , Etc.), and if the number of error corrections performed is small, an instruction is given to perform the error correction processing in the error correction circuit 16 using the first error correction means 23, and The operation clock 21 of the error correction circuit 16 is decreased by increasing the frequency division ratio. Conversely, if the number of error corrections performed is large, it is instructed that the error correction processing in the error correction circuit 16 is performed using the second error correction means 24, and the division in the frequency dividing circuit 20 is performed. The circumference ratio is set to the division ratio in the initial state.

As described above, in this embodiment, when the number of errors in the reproduced data is small, the first error correction means 23 capable of processing the correction of the small number of errors at high speed performs the error correction processing. Since the processing is completed with a small number of steps in the first correction means 23, the frequency division ratio in the frequency divider circuit 20 is increased to operate with the minimum clock, and the power consumption in the error correction circuit 16 is minimized. When the reproduced data has many errors, the error correction processing of the second error correction means 24, which can correct even the largest error, is performed.
Further, the frequency division ratio in the frequency dividing circuit 20 is determined by the minimum clock capable of performing the error correction of all data in the data field in the time when the error correction processing in the second error correction means 24 passes one sector. Since the operation is performed, error correction can be reliably completed within the transit time within one sector even in processing of consecutive sectors, and power consumption in the error correction circuit 16 can be suppressed as much as possible. When the number is small, it is possible to further reduce the power consumption.

In the first, second, and third embodiments, an example of a magneto-optical disk has been described. However, the present invention may be applied to a data generation circuit of another disk. In the first, second, and third embodiments, the (1, 7) RLL modulation method divides the frequency by 3 and (2, 3)
7) In the RLL modulation method, the frequency division is performed by four. However, in each modulation method, the frequency division ratio may be set so as to be the minimum clock. In the first, second, and third embodiments, the (1,7) and (2,7) RLL modulation schemes have been described, but the modulation scheme is not limited to these. An appropriate frequency division ratio may be set by the method described above.

[0049]

As described above, according to the present invention, the frequency divider circuit corrects the reference clock based on the signal reproduced from the recording medium, and the error correction circuit corrects the error with the passing time of one sector of the recording medium. The frequency is divided into clocks to be completed, and the error correction circuit performs the error correction processing using the clock divided by the frequency divider circuit. Therefore, even in the processing of continuous sectors, the error correction is performed reliably in the transit time within one sector. And the power consumption in the error correction circuit can be suppressed as much as possible.

The monitoring means monitors the status of the error correction processing by the error correction circuit, and changes the frequency division ratio of the frequency division circuit based on the monitoring result. Since the error correction process is performed with the clock that has been set, the error correction can be reliably completed within the passing time within one sector even in the processing of continuous sectors.
In addition, the power consumption in the error correction circuit 16 can be suppressed as much as possible, and when the number of error corrections is small, the power consumption can be further suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data reproducing circuit of a recording / reproducing apparatus according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining a (1, 7) RLL modulation code.

FIG. 3 is an explanatory diagram for explaining a (2, 7) RLL modulation code.

FIG. 4 is a timing chart showing original data and modulated data modulated by each modulation method.

FIG. 5 is an explanatory diagram for explaining a format of an error correction code.

FIG. 6 is a block diagram showing a configuration of a data reproducing circuit of a recording / reproducing apparatus according to another embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a data reproducing circuit of a recording / reproducing apparatus according to another embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a data reproducing circuit of a conventional recording / reproducing apparatus.

[Explanation of symbols]

 Reference Signs List 11 pickup 12 analog signal processing circuit 13 demodulation circuit 14 buffer 15 data transfer control circuit 16 error correction circuit 17 reproduced signal from pickup 11 data clock 19 demodulated data demodulated by demodulation circuit 13 20 frequency dividing circuit 21 frequency dividing circuit 20 Is a clock divided by. 22 monitoring means 23 first error correction means 24 second error correction means

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 20/18 572 G11B 20/18 572F G06F 11/10 330 G06F 11/10 330L G11B 20/14 341 G11B 20 / 14 341A 351 351A

Claims (15)

[Claims] 1. A data reproducing circuit in a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, comprising: a demodulation circuit for demodulating a signal reproduced from the recording medium; An error correction circuit for performing an error correction process on the recording medium, wherein the error correction circuit performs the error correction process with a clock that completes the error correction in a passage time of one sector of the recording medium. Data reproduction circuit. 2. A data reproducing circuit in a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, comprising: a demodulation circuit for demodulating a signal reproduced from the recording medium; An error correction circuit that performs an error correction process on the recording medium; and a reference clock based on a signal reproduced from the recording medium is divided into a clock in which the error correction circuit completes error correction in one pass of the sector of the recording medium. A data dividing circuit, comprising: a frequency dividing circuit for dividing the data; wherein the error correcting circuit performs an error correcting process using the clock divided by the frequency dividing circuit. 3. The data reproducing circuit according to claim 2, wherein the frequency dividing circuit changes a frequency dividing ratio based on a method of modulating data on the recording medium. 4. The frequency dividing circuit according to claim 2, wherein the frequency dividing circuit varies a frequency dividing ratio based on a method of modulating data on the recording medium so that a frequency-divided clock becomes the same. A data reproducing circuit of the recording / reproducing apparatus according to Claim 1. 5. The frequency dividing circuit according to claim 1, wherein a modulating method of data on the recording medium is (1,7) RLL modulation, a dividing ratio is set to divide by 3, and a modulating method of data on the recording medium is ,
3. The data reproducing circuit of a recording / reproducing apparatus according to claim 2, wherein the frequency division ratio is set to divide-by-4 in (2,7) RLL modulation. 6. A data reproducing circuit in a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, comprising: a demodulation circuit for demodulating a signal reproduced from the recording medium; An error correction circuit that performs an error correction process on the signal; a frequency divider circuit that divides a reference clock based on a signal reproduced from the recording medium; and a monitoring result of the error correction processing performed by the error correction circuit. Monitoring means for varying the frequency division ratio of the frequency division circuit based on the above, wherein the error correction circuit performs an error correction process using a clock divided by the frequency division circuit. Data recovery circuit of the device. 7. The monitoring means increases the frequency division ratio of the frequency dividing circuit when the number of error correction processes is small as a result of monitoring the status of the correction processing, and increases the frequency dividing circuit when the number of error correction processes is large. 7. The data reproducing circuit according to claim 6, wherein the frequency dividing ratio is reduced. 8. A data reproducing circuit in a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, comprising: a demodulation circuit for demodulating a signal reproduced from the recording medium; A first error correction circuit that performs a small number of error correction processes on the other hand, a second error correction circuit that performs a large number of error correction processes on the demodulated data demodulated by the demodulation circuit, A frequency dividing circuit that divides a reference clock based on the received signal, and monitors the error correction processing status of the first error correction circuit or the second error correction circuit, and based on the monitoring result,
Monitoring means for varying a frequency division ratio of the frequency dividing circuit, wherein the first error correction circuit and the second error correction circuit perform an error correction process using a clock divided by the frequency dividing circuit. A data reproducing circuit of a recording / reproducing apparatus, characterized by: 9. The monitoring means increases the frequency division ratio of the frequency dividing circuit when the number of error correction processes is small as a result of monitoring the error correction processing status, and increases the frequency division ratio when the number of error correction processes is large. 9. The data reproducing circuit of a recording / reproducing apparatus according to claim 8, wherein the frequency division ratio of the circuit is reduced. 10. When the number of error correction processes is small as a result of monitoring the error correction processing status, the monitoring means increases the frequency division ratio of the frequency divider circuit and corrects the error by the first error correction circuit. When the number of error correction processes is large, the frequency division ratio of the frequency dividing circuit is reduced, and
9. The data reproducing circuit according to claim 8, wherein the second error correcting circuit performs an error correcting process. 11. The apparatus according to claim 11, wherein the monitoring means accumulates a history of the number of errors during a previous reproducing operation, and sets a frequency division ratio of the frequency dividing circuit based on the accumulated result. 11. The data reproducing circuit of the recording / reproducing device according to any one of 6 to 10. 12. The monitoring means calculates the number of errors based on an error correction polynomial and an error locator polynomial used in an error correction process, and sets a frequency division ratio of the frequency dividing circuit based on the calculation result. The data reproducing circuit of the recording / reproducing apparatus according to any one of claims 6 to 10, wherein: 13. An error correction method in a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, wherein when performing error correction processing on demodulated data of a signal reproduced from the recording medium, An error correction method for a recording / reproducing apparatus, wherein the error correction processing is performed with a clock in which error correction is completed in a passage time of one sector. 14. An error correction method in a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, wherein the error correction processing is performed when demodulating data of a signal reproduced from the recording medium. An error correction method for a recording / reproducing apparatus, characterized in that a situation is monitored, a clock is varied based on the monitoring result, and the error correction processing is performed with the clock. 15. An error correction method in a recording / reproducing apparatus for recording / reproducing data on / from a recording medium, wherein the error correction processing is performed when demodulating data of a signal reproduced from the recording medium. The status is monitored, the clock is varied based on the monitoring result, and the error correction process is performed with the clock, and the first error correction process for performing a small number of error correction processes or the second error correction process for performing a large number of error correction processes is performed. An error correction method for a recording / reproducing apparatus, wherein the error correction processing is performed by switching the error correction processing.