JP2001282197A - Driving circuit and liquid crystal display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the electric state of a source driver. SOLUTION: The driving circuit of a matrix type liquid crystal display device is the one provided with counter electrodes, a counter electrode driving circuit for applying counter electrode driving signals to them, plural signal electrodes, and a signal electrode driving circuit for applying video signals to them. The signal electrode driving circuit comprises plural output circuits 100 corresponding to plural signal electrodes respectively. Each output circuit is configured so as to apply a video signal to the corresponding signal electrode via a 1st switching circuit 18. The 1st switching circuit is turned off for a 1st period, and the timing when the counter electrode driving signal is inverted in polarity is not included in the 1st period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driving circuit for a matrix type liquid crystal display device and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art FIG. 3 schematically shows a structure of a matrix type liquid crystal display device. This liquid crystal display device includes a matrix type liquid crystal display panel 1 and driving circuits (7, 8) for driving the same. FIG. 3 shows an equivalent circuit schematically showing an electric configuration of the matrix type liquid crystal display panel 1.

The matrix type liquid crystal display panel 1 has a plurality of picture elements 2 arranged in a matrix of n rows and m columns.
In FIG. 3, one horizontal scanning line is formed by a plurality of picture elements 2 for one row arranged in the horizontal direction. Therefore, the matrix type liquid crystal display panel 1 has n horizontal scanning lines. Although the picture element 2 is represented as a capacitor in the drawing, in actuality, the picture element electrode 4, a counter electrode 5 that is arranged to face the picture element electrode 4 at a predetermined interval, and a picture element electrode 4. And a liquid crystal layer 6 interposed between the liquid crystal layer 6 and the counter electrode 5. The pixel electrodes 4 are substantially rectangular electrodes and are arranged in a matrix of n rows and m columns. The counter electrode 5 has n
This is realized by one electrode provided commonly to all of the x m pixel electrodes 4. By changing the optical characteristics (such as transmittance) of the liquid crystal layer 6 due to the potential difference between the picture element electrode 4 and the counter electrode 5, for example, ON (light transmission) / OFF (light blocking)
Display is performed.

In the vicinity of the picture element 2, a plurality of switching elements (TFT, Thin Film Tran) for driving the picture element 2 are provided.
A sistor (thin film transistor) 3 is provided corresponding to each of the plurality of picture elements 2. The picture element electrode 4 of the picture element 2 is connected to the drain of the switching element 3. Note that a MOS (Metal Oxide Semiconductor) is used as the switching element 3.
or a metal oxide semiconductor) transistor.

[0005] The matrix type liquid crystal display panel 1 includes n scanning electrodes G1 to Gn (the reference numeral G is used when collectively referred to). Scan electrode G
Are arranged corresponding to each horizontal scanning line. j (j = 1 to
The gates of the plurality of TFTs 3 corresponding to the plurality of picture elements 2 forming the j-th horizontal scanning line are connected to the (n) th scanning electrode Gj. Further, the matrix type liquid crystal display panel 1 includes m signal electrodes S1 to Sm (referred to as a reference symbol S when collectively referred to) arranged in parallel with each other so as to be orthogonal to the scanning electrodes G. The signal electrode S is shown in FIG.
Are arranged corresponding to each picture element row arranged in the vertical direction on the paper surface of FIG. A plurality of TFs corresponding to the plurality of picture elements 2 forming the i-th picture element row are provided on the i-th (i = 1 to m) signal electrode Si.
Each source of T3 is connected.

The matrix type liquid crystal display panel 1 is driven by a drive circuit including a gate driver 7 and a source driver 8. The gate driver 7 is connected to the scanning electrode G of the matrix type liquid crystal display panel 1, and the source driver 8 is connected to the signal electrode S of the matrix type liquid crystal display panel 1.
Connected to. As shown in FIG. 4, the video signal V is supplied to the control circuit 50 by the interface circuit 51.
, A red signal VR, a blue signal VB, and a green VG (the reference symbol Va is used when collectively referred to), the polarities of which are inverted in one horizontal scanning period by a signal (FRV) inverting in one horizontal scanning period. 8 given.

The polarity of the video signal Va is inverted with respect to the central value of the amplitude for each scanning line or each horizontal scanning period.
For example, if the video signal Va given to the first scanning line is positive, the video signal Va given to the second scanning line is negative. Such a drive is called one horizontal (lH) line inversion drive. It is known that this 1H line inversion drive has an effect of suppressing flicker (flicker).

[0008] A counter electrode drive signal Vc is applied to the counter electrode 5 via an input terminal 9. Counter electrode drive signal Vc
Is opposite in polarity to a video signal (not shown) whose polarity is inverted every horizontal scanning period applied to the signal electrode S,
The signal is a signal whose polarity is inverted every horizontal scanning period. For example, when a positive video signal is given to the first scanning line, a negative counter electrode driving signal is given to the counter electrode 5 and a negative video signal is given to the second scanning line. In this case, the counter electrode 5 is supplied with a counter electrode drive signal of positive polarity.

As the counter electrode drive signal, a signal for generating a counter electrode drive signal from the outside is used in the interface circuit 51 for inverting the polarity of the signal sent to the interface circuit 51 every one horizontal scanning period. F
RC), the polarity is inverted every horizontal scanning period, and the signal is amplified to a predetermined amplitude. By changing the amplification factor of the amplifier circuit in the interface circuit 51 to change the amplitude of the counter electrode drive signal, the luminance (brightness) of the entire matrix type liquid crystal display panel 1 can be changed. For example, the brightness is increased in a bright place such as outdoors where there is much ambient light, and the brightness is lowered in a dark place such as indoors where there is little ambient light.

Control signals such as a scanning pulse input to the gate driver 7 and a sampling pulse input to the source driver 8 are given from a control circuit 50. The scan pulse is a signal that defines the timing at which a scan signal for conducting the TFT 3 is applied to the scan electrode G. The sampling pulse is the input video signal Va
, A signal defining the timing for sampling the signal levels applied to a plurality of picture elements constituting one horizontal scanning line.

Hereinafter, a matrix type liquid crystal display panel 1 will be described.
Will be described with reference to FIG.

The gate driver 7 includes, as shown in FIG.
A scanning signal (gate-on signal) is applied to the scanning electrodes G of the matrix type liquid crystal display panel 1 in order. That is, the gate driver 7 scans the horizontal scanning lines in a predetermined order.
Time TH is assigned to scanning of one horizontal scanning line. This period TH is one horizontal scanning period. When the j-th horizontal scanning line is scanned, the TFT 3 connected to the j-th scanning electrode Gj conducts.

The source driver 8 samples the input video signal with a sampling pulse having a predetermined frequency, and outputs the video signal to the signal electrodes S1 to Sm in synchronization with the timing at which the gate driver 7 applies the gate-on signal. As a result, a video signal is written to the picture element 2 via the conductive TFT 3. The signal written in the picture element 2 is held for a period TV until the next writing.

The source driver 8 includes a plurality of output circuits corresponding to each of the plurality of signal electrodes S. FIG.
Is a conventional output circuit 10 provided in the source driver 8.
An example of the configuration will be described. The output circuit 10 corresponds to one signal electrode S, and applies a video signal to the corresponding signal electrode Si via the switching element 18. A blue signal (SB) and a green signal (S
G), a red signal (SR) is supplied to a blue or green color filter (not shown in FIG. 3) arranged on the side of the counter electrode of the picture element electrode 4 connected to the output terminal 22 via the signal electrode S. , Corresponding to red.

A switching element 12 is connected to an input terminal 11.
Is connected to one of the terminals. Switching element 12
Is connected to one electrode of a sampling capacitor CSMP and the switching element 13
Connected to one of the terminals. The switching element 12
Conduction / non-conduction is controlled by the sampling pulse. The other electrode of the sampling capacitor CSMP is grounded. The other terminal of the switching element 13 is connected to one electrode of the hold capacitor CM and to the positive input terminal of the differential amplifier 14. The switching element 13 is provided with a transfer signal TRF described later.
Thus, conduction / non-conduction is controlled. The other electrode of the hold capacitor CM is grounded.

The output terminal of the differential amplifier 14 is connected to the gate of an N-channel transistor 15 and the gate of a P-channel transistor 16. Differential amplifier 14
The constant current source 25 (external to the differential amplifier circuit 14 in FIG. 6) is a switching element 24 whose conduction / non-conduction is controlled by the power save signal PS output from the controller circuit 50 shown in FIG. Is connected to the ground.

The drain of the transistor 15 is connected to a source driver power supply for supplying a source driver power supply voltage Vcc.
The drains of the P-channel transistors are respectively connected to the ground. The sources of the transistors 15 and 16 are
It is connected to one terminal of a switching element 18 whose conduction / non-conduction is controlled by the power save signal PS, and to the inverting input terminal of the differential amplifier 14. The other terminals of the switching element 18 that are not connected to the sources of the transistors 15 and 16 are connected to the output terminal 22. The switching element 18 connects or disconnects the output terminal 17 of the charge / discharge circuit composed of the transistors 15 and 16 and the output terminal 22 of the output circuit 10.

The output terminal 22 is connected to the anode terminal of the diode 19 and the cathode of the diode 20. The cathode of the diode 19 is connected to the power supply terminal 16. The anode side of the diode 20 is connected to the ground.

FIG. 7 is a time chart showing the operation of output circuit 10.

Part (Vj) in display period of video signal
Are stored in the sampling capacitor CSMP when the sampling pulse SPj is input. At the time of writing the video signal to the picture element 2, as shown in FIG.
j rises and further maintains a high level for a predetermined period T3. During this time, the switching element 24 connected to the constant current source of the differential amplifier 14 is turned off. As a result, the constant current stops flowing, and a low power consumption mode is set. At the same time, the switching element 26 that connects the output of the differential amplifier circuit 14 to the ground is turned on because the power save signal PSj is input via the inverter 27, and the charge / discharge circuit composed of the transistors 15 and 16 is turned on. Connected to ground to prevent latch-up. This allows the transistor 1
6 turns on, and the output terminal 17 of the charge / discharge circuit composed of the transistors 15 and 16 is at the ground level. In addition, the switching element 18 that conducts / disconnects the charge / discharge circuit output terminal 17 and the output terminal 22 of the output circuit 10 is also brought into a non-conductive state by the power save signal PSj at a high level. The purpose of bringing the switching element 18 into a non-conducting state is that when the output terminal 17 of the charge / discharge circuit goes to the ground level, the signal electrode S connected to the output terminal 22 also goes to the ground level, and the liquid crystal present on the signal electrode S This is to prevent the counter electrode capacitively coupled to the layer from receiving a voltage change and affecting the display.

Next, the polarity of the counter electrode drive signal is inverted during a period T3 in which the power save signal PSj is at a high level. Thereafter, when the power save signal PSj becomes low level, the switching element 24 for conducting / non-conducting the constant current source 25 of the differential amplifier 14 with the ground becomes conductive, and the constant current source 25 is turned on. At the same time, the switching element 26 connected to the output of the differential amplifier circuit is turned off, and the output switching element 18 of the charging / discharging circuit is turned on.

Then, the transfer signal TRFj goes high for a predetermined transfer time T1, and the signal stored in the sampling capacitor CSMP is transferred to the hold capacitor CM and input to the positive input terminal of the differential amplifier 14. When the voltage input to the differential amplifier 14 is higher than the previous input voltage,
5 is higher than the threshold voltage of the transistor 15, the transistor 15 is turned on, the capacitive load of the signal electrode S is charged, and the voltage of the output terminal 22 is reduced to a voltage corresponding to the input voltage VIN. To rise. On the other hand, when the input voltage VIN is lower than the previous input voltage, that is, when the gate voltage of the transistor 16 is lower than the threshold voltage of the transistor 16, the transistor 16 is turned on to discharge the capacitive load of the signal electrode S. Output terminal 22
Falls to a voltage corresponding to the input voltage VIN.

The drive signal for the scan electrode Gj is a transfer signal TR
When Fj goes high, it goes high at the same time as it is output from the gate driver 7 described above. As a result, the TFT 3 corresponding to the scanning electrode Gj becomes conductive, and a video signal is written to the pixel electrode 4 via the signal electrode S.

The above operation is repeatedly performed every one horizontal scanning period. Note that the rise of the transfer signal, the rise and fall of the gate-on signal, the rise and fall of the counter electrode signal,
The rise and fall of the power save signal are performed outside the display period of the video signal.

[0025]

In the conventional output circuit 10, when the power save signal PS becomes high level, the constant current circuit 25 is connected to the switching element 24 for conducting / non-conducting to the ground and the output terminal 22. After the switching element 18 becomes non-conductive, the polarity inversion (rising or falling) of the counter electrode drive signal is performed. This is because the high level period (T3) of the power save signal for reducing the power consumption of the output circuit of the source driver is made as long as possible. However, the output terminal 22 is in an electrically unstable state during a period when the power save signal is at a high level <that is, when the switching element 18 connected to the output terminal 22 is in a non-conductive state. At this time, when the polarity of the counter electrode drive signal is inverted, the potential of the output terminal 22 is changed to the potential of the switching element 1 by capacitive coupling of liquid crystal present between the counter electrode 5 and the signal electrode S.
8, the voltage exceeds the withstand voltage of 8, and there is a problem that the switching element 18 is broken.

In order to solve this problem, the output terminal 22
Are connected to diodes 19 and 20 for protection. However, since these diodes are provided in all the output terminals 22 of all the output circuits of the source driver, when the source driver is formed on a chip as an integrated circuit, the occupation area becomes large. For this reason, the size of the source driver increases, and the number of source drivers that can be formed per wafer decreases, which is disadvantageous in cost.

As another solution to the above problem, there is a method of increasing the withstand voltage of the switching element 18. In this case, a high withstand voltage process that can withstand a voltage exceeding the power supply voltage Vcc of the source driver is required. This happens when,
This means that a high breakdown voltage process is added to the current breakdown voltage process of the power supply voltage Vcc or lower, and the chip size of the source driver increases. In addition, when two types of processes are used, the time required to create a source driver is lengthened, which causes a cost increase. Even if all processes of the source driver have high breakdown voltage, the chip size of the source driver is still large, which is disadvantageous in cost.

The present invention has been made in view of the above circumstances, and aims at low power consumption.
An object of the present invention is to provide an electrically stable source driver (signal electrode driving circuit) and a driving circuit of a liquid crystal display device including the same.

[0029]

A drive circuit according to the present invention comprises a counter electrode, a counter electrode drive circuit for applying a counter electrode drive signal thereto, a plurality of signal electrodes, and a signal electrode drive circuit for applying a video signal thereto. , A driving circuit for a matrix type liquid crystal display device, wherein the signal electrode driving circuit includes a plurality of output circuits corresponding to each of the plurality of signal electrodes, and each of the output circuits includes a first output circuit. A first switching circuit configured to apply the video signal to a corresponding signal electrode via a switching circuit;
In the period, the non-conductive state is established, and the timing at which the polarity of the counter electrode drive signal is inverted is not included in the first period, thereby achieving the above object.

In one embodiment, the output circuit comprises: a holding circuit for holding the video signal; a charging circuit for supplying a charging current to the signal electrode so as to have the same potential as the held video signal; A discharge circuit that supplies a discharge current to the signal electrode so as to have the same potential as the video signal, the first switching circuit that conducts or non-conducts the output of the charging circuit / discharge circuit, and a differential amplifier. A second switching circuit that conducts or non-conducts a constant current circuit in the differential amplifier; and outputs the output of the differential amplifier to a power supply of the differential amplifier, a power supply of the signal electrode drive circuit or a ground or the like.
A third switching circuit for connecting the discharging circuit to a voltage source for stabilizing the discharging circuit, wherein the second switching circuit is turned off during the first period,
The third switching circuit is conductive during the first period.

In one embodiment, the first period is 1
It is included in the non-display period between the output period of one video data and the output period of the next video data.

In one embodiment, the video signal and the counter electrode driving signal are inverted in polarity every horizontal scanning period, inverted in polarity every vertical scanning period, or inverted in polarity every horizontal scanning period and every vertical scanning period. Further, the opposite electrode drive signal has a polarity opposite to that of the video signal.

[0033] The liquid crystal display device according to the present invention achieves the above object by including the above driving circuit.

The operation of the present invention will be described below.

According to the present invention, a scanning signal for turning on the switching element in a line-sequential manner is applied to the scanning electrodes of the liquid crystal display panel every predetermined horizontal scanning period. The switching element connected to the scanning electrode to which the scanning signal has been applied conducts, and the video signal from the signal electrode drive circuit is applied to the picture element electrode via the switching element. For the counter electrode,
A counter electrode drive signal from a counter electrode drive circuit is applied. A voltage based on the video signal and the counter electrode drive signal is applied to the liquid crystal layer interposed between the picture element electrode and the counter electrode, and the optical characteristics (such as transmittance) of the liquid crystal layer change.
A predetermined display is performed. The video signal and the counter electrode drive signal have opposite polarities, and the polarity is inverted every horizontal scanning period. With such a driving method, flicker (flicker) is reduced. The counter electrode drive signal has an amplitude corresponding to the luminance level of the entire display panel set from the outside.

The signal electrode drive circuit comprises a plurality of output circuits provided for each signal electrode. The output circuit includes a holding circuit, a charging circuit, and a discharging circuit, and allows the charging / discharging circuit to supply a charging / discharging current to the signal electrode so that the potential of the video signal is the same as that of the video signal held in the holding circuit. This charge / discharge current is supplied to the picture element electrode via the switching element turned on by the scanning signal. The output circuit of the present invention further includes a circuit for turning on / off the charge / discharge current, and a circuit for turning on / off the switching element of the constant current circuit in the operational amplifier.

In the present invention, the inversion timing of the counter electrode drive signal is switched prior to the timing when the charge / discharge circuit output and the constant current circuit are switched from conduction to non-conduction during the non-display period. In other words, the period in which the switching circuit that controls conduction between the output of the charge / discharge circuit and the output terminal of the output circuit is nonconductive does not include the timing at which the counter electrode drive signal is inverted. According to the configuration of the present invention, when the counter electrode driving signal is inverted, the output terminal of the source driver is fixed to be the same voltage as the input terminal voltage VIN of the differential amplifier circuit, so that the output terminal is stable. Thus, there is no influence of the polarity switching of the counter electrode. As a result, the conventional output circuit (FIG. 6)
The diodes 19 and 20 for protection used in the above can be eliminated, and the circuit configuration is simplified,
Cost reduction is achieved.

Further, the switching of the common electrode is performed at the beginning of the non-display period, and the polarity of the common electrode drive signal is inverted, and then the power save signal is immediately raised to the high level, whereby the high level of the power save signal is obtained. Since the period is not so short, low power consumption is guaranteed.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a matrix type liquid crystal display device according to an embodiment of the present invention will be described with reference to FIG.

FIG. 3 schematically shows the structure of a matrix type liquid crystal display device. This liquid crystal display device includes a matrix type liquid crystal display panel 1 and a driving circuit (7,
8). FIG. 3 shows an equivalent circuit schematically showing an electric configuration of the matrix type liquid crystal display panel 1.

The matrix type liquid crystal display panel 1 has a plurality of picture elements 2 arranged in a matrix of n rows and m columns.
In FIG. 3, one horizontal scanning line is formed by a plurality of picture elements 2 for one row arranged in the horizontal direction. Therefore, the matrix type liquid crystal display panel 1 has n horizontal scanning lines. Although the picture element 2 is represented as a capacitor in the drawing, in actuality, the picture element electrode 4, a counter electrode 5 that is arranged to face the picture element electrode 4 at a predetermined interval, and a picture element electrode 4. And a liquid crystal layer 6 interposed between the liquid crystal layer 6 and the counter electrode 5. The pixel electrodes 4 are substantially rectangular electrodes and are arranged in a matrix of n rows and m columns. The counter electrode 5 has n
This is realized by one electrode provided commonly to all of the x m pixel electrodes 4. By changing the optical characteristics (such as transmittance) of the liquid crystal layer 6 due to the potential difference between the picture element electrode 4 and the counter electrode 5, for example, ON (light transmission) / OFF (light blocking)
Display is performed.

In the vicinity of the picture element 2, a plurality of switching elements (TFT, Thin Film Tran) for driving the picture element 2 are provided.
A sistor (thin film transistor) 3 is provided corresponding to each of the plurality of picture elements 2. The picture element electrode 4 of the picture element 2 is connected to the drain of the switching element 3. Note that a MOS (Metal Oxide Semiconductor) is used as the switching element 3.
or a metal oxide semiconductor) transistor.

The matrix type liquid crystal display panel 1 includes n scanning electrodes G1 to Gn (the reference numeral G is used when collectively referred to). Scan electrode G
Are arranged corresponding to each horizontal scanning line. j (j = 1 to
The gates of the plurality of TFTs 3 corresponding to the plurality of picture elements 2 forming the j-th horizontal scanning line are connected to the (n) th scanning electrode Gj. Further, the matrix type liquid crystal display panel 1 includes m signal electrodes S1 to Sm (referred to as a reference symbol S when collectively referred to) arranged in parallel with each other so as to be orthogonal to the scanning electrodes G. The signal electrode S is shown in FIG.
Are arranged corresponding to each picture element row arranged in the vertical direction on the paper surface of FIG. A plurality of TFs corresponding to the plurality of picture elements 2 forming the i-th picture element row are provided on the i-th (i = 1 to m) signal electrode Si.
Each source of T3 is connected.

The matrix type liquid crystal display panel 1 is driven by a drive circuit including a gate driver 7 (scan electrode drive circuit) and a source driver 8 (signal electrode drive circuit). The gate driver 7 is connected to the scanning electrodes G of the matrix type liquid crystal display panel 1, and the source driver 8 is connected to the signal electrodes S of the matrix type liquid crystal display panel 1. As shown in FIG. 4, the video signal V is, by the interface circuit 51, a red signal VR and a blue signal VB whose polarity is inverted in one horizontal scanning period by a signal (FRV) whose polarity is inverted in one horizontal scanning period from the control circuit 50. , Green VG (the reference numeral Va is used when collectively referred to) and is supplied to the source driver 8.

The polarity of the video signal Va is inverted with respect to the median value of the amplitude every scanning line or each horizontal scanning period.
For example, if the video signal Va given to the first scanning line is positive, the video signal Va given to the second scanning line is negative. Such a drive is called one horizontal (lH) line inversion drive. It is known that this 1H line inversion drive has an effect of suppressing flicker (flicker).
Note that the video signal Va may be subjected to one-frame inversion drive in which the polarity is inverted with respect to the central value of the amplitude every vertical scanning period. That is, the present invention can be applied to any case where the polarity of the video signal is inverted every horizontal scanning period, the polarity is inverted every vertical scanning period, or the polarity is inverted every horizontal scanning period and every vertical scanning period.

A counter electrode drive signal V is applied to the counter electrode 5 via an input terminal 9 by a counter electrode drive circuit (not shown).
c is applied. The counter electrode drive signal Vc is applied to the signal electrode S
Is a signal whose polarity is opposite to that of a video signal (not shown) whose polarity is inverted every horizontal scanning period, and whose polarity is inverted every horizontal scanning period. For example, when a positive video signal is given to the first scanning line, a negative counter electrode drive signal is given to the counter electrode 5 and
When a video signal of a negative polarity is given to the second scanning line, a counter electrode drive signal of a positive polarity is given to the counter electrode 5. Note that, in the present invention, also for the counter electrode drive signal, polarity inversion every horizontal scanning period, polarity inversion every vertical scanning period,
Alternatively, the present invention can be applied to any case where the polarity is inverted every horizontal scanning period and every vertical scanning period.

As the counter electrode drive signal, a signal for generating an external counter electrode drive signal from the outside is used in the interface circuit 51 for inverting the polarity of the signal sent to the interface circuit 51 every one horizontal scanning period. F
RC), the polarity is inverted every horizontal scanning period, and the signal is amplified to a predetermined amplitude. By changing the amplification factor of the amplifier circuit in the interface circuit 51 to change the amplitude of the counter electrode drive signal, the luminance (brightness) of the entire matrix type liquid crystal display panel 1 can be changed. For example, the brightness is increased in a bright place such as outdoors where there is much ambient light, and the brightness is lowered in a dark place such as indoors where there is little ambient light.

Control signals such as a scanning pulse inputted to the gate driver 7 and a sampling pulse inputted to the source driver 8 are given from the control circuit 50. The scan pulse is a signal that defines the timing at which a scan signal for conducting the TFT 3 is applied to the scan electrode G. The sampling pulse is the input video signal Va
, A signal defining the timing for sampling the signal levels applied to a plurality of picture elements constituting one horizontal scanning line.

The following describes the matrix type liquid crystal display panel 1
Will be described with reference to FIG.

As shown in FIG. 5, the gate driver 7
A scanning signal (gate-on signal) is applied to the scanning electrodes G of the matrix type liquid crystal display panel 1 in order. That is, the gate driver 7 scans the horizontal scanning lines in a predetermined order.
Time TH is assigned to scanning of one horizontal scanning line. This period TH is one horizontal scanning period. When the j-th horizontal scanning line is scanned, the TFT 3 connected to the j-th scanning electrode Gj conducts.

The source driver 8 samples the input video signal with a sampling pulse having a predetermined frequency, and outputs the video signal to the signal electrodes S1 to Sm in synchronization with the gate-on signal application timing by the gate driver 7. As a result, a video signal is written to the picture element 2 via the conductive TFT 3. The signal written in the picture element 2 is held for a period TV until the next writing.

The source driver 8 includes a plurality of output circuits corresponding to each of the plurality of signal electrodes S. FIG.
Shows a configuration example of the output circuit 100 according to the present invention. The output circuit 100 corresponds to one signal electrode S, and applies a video signal to the corresponding signal electrode Si via the switching element 18 (first switching circuit). A blue signal (SB), a green signal (SG), and a red signal (SR) input to the input terminal 11 as a video signal are supplied to the counter electrode side of the picture element electrode 4 connected to the output terminal 22 via the signal electrode S. Blue of the arranged color filter (not shown in FIG. 3),
Green and red are supported.

The input terminal 11 has a switching element 12
Is connected to one of the terminals. Switching element 12
Is connected to one electrode of a sampling capacitor CSMP and the switching element 13
Connected to one of the terminals. The switching element 12
Conduction / non-conduction is controlled by the sampling pulse. The other electrode of the sampling capacitor CSMP is grounded. The other terminal of the switching element 13 is connected to one electrode of the hold capacitor CM and to the positive input terminal of the differential amplifier 14. The switching element 13 is provided with a transfer signal TRF described later.
Thus, conduction / non-conduction is controlled. The other electrode of the hold capacitor CM is grounded.

The output terminal of the differential amplifier 14 is connected to the gate of the N-channel transistor 15 and the gate of the P-channel transistor 16. Differential amplifier 14
The constant current source 25 (external to the differential amplifier circuit 14 in FIG. 1) is a switching element 24 whose conduction / non-conduction is controlled by the power save signal PS output from the controller circuit 50 shown in FIG. (Second switching circuit) is connected to the ground.

The drain of the transistor 15 is connected to a source driver power supply for supplying a source driver power supply voltage Vcc.
The drains of the P-channel transistors are respectively connected to the ground. The sources of the transistors 15 and 16 are
It is connected to one terminal of a switching element 18 whose conduction / non-conduction is controlled by the power save signal PS, and to the inverting input terminal of the differential amplifier 14. The other terminals of the switching element 18 that are not connected to the sources of the transistors 15 and 16 are connected to the output terminal 22. The switching element 18 connects or disconnects the output terminal 17 of the charge / discharge circuit composed of the transistors 15 and 16 and the output terminal 22 of the output circuit 100.

FIG. 2 is a time chart for explaining the operation of the output circuit 100.

Part (Vj) in display period of video signal
Are stored in the sampling capacitor CSMP when the sampling pulse SPj is input. When writing the video signal to the picture element 2, first, as shown in FIG. 2, the polarity of the counter electrode drive signal is inverted at the beginning of the non-display period. Thereafter, the power save signal PSj goes high for a predetermined period T2 (first period), and the switching element 24 connected to the constant current source of the differential amplifier 14 is turned off. As a result, the constant current stops flowing, and a low power consumption mode is set.

At the same time, the switching element 26 (third switching circuit) that connects the output of the differential amplifier circuit 14 to the ground is turned on because the power save signal PSj is input via the inverter 27 and the transistor 15 is turned on. , 16 are connected to the ground so as not to latch up. This turns on the transistor 16 and turns on the transistors 15, 1
The output terminal 17 of the charge / discharge circuit constituted by 6 is at the ground level. In the present embodiment, the differential amplifier 1
4 is connected to the ground, but instead of the ground, the power supply of the differential amplifier 14 or the signal electrode driving circuit 1
00 may be connected to the power supply. Thereby, the electric state of the charging circuit / discharging circuit can be stabilized.

The high-level power save signal PSj also causes the switching element 18 for conducting / non-conducting the output terminal 17 of the charging / discharging circuit and the output terminal 22 of the output circuit 100 to be non-conductive.

In the present invention, as described above, the polarity inversion timing t of the counter electrode drive signal Vc is switched prior to the timing at which the charge / discharge circuit output and the constant current circuit are turned off from conduction in the non-display period. I have to. In other words, the output of the charge / discharge circuit and the output terminal 2 of the output circuit 100
The period T2 during which the switching element 18 that controls conduction with the second electrode 2 becomes nonconductive does not include the timing t at which the polarity of the counter electrode drive signal Vc is inverted. As a result, the output terminal 22 of the source driver 8 outputs the counter electrode drive signal Vc
Is fixed so as to be the same voltage as the input terminal voltage VIN of the differential amplifier circuit at the time when the polarity is inverted, the electrical state is stable, and the influence of the polarity switching of the counter electrode drive signal Vc is not affected. I will not receive it.

As shown in FIG. 2, the period T2 during which the power save signal PS is at the high level is the output period of one video data (corresponding to the video signal Vj) and the output period of the next video data (video (Corresponding to the signal Vj + 1), the power save signal PSj goes low after the period T2, which is included in the non-display period, to connect the constant current source 25 of the differential amplifier 14 to the ground. The non-conductive switching element 24 is turned on, and the constant current source 25 is turned on. At the same time, the switching element 26 connected to the output of the differential amplifier circuit is turned off, and the output switching element 18 of the charging / discharging circuit is turned on.

Then, the transfer signal TRFj becomes high level for a predetermined transfer time T 1, and the signal stored in the sampling capacitor CSMP is transferred to the hold capacitor CM and input to the positive input terminal of the differential amplifier 14. When the voltage input to the differential amplifier 14 is higher than the previous input voltage,
Is higher than the threshold voltage of the transistor 15, the transistor 15 is turned on, the capacitive load of the signal electrode S is charged, and the voltage of the output terminal 22 rises to the voltage corresponding to the input voltage VIN. I do. On the other hand, when the input voltage VIN is lower than the previous input voltage, that is, when the input voltage VIN is lower than the threshold voltage of the transistor 16, the transistor 16 is turned on and the capacitive load of the signal electrode S is discharged. The voltage drops to a voltage corresponding to the input voltage VIN.

The drive signal for the scan electrode Gj is the transfer signal TR
When Fj goes high, it goes high at the same time as it is output from the gate driver 7 described above. As a result, the TFT 3 corresponding to the scanning electrode Gj becomes conductive, and a video signal is written to the pixel electrode 4 via the signal electrode S. The video signal applied to the picture element electrode 4 is a video signal Va whose polarity has been inverted as shown in FIG. As described above, the video signal Va and the counter electrode drive signal Vc are such that the polarity is inverted every horizontal scanning period, the polarity is inverted every vertical scanning period, or the polarity is inverted every horizontal scanning period and every vertical scanning period. , And have opposite polarities to each other.

The above-described operation is repeatedly executed every one horizontal scanning period. Note that the rise of the transfer signal, the rise and fall of the gate-on signal, the rise and fall of the counter electrode signal,
The rise and fall of the power save signal are performed outside the display period of the video signal.

[0065]

According to the present invention, the counter electrode drive signal Vc
Is switched earlier than the timing at which the charge / discharge circuit output and the constant current circuit are turned off from conduction in the non-display period. In other words, the period T2 during which the switching element 18 that controls conduction between the output of the charge / discharge circuit and the output terminal 22 of the output circuit 100 is non-conductive is
The counter electrode driving signal Vc does not include the timing t at which the polarity is inverted. As a result, the output terminal 22 of the source driver 8 is fixed to have the same voltage as the input terminal voltage of the differential amplifier circuit at the time when the polarity of the counter electrode drive signal Vc is inverted. It is stable and is not affected by the polarity switching of the counter electrode drive signal Vc. As a result, the conventional output circuit (FIG. 6)
The diodes 19 and 20 for protection used in the above can be eliminated, and the circuit configuration is simplified,
Cost reduction is achieved.

The switching of the common electrode is performed at the beginning of the non-display period, and the polarity of the common electrode signal is inverted. Since power consumption is not shortened, low power consumption is guaranteed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an output circuit according to the present invention provided in a source driver.

FIG. 2 is a time chart for explaining the operation.

FIG. 3 is a schematic configuration diagram of a matrix type liquid crystal display device.

FIG. 4 is a block diagram illustrating a configuration related to a control circuit.

FIG. 5 is a time chart illustrating scanning of a matrix type liquid crystal display panel.

FIG. 6 is a diagram showing a configuration of a conventional output circuit provided in a source driver.

FIG. 7 is a time chart for explaining the operation.

[Explanation of symbols]

 Reference Signs List 1 matrix type liquid crystal display panel 2 picture element 3 TFT 4 picture element electrode 5 counter electrode 6 liquid crystal layer 7 gate driver 8 source driver 10, 100 output circuit of source driver 11 video signal terminal 12, 13, 18, 24, 26 switching element Reference Signs List 14 differential voltage amplifier 15, 16 transistor 17 differential amplifier circuit output terminal 19, 20 diode 22 source driver output terminal 23 power save signal terminal 25 constant current source of differential amplifier 50 control circuit 51 interface circuit G scan electrode S signal Electrode Vc Counter electrode drive signal CSMP Sampling capacitor CM Hold capacitor Vout Output voltage Vcc Source driver power supply PS Power save signal FRV Video signal 1H polarity inversion signal FRC Counter electrode signal 1H polarity inversion signal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA33 NA45 NC11 NC15 ND10 ND39 ND54 5C006 AA16 AC11 AC21 AF42 AF71 BB16 BC12 BF25 BF34 FA16 FA43 FA47 5C058 AA09 BA02 BA04 BA26 BA35 BB06 BB09 5C080 AA10 BB05 DD25 DD25 DD25 JJ02 JJ03 JJ04

Claims (5)

[Claims] 1. A matrix type liquid crystal display device comprising: a counter electrode; a counter electrode driving circuit for applying a counter electrode driving signal thereto; and a plurality of signal electrodes and a signal electrode driving circuit for applying a video signal thereto. A circuit, wherein the signal electrode drive circuit includes a plurality of output circuits corresponding to each of the plurality of signal electrodes, and each output circuit includes:
Timing for applying the video signal to a corresponding signal electrode via a first switching circuit, wherein the first switching circuit is non-conductive during a first period and the polarity of the counter electrode drive signal is inverted Denotes a driver circuit which is not included in the first period. 2. An output circuit comprising: a holding circuit for holding the video signal; a charging circuit for supplying a charging current to the signal electrode so as to have the same potential as the held video signal; A discharge circuit for supplying a discharge current to the signal electrode so as to be at the same potential as the first electrode, a first switching circuit for conducting or non-conducting an output of the charging circuit / discharge circuit, a differential amplifier, A second switching circuit that conducts or non-conducts a constant current circuit in the amplifier; and a charging / discharging circuit such as a power supply of the differential amplifier, a power supply of the signal electrode driving circuit, or a ground, which outputs an output of the differential amplifier. A third switching circuit for connecting to a voltage source for stabilization, wherein the second switching circuit is non-conductive during the first period, and the third switching circuit is connected to the first switching circuit.
2. The drive circuit according to claim 1, wherein the drive circuit is in a conductive state during the period. 3. The drive according to claim 1, wherein the first period is included in a non-display period between an output period of one video data and an output period of the next video data. circuit. 4. The video signal and the counter electrode drive signal are inverted in polarity every horizontal scanning period, inverted in polarity every vertical scanning period, or inverted in polarity every horizontal scanning period and every vertical scanning period. 4. The drive circuit according to claim 1, wherein the counter electrode drive signal has a polarity opposite to that of the video signal. 5. A liquid crystal display device comprising the drive circuit according to claim 1.