JP2001281303A - Semiconductor integrated circuit testing device, calibration method for it, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a relative error of a voltage set value fed to each pin of a measured device within the resolution range of a measurement system. SOLUTION: The semiconductor integrated circuit testing device is provided with a common-use direct current measurement part 16 measuring an actual voltage value, which is fed from a specific related circuit in the semiconductor integrated circuit testing device connected to respective pins of a measured device 100 to the respective pin, for every pin during inspection of the measured device, a ROM 12 storing a voltage preset value fed to each pin of the measured device during the inspection time, and a CPU 10 finding an error between a voltage measurement value measured by means of the direct current measurement part 16 and fed to each pin and the preset value for every pin, performing feedback so that a voltage value having the opposite polarity to the error polarity and serving as a correction value is impressed to a pin having an error above an allowance value in the measured device and setting a supply voltage so as to lower the error below the allowance value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test, and more particularly to a semiconductor integrated circuit test apparatus for a semiconductor integrated circuit test apparatus. For calibration during device testing.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 7-280885 discloses an invention relating to a method for calibrating a driver of a semiconductor integrated circuit test apparatus. According to the present invention, in the conventional semiconductor integrated circuit test apparatus, the device under test is separated from the semiconductor integrated circuit test apparatus when calibrating the driver. In order to solve the problem that the condition differs from the condition at the time of calibration due to the difference, the voltage level of the signal applied to the device under test is calibrated under the test condition of the device under test.

[0003]

SUMMARY OF THE INVENTION The above-mentioned JP-A-7-2
In the invention described in Japanese Patent No. 80885, the accuracy of the absolute value of the signal voltage level applied to the device under test is problematic. On the other hand, during inspection of a semiconductor device such as an LSI, the accuracy of the absolute value is also important, but the relative accuracy of the output of a specific related circuit system such as a power supply unit, a driver, and a comparator in a semiconductor integrated circuit test device is important. There are cases where it is desired to reduce the error even a little.

[0004] For example, L which is characterized by an analog linear circuit
If SI is the device to be measured, DC measurement,
In some cases, higher accuracy may be required under the set test conditions (such as a bias voltage applied to each pin of the device under test). A case where an unacceptable relative error occurs in a conventional semiconductor integrated circuit test apparatus due to an error included in a voltage applied to a device under test will be described with reference to FIG.

In FIG. 5, a voltage set value (programmed value) is supplied from tester driver channels # 1 and # 2 to pins A and B of a device under test 100 which is an LSI characterized by an analog linear circuit. In such a case, even in a calibrated semiconductor integrated circuit test device having a calibration function, the accuracy that the semiconductor integrated circuit test device guarantees is usually such that the tester driver channel # 1 is ± α (α = In the worst case, an error of + α occurs in the tester driver channel # 1 and an error of −α occurs in the tester driver channel # 2 in the guaranteed range. The same applies to the voltage supplied to the power supply terminal Vcc.

Reference output of device under test 100
When the voltage level of REF OUT is determined by the relative potential difference between the signal voltages supplied to the device under test 100 (including the voltage supplied to the power supply terminal Vcc), for example, the voltage supplied to the power supply terminal Vcc The device under test 100 determines the potential difference between the tester driver channel # 1 and the potential difference between the tester driver channel # 1 and the tester driver channel # 2 with respect to the supplied power supply voltage, and the reference output REF OUT is determined. In the worst case, + 2α occurs, but there is a problem that this error may not be allowed in the inspection.
The present invention has been made in view of such circumstances,
Provided are a semiconductor integrated circuit test apparatus, a calibration method for a semiconductor integrated circuit test apparatus, and a recording medium capable of suppressing a relative error of a voltage set value supplied to each pin of a device under test within a range of resolution of a measurement system. The purpose is to:

[0007]

According to one aspect of the present invention, there is provided a semiconductor integrated circuit for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test. In the method for calibrating a circuit test apparatus, a common measurement system is used to measure an actual voltage value supplied to each pin from a specific related circuit in the semiconductor integrated circuit test apparatus connected to each pin of the device under test. The measurement is performed for each pin during the inspection of the device under test, and the error between the measured value and the preset value is obtained for each pin. Feedback to apply a voltage value of the opposite polarity as a correction value to the corresponding pin of the device under test, and repeat the feedback operation until the error becomes equal to or less than an allowable value to reduce the supply voltage. Characterized in that it constant.

According to the first aspect of the present invention, the actual voltage value supplied to each pin from a specific related circuit in the semiconductor integrated circuit test device connected to each pin of the device under test is shared. Measurement is performed for each pin during the inspection of the device under test using a measurement system, and an error between the measured value and a preset value is obtained for each pin. The feedback is performed so that the voltage value of the opposite polarity of the error is applied to the corresponding pin of the device under test as a correction value, and the feedback operation is repeated until the error becomes equal to or less than the allowable value to set the supply voltage. Therefore, the relative error of the voltage set value supplied to each pin of the device under test can be suppressed within the range of the resolution of the measurement system.

The invention described in claim 2 is the first invention.
The method for calibrating a semiconductor integrated circuit test device according to
The correction value finally determined for each pin of the device under test is stored as an electronic file, and calibration measurement is not performed from the next test, and the device under test read out from the electronic file is read. A value obtained by adding a correction value for each pin to an apparent set value supplied to each pin is supplied to each pin as a set value.

According to the second aspect of the present invention, the correction value finally determined for each pin of the device under test is stored as an electronic file, and the calibration measurement is performed from the next test. Since the correction value for each pin of the device under test read from the electronic file is added to the apparent set value supplied to each pin as a set value and supplied to each pin as a set value, calibration is not performed. Time can be reduced.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test. A common voltage measuring means for measuring an actual voltage value supplied to each of the pins from a specific related circuit in the semiconductor integrated circuit test apparatus connected to each pin during the inspection of the device under test for each pin; And storage means for storing a preset value of a voltage supplied to each pin of the device under test during a test,
The error between the measured value of the voltage supplied to each pin measured by the voltage measuring means and the preset value stored in the storage means is obtained for each pin. Control means for feeding back such that a voltage value of the opposite polarity of the error is applied as a correction value to a corresponding pin of the device under test, and repeating the feedback operation until the error becomes equal to or less than an allowable value to set a supply voltage. And characterized in that:

According to a third aspect of the present invention, in a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test, A common voltage measuring means for measuring an actual voltage value supplied to each of the pins from a specific related circuit in the semiconductor integrated circuit test apparatus connected to each pin during the inspection of the device under test for each pin; And storage means for storing a preset value of a voltage supplied to each pin of the device under test during a test,
The error between the measured value of the voltage supplied to each pin measured by the voltage measuring means and the preset value stored in the storage means is obtained for each pin. Control means for feeding back such that a voltage value of the opposite polarity of the error is applied as a correction value to a corresponding pin of the device under test, and repeating the feedback operation until the error becomes equal to or less than an allowable value to set a supply voltage. Therefore, the relative error of the voltage setting value supplied to each pin of the device under test can be suppressed within the range of the resolution of the measurement system.

The invention described in claim 4 is the first invention.
5. The semiconductor integrated circuit test apparatus according to claim 2, further comprising a second storage unit that stores the correction value finally determined for each pin of the device under test as a file, wherein the control unit performs a next test. After that, no calibration measurement was performed, and the correction value for each pin of the device under test read from the file stored in the second storage means was added to the apparent set value supplied to each pin. A value is supplied to each pin as a set value.

According to the invention described in claim 4, according to claim 1 of the present invention,
5. The semiconductor integrated circuit test apparatus according to claim 2, further comprising a second storage unit that stores the correction value finally determined for each pin of the device under test as a file, wherein the control unit performs a next test. After that, no calibration measurement was performed, and the correction value for each pin of the device under test read from the file stored in the second storage means was added to the apparent set value supplied to each pin. Since the value is supplied to each pin as a set value, the calibration time can be reduced.

Further, the invention according to claim 5 provides a method for supplying a predetermined voltage or a test signal to each pin of a device under test and performing a test on a semiconductor integrated circuit test apparatus for performing various tests. The actual voltage value supplied to each pin from a specific related circuit in the semiconductor integrated circuit test device connected to each pin of the measurement device is measured for each pin using a common measurement system for each pin. A first process of measuring during the device inspection, and an error between the measured value and the preset value is obtained for each pin. For a pin having the error equal to or more than an allowable value, a voltage value having a polarity opposite to the error is obtained. And a third process of setting the supply voltage by repeating the feedback operation until the error becomes equal to or less than an allowable value. The recording medium readable by the recording a computer program for executing a process on a computer and gist.

According to the present invention, when calibrating a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test, The actual voltage value supplied to each pin from a specific related circuit in the semiconductor integrated circuit test device connected to each pin of the measurement device is measured for each pin using a common measurement system for each pin. A first process of measuring during the device inspection, and an error between the measured value and the preset value is obtained for each pin. For a pin having the error equal to or more than an allowable value, a voltage value having a polarity opposite to the error is obtained. And a third process of setting the supply voltage by repeating the feedback operation until the error becomes equal to or less than an allowable value. Since the program for causing the computer to execute the processing is recorded on a computer-readable recording medium, the program recorded on the recording medium is read into a computer system and executed, whereby The relative error of the voltage set value supplied to each pin can be suppressed within the range of the resolution of the measurement system.

Further, the invention according to claim 6 provides a method for calibrating a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test. The actual voltage value supplied at each pin from a specific related circuit in the semiconductor integrated circuit test device connected to each pin of the measurement device is measured for each pin using a common measurement system. A first process of measuring during the device inspection, and an error between the measured value and the preset value is obtained for each pin. For a pin having the error equal to or more than an allowable value, a voltage value having a polarity opposite to the error is obtained. And a third process of setting the supply voltage by repeating the feedback operation until the error becomes equal to or less than an allowable value. Processing and the correction values finally determined for each pin of the device under test are stored as an electronic file, and calibration measurements are not performed from the next test, and the measured values read from the electronic file are not stored. A program for causing a computer to execute a fourth process of supplying a value obtained by adding a correction value for each pin of the measuring device to an apparent set value supplied to each pin as a set value to each pin is recorded. The gist is a computer-readable recording medium.

According to the present invention, when a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of the device under test is calibrated, The actual voltage value supplied at each pin from a specific related circuit in the semiconductor integrated circuit test device connected to each pin of the measurement device is measured for each pin using a common measurement system. A first process of measuring during the device inspection, and an error between the measured value and the preset value is obtained for each pin. For a pin having the error equal to or more than an allowable value, a voltage value having a polarity opposite to the error is obtained. And a third process of setting the supply voltage by repeating the feedback operation until the error becomes equal to or less than an allowable value. Processing and the correction values finally determined for each pin of the device under test are stored as an electronic file, and calibration measurements are not performed from the next test, and the measured values read from the electronic file are not stored. A program for causing a computer to execute a fourth process of supplying a value obtained by adding a correction value for each pin of the measuring device to an apparent set value supplied to each pin to each pin as a set value is executed by the computer. Since the data is recorded on a readable recording medium, the calibration time can be reduced.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a schematic configuration of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit test apparatus 1 includes a CPU 10 for controlling each unit of the semiconductor integrated circuit device by executing a control program, a ROM 12 storing a control program and fixed data, and reading and writing data. RAM 14 as a storage element capable of
, A DC measurement unit 16, a multiplexer unit 18, and a pin electronics unit 20. In the RAM 14, a user setting data storage area and a work area of the CPU 10 are set.

The DC measuring section 16 has three functions: a function of applying a constant voltage to measure current, a function of applying a constant current to measure voltage, and a function of measuring voltage. It functions as a common measurement system that measures the voltage applied to or output from each pin of the device. In the embodiment of the present invention, a set voltage applied to each pin of the device under test (DUT) 100 is measured. DC measurement unit 1
Numeral 6 is connected to the pin electronics section 20 via a detection line (SNSE LINE) 30, a voltage (current) supply line (FORCE LINE) 31, and a multiplexer 18. The pin electronics section 20 includes a driver 200, a comparator 201, and a relay 202 (D
RV), 203 (CMP), 204 (DCS), 205
(DCF).

In the above configuration, the ROM of each device (DUT) (not shown) is read from the driver 200 in the pin electronics unit 20 via the relay 202 to the pins.
12 is supplied with a voltage of a predetermined set value stored in
The voltage output from each pin of the device under test is input to the comparator 201 via the relay 203 and is compared with a reference value. Further, the DC measurement unit 16 includes a detection line 30, a voltage (current) line 31,
The voltage applied to each pin of the device under test via the multiplexer unit 18 and the relays 204 and 205 or the voltage output from each pin is measured.

Next, FIG. 2 shows a configuration of a main part of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention. In FIG. 2, during the test of the device under test 100, which is an LSI featuring an analog linear circuit,
Tester driver channels # 1 and # 2 that supply a predetermined set voltage to pins A and B at 0, device under test 1
00, a power supply line 101 supplying a power supply voltage to a power supply terminal Vcc, and a reference output RE of the device under test 100.
Each voltage such as the voltage output from F OUT to the output line 102 connected to the comparator (built-in the pin electronics unit 20) side of the tester is relayed to the relay 111,
It is configured to be taken into the DC measurement unit 16 which is a common measurement system via 112, 113, 114. Other configurations are the same as those shown in FIG. Note that there are many terminals, that is, pins, of the device under test 100,
It is omitted for convenience of explanation.

The contents of the control program executed by the CPU 10 of the semiconductor integrated circuit test apparatus having the above configuration will be described with reference to the flowchart of FIG. When the control program stored in the ROM 12 shown in FIG. 3 is started, in step 300, the voltage values supplied from the tester driver channels # 1 and # 2 are set to the pins A and B of the device under test 100. . The power supply voltage and the like supplied to the power supply terminal VCC are similarly supplied with the set value voltage.

Next, a DC measuring unit 1 which is a common measuring system
6, the voltage values actually applied to the pins such as the pin A and the pin B are fetched via the relays 111, 112, 113 and 114, and are sequentially measured (step 301). Further, in step 302, a difference between the measured value and the preset value, that is, an error X is calculated. Next, it is determined whether or not the absolute value | X | of the error X is within the allowable value M (step 303). If the determination in step 303 is affirmative, that is, if it is determined that the absolute value | X | of the error X is within the allowable value M, the execution of this program ends.

On the other hand, in step 303, the absolute value of the error X |
If it is determined that X | is equal to or more than the allowable value M, the measured value of the absolute value | X | A setting is made so as to feed back to the corresponding pin (or terminal) of 100, that is, to add a correction value to an apparent set value (step 304). This feedback processing is repeatedly executed until the determination in step 303 is affirmed.

Next, FIG. 4 shows the specific contents of the control program executed by the CPU 10 of the semiconductor integrated circuit test apparatus shown in FIG. In the figure, when the control program is started, in step 400, test conditions of the device under test 100 are set. For example, the power supply line 101 has +5.50 V as the set value of the power supply voltage,
The pin electronics section 20 sets the voltage of the set value + 5.00V to the tester driver channel # 1 and the voltage of the set value + 4.50V to the tester driver channel # 2.

Next, a test of the device under test 100 is performed by the semiconductor integrated circuit device (step 40).
1). Further, in step 402, the common DC measurement unit 1
In step 6, the set voltage supplied to each pin of the device under test 100 is measured, and an error between the measured value and the set value is obtained (step 402). The potentials of the power supply line 101 and the tester drive channels # 1 and # 2 are sequentially measured, and errors + α, + β, and + γ between these measured values and the set values are obtained. Next, at step 403, it is determined whether or not these errors are within allowable values.

If the errors + α, + β, + γ are within the allowable values and can be ignored in step 403, the execution of this program is terminated. In step 403, the error + α,
When + β and + γ are each equal to or larger than the allowable value and cannot be ignored, the set value supplied to the power supply line 101 is −α.
For the tester driver channel # 1 as -β
Is supplied to the tester driver channel # 2 as a new set value so that -γ is fed back to the set value (step 404), and the process returns to step 401. The processing of steps 401 to 404
The process is repeated until the determination in step 403 is affirmed.

FIG. 6 is a flowchart showing a control operation during calibration of a conventional semiconductor integrated circuit test apparatus in comparison with a control operation during calibration of the semiconductor integrated circuit test apparatus according to the above-described embodiment of the present invention. In the figure, at step 500, test conditions for the device under test 100 are set. As in the case of FIG. 4, for example, a voltage of +5.50 V as the set value of the power supply voltage in the power supply line 101, a voltage of +5.000 V in the tester driver channel # 1, and a voltage of +4 in the tester driver channel # 2. A voltage of .50 V is set by the pin electronics unit 20 so as to be supplied.

Next, a test of the device under test 100 is performed by the semiconductor integrated circuit device (step 50).
1). Further, in step 502, the DC measuring unit 16 measures the set voltage of the reference output REF OUT in the device under test 100, and makes a determination. Here, in the conventional calibration method of the semiconductor integrated circuit test apparatus, since the relative error is not corrected, the voltage value supplied to each pin of the device under test 100, that is, the power supply line 101 supplying power to the power supply terminal Vcc The measurement is performed in a state where the guaranteed accuracy error ± α of the semiconductor integrated circuit test device is included in each set value in the tester driver channels # 1 and # 2.

Therefore, in the worst case, the errors β and γ of the set values of the tester driver channels # 1 and # 2 become β = +
α, γ = −α, that is, the measured value of the set value in the tester driver channel # 1 is + 5.00 + α
(V), the measured value of the set value in the tester driver channel # 2 is + 4.50-α (V), which is between the tester driver channels # 1 and # 2. In this case, as described above, since the judgment output of the reference output REF OUT is determined by the set values of the tester driver channels # 1 and # 2, the relative error includes an error of + 2α, which may hinder the judgment. There is.

On the other hand, in the semiconductor integrated circuit test apparatus according to the embodiment of the present invention, the set voltage at each pin of the device under test 100 is measured by the DC measuring section 16 which is a common measuring system. Therefore, the relative error of the voltage set value supplied to each pin of the device under test can be suppressed within the range of the resolution of the DC measurement unit 16.

In addition, when a correction value of the same magnitude as the error for each pin of the device under test 100 and of the opposite polarity is added to an apparent set value and fed back to set the corresponding pin. In the meantime, the correction value finally determined is stored as an electronic file, the calibration measurement is not performed from the next test, and the correction value for each pin of the device under test read from the electronic file is stored. A value added to the apparent set value supplied to each pin may be supplied to each pin as a set value. With this configuration, the calibration time of the semiconductor integrated circuit test device can be reduced.

As described above, according to the method for calibrating a semiconductor integrated circuit test apparatus according to the embodiment of the present invention,
The actual voltage value supplied to each pin from a specific related circuit in the semiconductor integrated circuit test device connected to each pin of the device under test is measured for each pin using a DC measurement unit which is a common measurement system. During the inspection of the device under test, and the error between the measured value and the preset value is obtained for each pin. For a pin whose error is equal to or more than an allowable value, the voltage value of the opposite polarity of the error is obtained. Is applied to the corresponding pin of the device under test as a correction value, and the supply voltage is set by repeating the feedback operation until the error becomes equal to or less than the allowable value. Can be suppressed within the range of the resolution of the measurement system.

According to the method of calibrating a semiconductor integrated circuit test apparatus according to the embodiment of the present invention, the correction value finally determined for each pin of the device under test is stored as an electronic file, From the next test, calibration measurement is not performed, and the value obtained by adding the correction value for each pin of the device under test read from the electronic file to the apparent set value supplied to each pin is used as the set value. Since the voltage is supplied to each pin, the calibration time can be reduced.

According to the semiconductor integrated circuit test apparatus according to the embodiment of the present invention, a semiconductor integrated circuit test apparatus which performs various tests by supplying a predetermined voltage or a test signal to each pin of a device under test is provided. The actual voltage value supplied to each of the pins from a specific related circuit in the semiconductor integrated circuit test apparatus connected to each of the pins of the device to be measured is being tested for each of the devices under test for each pin. A DC measuring unit 16 as a common voltage measuring unit for measuring the voltage, a ROM 12 as a storing unit storing a preset value of a voltage supplied to each pin of the device under test during a test, and a DC measuring unit 16. An error between the measured value of the voltage supplied to each pin and the preset value stored in the ROM 12 is obtained for each pin. For the pin to be supplied, feedback is performed so that a voltage value of the opposite polarity of the error is applied as a correction value to the corresponding pin of the device under test, and the feedback operation is repeated until the error becomes equal to or less than an allowable value to reduce the supply voltage. Since the apparatus has the CPU 10 as a control unit for setting, it is possible to suppress the relative error of the voltage set value supplied to each pin of the device under measurement within the range of the resolution of the measurement system.

Further, according to the semiconductor integrated circuit testing apparatus of the embodiment of the present invention, the second storage means for storing the correction value finally determined for each pin of the device under test as a file. The CP 10 as a control unit does not perform calibration measurement from the next test, and stores the correction value for each pin of the device under test read from the file stored in the RAM 14 for each pin. Is supplied to each pin as a set value in addition to the apparent set value supplied to each pin, so that the calibration time can be reduced.

Further, when a predetermined voltage or a test signal is supplied to each pin of the device under test to calibrate a semiconductor integrated circuit test apparatus for performing various tests, it is connected to each of the pins of the device under test. Measuring the actual voltage value supplied to each of the pins from a specific related circuit in the semiconductor integrated circuit test apparatus using a common measurement system during the inspection of the device under test for each pin. 1 and an error between the measured value and the preset value is obtained for each pin. For a pin whose error is greater than or equal to an allowable value, a voltage value having a polarity opposite to that of the error is used as a correction value for the corresponding device under test. A second process of providing feedback to the computer and a third process of setting the supply voltage by repeating the feedback operation until the error becomes equal to or less than an allowable value. The program to be executed is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system, and executed to calibrate the semiconductor integrated circuit test apparatus. Is also good.

By causing the computer system to read and execute the program recorded on the recording medium, the relative error of the voltage set value supplied to each pin of the device under test is suppressed within the range of the resolution of the measuring system. be able to.

Further, when calibrating a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of the device under test, the device is connected to each of the pins of the device under test. Measuring the actual voltage value supplied at each of the pins from a specific related circuit in the semiconductor integrated circuit test apparatus using a common measurement system during the inspection of the device under test for each pin. 1 and an error between the measured value and the preset value is obtained for each pin. For a pin whose error is greater than or equal to an allowable value, a voltage value having a polarity opposite to that of the error is used as a correction value for the corresponding device under test. A second process of setting the supply voltage by repeating the feedback operation until the error becomes equal to or less than an allowable value; The correction value finally determined for each pin of each device is stored as an electronic file, and calibration measurement is not performed from the next test, and each pin of the device under test read from the electronic file is stored. A program for causing a computer to execute a fourth process of supplying a value obtained by adding the correction value of (i) to the apparent set value supplied to each pin as a set value to each pin on a computer-readable recording medium Record it, and let the computer system read the program recorded on this recording medium,
By executing the calibration, the calibration of the semiconductor integrated circuit test apparatus may be performed.

Since the program recorded on the recording medium is read by a computer system and executed to execute the recording, the calibration time can be shortened.

It is to be noted that the “computer system” here includes an OS and hardware such as peripheral devices. The “computer system” includes a homepage providing environment (or a display environment) if a WWW system is used.

The "computer-readable recording medium" is a general-purpose medium such as a floppy (registered trademark) disk, a magneto-optical disk, a ROM, a CD-ROM, or a storage device such as a hard disk built in a computer system. That means. Further, a "computer-readable recording medium" refers to a communication line for transmitting a program via a network such as the Internet or a communication line such as a telephone line, and dynamically holds the program for a short time. In this case, a medium that stores a program for a certain period of time, such as a volatile memory in a computer system serving as a server or a client in that case, is also included.

The above program may be for realizing a part of the functions described above. Furthermore, a program that can realize the above-described functions in combination with a program already recorded in the computer system, that is, a so-called difference file (difference program) may be used.

[0045]

According to the first aspect of the present invention, the actual voltage value supplied to each pin from a specific related circuit in the semiconductor integrated circuit test apparatus connected to each pin of the device under test is determined. Measurement is performed for each pin during the inspection of the device under test using a common measurement system, and an error between the measured value and the preset value is obtained for each pin, and the pin whose error is equal to or more than an allowable value is obtained. For, the feedback is performed so that the voltage value of the opposite polarity of the error is applied as a correction value to the corresponding pin of the device under test, and the feedback operation is repeated until the error becomes equal to or less than the allowable value to set the supply voltage. With this configuration, the relative error of the voltage set value supplied to each pin of the device under test can be suppressed within the range of the resolution of the measurement system.

According to the second aspect of the present invention, the correction value finally determined for each pin of the device under test is stored as an electronic file, and the calibration measurement is performed from the next test. Since the correction value for each pin of the device under test read from the electronic file is added to the apparent set value supplied to each pin as a set value and supplied to each pin as a set value, calibration is not performed. Time can be reduced.

According to the third aspect of the present invention, there is provided a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test. A common voltage measuring means for measuring an actual voltage value supplied to each of the pins from a specific related circuit in the semiconductor integrated circuit test apparatus connected to each pin during the inspection of the device under test for each pin; And storage means for storing a preset value of a voltage supplied to each pin of the device under test during a test,
The error between the measured value of the voltage supplied to each pin measured by the voltage measuring means and the preset value stored in the storage means is obtained for each pin. Control means for feeding back such that a voltage value of the opposite polarity of the error is applied as a correction value to a corresponding pin of the device under test, and repeating the feedback operation until the error becomes equal to or less than an allowable value to set a supply voltage. Therefore, the relative error of the voltage setting value supplied to each pin of the device under test can be suppressed within the range of the resolution of the measurement system.

According to the invention described in claim 4, according to claim 1
5. The semiconductor integrated circuit test apparatus according to claim 2, further comprising a second storage unit that stores the correction value finally determined for each pin of the device under test as a file, wherein the control unit performs a next test. After that, no calibration measurement was performed, and the correction value for each pin of the device under test read from the file stored in the second storage means was added to the apparent set value supplied to each pin. Since the value is supplied to each pin as a set value, the calibration time can be reduced.

According to the fifth aspect of the present invention, when a predetermined voltage or a test signal is supplied to each pin of a device under test to perform various tests, the semiconductor integrated circuit test apparatus is calibrated. The actual voltage value supplied to each pin from a specific related circuit in the semiconductor integrated circuit test device connected to each pin of the measurement device is measured for each pin using a common measurement system for each pin. A first process of measuring during the device inspection, and an error between the measured value and the preset value is obtained for each pin. For a pin having the error equal to or more than an allowable value, a voltage value having a polarity opposite to the error is obtained. And a third process of setting the supply voltage by repeating the feedback operation until the error becomes equal to or less than an allowable value. Since the program for causing the computer to execute the processing is recorded on a computer-readable recording medium, the program recorded on the recording medium is read into a computer system and executed, whereby The relative error of the voltage set value supplied to each pin can be suppressed within the range of the resolution of the measurement system.

According to the present invention, when calibrating a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test, The actual voltage value supplied at each pin from a specific related circuit in the semiconductor integrated circuit test device connected to each pin of the measurement device is measured for each pin using a common measurement system. A first process of measuring during the device inspection, and an error between the measured value and the preset value is obtained for each pin. For a pin having the error equal to or more than an allowable value, a voltage value having a polarity opposite to the error is obtained. And a third process of setting the supply voltage by repeating the feedback operation until the error becomes equal to or less than an allowable value. Processing and the correction values finally determined for each pin of the device under test are stored as an electronic file, and calibration measurements are not performed from the next test, and the measured values read from the electronic file are not stored. A program for causing a computer to execute a fourth process of supplying a value obtained by adding a correction value for each pin of the measuring device to an apparent set value supplied to each pin to each pin as a set value is executed by the computer. Since the program is recorded on a readable recording medium, the computer system reads and executes the program recorded on the recording medium, thereby shortening the calibration time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the semiconductor integrated circuit test apparatus according to the embodiment of the present invention.

FIG. 3 is a flowchart showing a control operation of the semiconductor integrated circuit test device shown in FIG. 2;

4 is a flowchart showing a more specific control operation of the semiconductor integrated circuit test device shown in FIG.

FIG. 5 is a block diagram showing a configuration of a main part of a conventional semiconductor integrated circuit test apparatus.

6 is a flowchart showing a control operation of the conventional semiconductor integrated circuit test device shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit test apparatus 10 ... CPU 12 ... ROM 14 ... RAM 16 ... DC measurement part 100 ... Device under test 101 ... Power supply line 102 ... Output line 111,112,113,114 ... Relay

Claims (6)

[Claims] 1. A method for calibrating a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test. An actual voltage value supplied to each of the pins from a specific related circuit in the semiconductor integrated circuit test apparatus is measured for each pin during the inspection of the device under test using a common measurement system, and An error between the measured value and the preset value is obtained for each pin, and for a pin whose error is equal to or greater than an allowable value, a voltage value having a polarity opposite to that of the error is applied to the corresponding pin of the device under test as a correction value. A calibration method for a semiconductor integrated circuit test apparatus, wherein the supply voltage is set by repeating the feedback operation until the error becomes equal to or less than an allowable value. 2. The correction value finally determined for each pin of the device under test is stored as an electronic file, and a calibration measurement is not performed from the next test, and is read from the electronic file. 2. The semiconductor integrated circuit according to claim 1, wherein a value obtained by adding the corrected value for each pin of the device under test to an apparent set value supplied to each pin is supplied to each pin as a set value. Calibration method for test equipment. 3. A semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test, wherein the semiconductor integrated circuit connected to each pin of the device under test Common voltage measuring means for measuring an actual voltage value supplied to each of the pins from a specific related circuit in a test apparatus for each pin during the inspection of the device under test; A storage unit in which a preset value of a voltage supplied to each pin is stored; and a storage unit storing a measured value of the voltage supplied to each pin measured by the voltage measurement unit and a preset value stored in the storage unit. An error is determined for each pin, and for a pin whose error is equal to or greater than an allowable value, a voltage value having a polarity opposite to the error is applied to the corresponding pin of the device under test as a correction value. And a control means for setting the supply voltage by repeating the feedback operation until the error becomes equal to or less than an allowable value. 4. A second storage means for storing, as a file, the correction value finally determined for each pin of the device under test, wherein the control means is provided for calibrating from the next test. Measurement is not performed, and a value obtained by adding the correction value for each pin of the device under test read from the file stored in the second storage means to the apparent set value supplied to each pin is used as the set value. 2. The semiconductor integrated circuit test apparatus according to claim 1, wherein the test signal is supplied to each pin. 5. When calibrating a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test, the device is connected to each of the pins of the device under test. Measuring the actual voltage value supplied to each of the pins from a specific related circuit in the semiconductor integrated circuit test apparatus using a common measurement system during the inspection of the device under test for each pin. 1 and the error between the measured value and the preset value is determined for each pin,
For a pin whose error is equal to or greater than an allowable value, a second process of feeding back such that a voltage value of the opposite polarity of the error is applied as a correction value to a corresponding pin of the device under test, and the error is equal to or less than the allowable value. And a third process for setting the supply voltage by repeating the feedback operation until the computer becomes readable by a computer. 6. When calibrating a semiconductor integrated circuit test apparatus for performing various tests by supplying a predetermined voltage or a test signal to each pin of a device under test and connecting it to each of the pins of the device under test. Measuring the actual voltage value supplied at each of the pins from a specific related circuit in the semiconductor integrated circuit test apparatus using a common measurement system during the inspection of the device under test for each pin. 1 and the error between the measured value and the preset value is determined for each pin,
For a pin whose error is equal to or greater than an allowable value, a second process of feeding back such that a voltage value of the opposite polarity of the error is applied as a correction value to a corresponding pin of the device under test, and the error is equal to or less than the allowable value. A third process of setting the supply voltage by repeating the above-mentioned feedback operation until the correction value finally determined for each pin of the device under test is stored as an electronic file, and is stored in the next test. No calibration measurement is performed from then on, and the value obtained by adding the correction value for each pin of the device under test read from the electronic file to the apparent set value supplied to each pin is supplied to each pin as a set value. And a computer-readable recording medium recording a program for causing a computer to execute the fourth process.