JP2001281292A - Method and device for calibrating voltage generator of ic testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To propose a calibrating method for a voltage generator which can calibrate in a short time the arithmetic value of the voltage generator whose voltage generation characteristics should accurately be calibrated. SOLUTION: By this calibrating method for a voltage generator, an offset voltage set in an offset voltage setter and the value of a gain set in a gain setter are found as correction coefficients after being calibrated by a voltage setter which sets a voltage value to be generated, an offset voltage setter, an adder which adds values set in those voltage setter and offset voltage setter, a multiplier which multiplies the addition result of the adder by a gain set value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a device for calibrating a voltage generator used in a semiconductor device test apparatus for testing a semiconductor integrated circuit device (hereinafter referred to as a semiconductor device).

[0002]

2. Description of the Related Art FIG. 4 shows a schematic calibration of a semiconductor device test apparatus. In the figure, TES indicates the entire semiconductor device test apparatus. Semiconductor device test equipment TES is main controller 1
1, a pattern generator 12, a timing generator 13, a waveform formatter 14, a logical comparator 15, a driver 16,
Analog comparator 17, failure analysis memory 18, logic amplitude reference voltage source 21, comparison reference voltage source 22, device power supply 23
And so on.

The main controller 11 is generally constituted by a computer system. The main controller 11 mainly controls a pattern generator 12 and a timing generator 13 according to a test program created by a user, and generates test pattern data from the pattern generator 12. The pattern data is converted by the waveform formatter 14 into a test pattern signal having a real waveform, and the test pattern signal is amplified by the driver 16 which amplifies the voltage of the test pattern signal into a waveform having the amplitude value set by the logical amplitude reference voltage source 21. 19 and stored.

A response signal read from the device under test 19 is compared with a reference voltage supplied from a comparison reference voltage source 22 by an analog comparator 17 and has a predetermined logic level (H logic voltage, L logic voltage). Judge whether or not
The signal determined to have the predetermined logic level is compared with the expected value output from the pattern generator 12 by the logic comparator 15, and when a mismatch occurs with the expected value, the signal is read to the memory cell of the read address. Judge that there is a defect,
Each time a failure occurs, a failure address is stored in the failure analysis memory 18, and at the end of the test, for example, it is determined whether or not the failure cell can be rescued.

[0005] Here, the timing generator 13 has a timing for defining a rising timing and a falling timing of the waveform of the test pattern signal supplied to the device under test 19, and a strobe for defining the logical comparison timing in the logical comparator 15. Generate pulse timing. Each of these timings is described in a test program created by the user, and is configured to operate the device under test 19 at a timing intended by the user and to test whether the operation is normal or not.

FIG. 4 shows a configuration in which a test pattern signal is supplied to one input pin of the device under test 19 and a configuration in which a response signal output from one output pin is fetched and logically compared. In the configuration, the number of pins of the device under test 19 is the same as that shown in FIG. Approximately 64 pins when the device under test 19 is a memory, and 250 to 50 pins when the device under test 19 is a logic IC.
It is about 0 pins. Here, the configuration of the analog comparator 17 will be described in more detail. The analog comparator 17 has two voltage comparators CP1 and CP2 as shown in FIG. 5, and the comparison reference voltage source 22 has two voltage generators 22A and 22B.
And equipped with The non-inverting input terminal of one voltage comparator CP1 is applied with the comparison voltage VOH of the H logic side from the voltage generator 22A, and the inverting input terminal of the other voltage comparator CP2 is applied with the comparison voltage VOH of the L logic side from the voltage generator 22B. Comparison voltage V
OL is applied. The inverting input terminal of the voltage comparator CP1 and the non-inverting input terminal of the voltage comparator CP2 are commonly connected and connected to the input terminal 17A, and the response output signal VO of the semiconductor device under test is applied to the input terminal 17A.

The response output signal V0 and the comparison voltage VOH,
As is clear from the relationship shown in FIG. 6 with the VOL,
If the L logic of the response output signal VO of the semiconductor device under test is more negative than the comparison voltage VOL, the voltage comparator CP2 outputs L
By outputting the logic and outputting this L logic, the comparison result of the analog comparator 17 is determined to be a pass. If the H logic of the response output signal VO is more positive than the comparison voltage VOH, the voltage comparator CP1 outputs the L logic, and by outputting this L logic, the analog comparator 17 determines that the comparison result is a pass. I do.

As described above, the voltage comparators CP1 and CP1
2 is a comparison voltage VO set in the voltage generators 22A and 22B.
Since the logic value of the signal VO output from the semiconductor device under test 19 is determined based on H and VOL,
These comparison voltages VOH and VOL must definitely be set to the correct values. Voltage generator 22A
And 22B, when a voltage value to be generated as a basic function is input as a digital value, it is required that the voltage value be correctly output as an analog voltage. For this purpose, a correction operation unit is provided, and the correction operation unit is configured to correctly output the voltage as an analog voltage even if any voltage value is set.

FIG. 7 shows the internal structure of the voltage generator 22A or 22B. 24 is a voltage setting device for setting a voltage value to be output as a digital value, 25 is an offset setting device for setting an offset voltage, 26 is an adder, 27 is a gain setting device,
28 is a multiplier, 29 is a digital-analog converter. The adder 26 performs an operation of removing the offset voltage from the set value set in the voltage setter 24. The voltage value, offset voltage value, and gain value set in the voltage setting device 24 are set from the main controller 11 through the bus line BUS.

A multiplier 28 multiplies the voltage value from which the offset voltage has been removed by the gain set in the gain setting unit 27, inputs the multiplication result to a digital-analog converter 29, converts the multiplication result into an analog voltage, and outputs the analog voltage. 30 and apply the analog voltage to the voltage comparator CP1 or CP2. Here, a conventional offset voltage and gain calibration method will be described. The digital-analog converter 29 outputs an analog voltage having a level proportional to the input operation value. The calculated value is given by: calculated value = (voltage setting value + offset value) gain (1).

In order to determine an appropriate offset value and gain in the equation (1), it is necessary to determine the value of the analog voltage output to the output terminal 30 at at least two different points. First, the offset value is set to F0 and the gain value is set to GA as temporary settings (FIG. 9A). Assuming that the calculated values when the set values are 0V (S0) and 3V (S3) are R0 and R3, from the equation (1), R0 = (S0 + F0) GA (2) R3 = (S3 + F0) GA (3) I can lead.

The actual analog voltage values when the calculated values R0 and R3 are input to the digital-analog converter 29 are D0 and D3 shown in FIG. Further, the calculated values at which the output levels should be set values S0 and S3 are G0 and G3. There is a proportional relationship between these calculated values G0, G3 and R0, R3 and the output levels S0, S3 and D0, D3, and the following equation can be derived. (G0-R0) / (S0-D0) = (R3-R0) / (D3-R0) (4) (G3-R0) / (S3-D0) = (R3-R0) / (D3-R0) (5) When G0 and G3 are solved from the equations (4) and (5), G0 = (D3 × R0−D0 × R3 + S0 × R3-S0 × R0) (6) G3 = (D3 × R0−D0 × R3 + S3 * R3-S3 * R0) (7)

Therefore, the offset value (N0) and the gain value (NG) may be obtained so that the calculated values when the set values are S0 and S3 are G0 and G3 (FIG. 9B). (2),
By substituting the corresponding variables using equation (3), G0 = (S0 + N0) × NG (8) G3 = (S3 + N0) × NG (9), and from equations (8) and (9), N0, NG Are obtained as corrected correction values.

By determining N0 and NG, the operation values of the voltage generators 22A and 22B are calibrated, and the set value and the output value become equal as shown in FIG. 9B. In order to perform the above-described calibration, the output values D0 and D3 must be actually measured. Conventionally, in order to measure the output values D0 and D3, a reference voltage generator 32 is selectively connected to the input terminal 17A of the analog comparator 17 as shown in FIG. The reference value VS output from the voltage generator 22A or 22B and the reference voltage V while gradually changing the reference voltage VS output from the reference voltage generator 32 are generated.
S is compared with the voltage comparator CP1 or CP2, and D0 and D3 are determined by the value of the output voltage VS of the reference voltage generator 32 when the polarity of the output of the voltage comparator CP1 or CP2 is inverted.
Is measured.

The operation of detecting that the polarity of the output of the voltage comparator CP1 or CP2 has been reversed is performed using an operation mode for testing the semiconductor device 19 under test. That is, one strobe pulse STB is applied to the voltage comparators CP1 and CP2 every test cycle. The voltage comparators CP1 and CP2 execute a comparison operation each time the strobe pulse STB is input, and send out the comparison result to the logic comparator 15. For example, when the voltage generator 22A is generating the voltage D0 having a positive polarity, the reference voltage generator 32
Input voltage VS smaller than voltage D0, voltage comparator CP1 outputs H logic. This H logic is determined as a failure (fail) by the logic comparator 15. The reference voltage generator 32 inverts the polarity of the output of the voltage comparator CP1 when the reference voltage VS, which gradually increases the voltage VS, for example, in each test cycle, exceeds the voltage D0, and outputs L logic.

The logic comparator 15 has a strobe pulse STB.
Comparator CP1 or CP2 at the application timing of
Is compared with the expected value, and the L logic is read to determine good (pass), and the determination result is sent to the main controller 11.

[0017]

As described above, the conventional one
The voltage VS of the reference voltage generator 32 is gradually changed in each test cycle until the logical comparison result of the logical comparator 15 is inverted from, for example, fail to pass, and the voltage of the reference voltage generator 32 when the logical comparison result is inverted. The comparison voltage generated by the voltage generators 22A and 22B is measured by a method of knowing the value of the comparison voltage D0 output from the voltage generator 22A or 22B from the voltage of VS, and this measurement is performed over two voltages having different values. By measuring, the voltage generator 22A
And 22B are calculated, there is a disadvantage that this measurement takes time.

Of course, when the voltage VS of the reference voltage generator 32 is changed, there is a disadvantage that the settling time until the target voltage is stabilized is relatively long, so that a long waiting time is required. That is, the operation of gradually changing the reference voltage VS cannot be speeded up. Further, each analog comparator 17 has two voltage generators 22A and 22B, and D0 is provided to each of the voltage generators 22A and 22B.
And D3 must be measured at four points in total. In addition, since only one reference voltage generator 32 is provided for a plurality of analog comparators 17, it is necessary to calibrate each analog comparator 17 one by one. Therefore, there is a disadvantage that the operation of calibrating the generated voltages of the voltage generators 22A and 22B provided in each analog comparator 17 requires a long time.

An object of the present invention is to provide a method for calibrating a voltage comparator in an IC test apparatus capable of calibrating a voltage generated by a voltage generator attached to an analog comparator in a short time, and a voltage calibrator operating according to the calibration method. Is proposed. According to a first aspect of the present invention, there is provided a voltage comparator for comparing whether or not a logical value of a response signal output from an IC under test has a predetermined voltage, and a voltage generator for applying a comparison voltage to the voltage comparator. And a reference voltage having a known value is applied to an input terminal of a voltage comparator to which a response signal of the IC under test is applied,
With the reference voltage fixed, the comparison voltage output by the voltage generator is changed, and based on the comparison result of the voltage comparator, it is detected that the value of the comparison voltage output by the voltage generator matches the reference voltage, and the comparison voltage is detected. A voltage generator in an IC test apparatus for determining a calculated value of a voltage generator by executing the specification of a value for a plurality of voltage values, and calculating a correction coefficient for obtaining a desired calculated value from the calculated value. We propose a calibration method.

According to a second aspect of the present invention, in the method for calibrating a voltage generator in an IC test apparatus according to the first aspect,
The voltage generator includes a voltage setter for setting a voltage value to be generated, an offset voltage setter, an adder for adding each set value set in the voltage setter and the offset voltage setter, and an addition of the adder. A multiplier configured to multiply the result by a gain setting value and a digital-analog converter configured to convert the multiplication result of the multiplier into an analog value are set in the offset voltage and gain setting devices to be set in the offset voltage setting device. We propose a method for calibrating a voltage generator in an IC test apparatus that determines a gain value as a correction coefficient for obtaining a desired operation value.

According to a third aspect of the present invention, in a method for calibrating a voltage generator in an IC test apparatus according to the second aspect,
The same voltage value S is applied to each of the voltage setting device and the reference voltage generator.
0 or S3 is set, and in each setting state of S0 or S3, the offset voltage value set in the offset setting device is changed,
The offset voltage value F0 or F at which the value of the comparison voltage actually applied from the digital-analog converter to the voltage comparator matches the voltage value S0 or S3 output by the reference voltage generator
3 and calculate the calculated value G0 or G3 by the value of the offset voltage F0 or F3 as G0 = (S0 + F0) GA and G
3 = (S3 + F3) GA, and these calculated values G
0 and G3, G0 = (S0 + N0) NG and G3 = (S0
+ N0) We propose a method of calibrating a voltage generator in an IC test apparatus for obtaining an offset voltage value N0 for determining a target operation value from NG and a gain value NG.

According to a fourth aspect of the present invention, there is provided a voltage setting device for setting a voltage value to be generated, an offset voltage setting device for setting an offset voltage, a voltage value set in the voltage setting device, and a setting in the offset voltage generator. An adder that adds the offset voltage thus set and outputs the addition result, a gain setting device that sets a gain value, and multiplies the gain value set in the gain setting device by the addition result output from the adder. A digital-to-analog converter that converts the multiplication result output from the multiplier into an analog voltage, and a reference voltage having a known value supplied from a reference voltage generator to one input terminal, and A voltage comparator to which an analog voltage output from the digital-analog converter is applied to an input terminal; and a digital-analog converter which detects that the logic of the comparison output of the voltage comparator is inverted. A logical comparator for detecting that the analog voltage converter output matches the reference voltage, sets the voltage S0 or S3 to the voltage setter and the reference voltage generator,
A controller for temporarily setting the offset voltage F0 in the offset voltage setting device and a gain value GA for the gain setting device, and a digital-analog converter for changing the offset voltage value F0 set in the offset voltage setting device in this setting state. An offset voltage varying means for changing an analog voltage applied to the voltage comparator from the comparator, and detecting a match between the voltages S0 and S3 output from the reference voltage generator by changing the analog voltage,
An offset voltage measuring means for obtaining the offset voltage values F0 and F3 satisfying the coincidence condition;
(S3 + F3) Determined by GA, and G0 = (S0 + N0) NG and G3 = (S3 + N) from these calculated values G0 and G3.
0) An apparatus for calibrating a voltage generator in an IC test apparatus constituted by an offset voltage value N0 for giving a target operation value by NG and an operation means for obtaining a gain value NG is proposed.

[0023]

According to the method for calibrating a voltage generator in an IC test apparatus according to the present invention, the reference voltage output from the voltage generator to be calibrated is changed while the reference voltage output from the reference voltage generator is fixed. Since the method of detecting the coincidence between the value of the comparison voltage and the value of the reference voltage and knowing the value of the comparison voltage output by the voltage generator is adopted, there is no need to wait for the settling time of the reference voltage output by the reference voltage generator. .

Therefore, it is only necessary to detect whether or not the comparison voltage matches the reference voltage with the logical comparator, and the time for measuring the value of the comparison voltage can be shortened. Further, the reference voltage VS
Is fixed, the reference voltage VS can be supplied to all the analog comparators 17 and calibration can be performed by changing the voltage of the voltage generator 22A or 22B in each analog comparator 17, so that a plurality of Calibration of the voltage generated by the voltage generator can be performed at the same time. In this respect, the advantage that the time required for calibration can be greatly reduced is obtained.

[0025]

FIG. 1 shows an embodiment of a voltage generator calibrating apparatus to which a voltage generator calibrating method used in an IC testing apparatus according to the present invention is applied. The analog comparator 17 of the IC test apparatus is provided with two voltage comparators CP1 and CP2 as described with reference to FIG. These two
The voltage values on the H logic side and the L logic side of the logic waveform output by the semiconductor device under test 19 (see FIG. 4) by the voltage comparators CP1 and CP2 are equal to or higher than the specified voltage VOH;
An operation of confirming that it is equal to or less than VOL is executed.

22A and 22B are voltage comparators CP1 and CP
2 shows a voltage generator for applying the comparison voltages VOH and VOL. FIG. 1 shows a connection state of a mode for calibrating a calculation value for determining a generation characteristic of a comparison voltage generated by the voltage generators 22A and 22B. In the calibration mode, one input terminal of each of the voltage generators CP1 and CP2 is connected to the common connection point A, and the output terminal of the reference voltage generator 32 is connected to the common connection point A by switching the switch SW1.

The reference voltage VS is applied from the reference voltage generator 32 to the common connection point A in place of the response output signal VO output from the semiconductor device under test 19 by switching the changeover switch SW1. The main controller 11 includes an offset voltage measuring unit 11A and an offset voltage varying unit 11B.
And an operation unit 11C. These offset voltage measuring means 11A, offset voltage varying means 11B,
The operation means 11C is constituted by software for operating the main controller 11, respectively.

The same setting value S0 is set from the main controller 11 to the voltage setting unit 24 and the reference voltage generator 32. At the same time, F0 is set in the offset voltage setting unit 25 and the gain setting unit 27 as a temporary offset voltage setting value, and GA is set as a temporary gain value. In this provisional setting state, the offset voltage value F0 is gradually changed (in small increments) by the offset voltage variable means 11B, and the offset voltage value F0 'at which the logical value of the output of the voltage comparator CP1 is inverted is converted to the logical comparator 1
5 and the offset voltage measuring means 11A.

Therefore, in this state, the analog voltage value Q actually output from the digital-analog converter 29
(See FIG. 2) means that the voltage is calibrated to a value as close as possible to the voltage S0 output from the reference voltage generator 32. next,
The same set value S is set in the voltage setter 24 and the reference voltage generator 32.
Set 3. At the same time, the offset voltage setting unit 25
, The provisional offset voltage F3 and the provisional gain value GA are set in the gain setting unit 27.

In this provisional setting state, the offset voltage F3 is gradually changed by the offset voltage variable means 11B, and the offset voltage F3 at which the logical value of the voltage comparator CP1 is inverted.
Is measured by the logical comparator 15 and the offset voltage measuring means 11A. Digital-analog converter 2
9 are offset voltages F0 ′ and F3 ′ whose voltage Q matches the voltages S0 and S3 set in the reference voltage generator 32.
Is calculated, the calculating means 11C determines the values of the calculated values G0 and G3 of the voltage generator CP1 by G0 = (S0 + F0 ') GA G3 = (S3 + F3') GA, and calculates the calculated values G0 and G3. From the value of G0 = (S0 + N0) NG G3 = (S3 + N0) NG. Desired offset voltage N0 and gain value NG
Ask for. The calibration is completed by setting the obtained offset voltage N0 and gain value NG in the offset voltage setting unit 25 and the gain setting unit 27.

Although the above description has been made with reference to the voltage generator 22A, the voltage generator 22B can be similarly calibrated. Further, calibration can be similarly performed for other analog comparators. FIG. 3 shows a modified embodiment of the present invention. In this embodiment, the voltage values of the H logic and the L logic of the drive signal output from the driver 16 are
(The voltage measuring function provided in the reference voltage source 32), and using the calibrated output signal of the driver 16, the voltage generator 22 provided in the analog comparator 17
An example in which a calibration method for calibrating the arithmetic values G0 and G3 of A and 22B will be described.

That is, in this example, the voltages corresponding to the known voltage values S0 and S3 are generated from the driver 16, and these voltages S0 and S3 are measured by using the voltmeter 33, and the voltages S0 and S3 are correct. Calibrate to a value. Driver 1
6, the calibrated voltage S0 or S3 is output, and the voltage generators 22A and 22B are calibrated in each state. Therefore, according to this embodiment, the semiconductor device test apparatus generally has the driver 16 for each pin, and each driver 16 outputs. For example, the voltages of H logic and L logic are calibrated to S0 and S3 as described above, so that the voltage generators 22A and 22A are independently provided for each pin as in the embodiment of FIG.
B can be calibrated.

[0033]

As described above, according to the present invention, the offset voltage F0 'satisfying the condition that the voltage Q output from the voltage generator 22A or 22B matches the voltages S0 and S3 output from the reference voltage generator 32. , F3 ′, it is not necessary to gradually change the voltage of the reference voltage generator 32. That is, the offset voltages F0 'and F
Since the time for measuring 3 'can be shortened, the time for calibrating the voltage generators 22A and 22B can be shortened. Further, the voltages S0 and S3 output from the reference voltage generator 32 can be shared by the analog comparators 17, and the analog comparators 17 can individually execute the calibration operation. Therefore, the calibration of the voltage generators 22A and 22B of many analog comparators 17 can be performed at the same time. As a result, there is obtained an advantage that the calibration of the voltage generator can be completed in a shorter time than the value of the number of pins of the IC under test as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a voltage generator calibrating apparatus that operates by applying the voltage generator calibrating method according to the present invention.

FIG. 2 is a graph for explaining a method of calibrating a voltage generator according to the present invention.

FIG. 3 is a block diagram for explaining a modified embodiment of the present invention.

FIG. 4 is a block diagram illustrating an outline of a semiconductor device test apparatus.

FIG. 5 is a block diagram for explaining the configuration and operation of an analog comparator used in the semiconductor device under test.

FIG. 6 is a waveform chart for explaining the operation of the analog comparator shown in FIG. 5;

FIG. 7 is a block diagram for explaining a conventional voltage generator calibration method.

FIG. 8 is a graph for explaining a conventional voltage generator calibration method.

FIG. 9 is a diagram for explaining a procedure of a conventional calibration method.

FIG. 10 is a block diagram for explaining a connection state of a conventional voltage generator in a calibration mode.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Main controller 11A Offset voltage variable means 11B Offset voltage measuring means 11C Calculation means 16 Driver 17 Analog comparator CP1, CP2 Voltage comparator 19 Semiconductor device under test 22A, 22B Voltage generator 24 Voltage setting device 25 Offset voltage setting device 26 Adder 27 gain setter 28 multiplier 29 digital-analog converter 30 output terminal 32 reference voltage generator

Claims (4)

[Claims] 1. A voltage comparator for comparing whether a logic value of a response signal output from an IC under test has a predetermined voltage, and a voltage generator for applying a comparison voltage to the voltage comparator. An analog comparator comprising: a reference voltage having a known value is applied to an input terminal of the voltage comparator to which the response signal is applied, and the voltage generator outputs a signal in a state where the reference voltage is fixed. A plurality of times of detecting that the value of the comparison voltage output by the voltage generator matches the reference voltage and specifying the value of the comparison voltage based on the comparison result of the voltage comparator. A method for calibrating a voltage generator in an IC test apparatus, comprising: obtaining an operation value of the voltage generator by executing the operation on a voltage value; and obtaining a correction coefficient for obtaining a desired operation value from the operation value. . 2. The voltage generator according to claim 1, wherein the voltage generator sets a voltage value to be generated, an offset voltage setter, and the voltage setter. An adder that adds each set value set in the offset voltage setting device, a multiplier that multiplies the addition result of the adder by a gain setting value, and a digital-analog that converts the multiplication result of the multiplier into an analog value. A converter for determining the offset voltage to be set in the offset voltage setter and the gain to be set in the gain setter as correction coefficients for obtaining the desired operation value. How to calibrate the voltage generator. 3. The method for calibrating a voltage generator in an IC test apparatus according to claim 2, wherein the same voltage value S0 or S3 is set to each of the voltage setter and the reference voltage generator, and the offset is set in each setting state. By changing the offset voltage value set in the setting device, the value of the comparison voltage actually applied from the digital-analog converter to the voltage comparator matches the voltage value S0 or S3 output from the reference voltage generator. The value F0 or F3 of the offset voltage is obtained, and the calculated value G0 or G3 is calculated using the value of the offset voltage F0 or F3 as G0 = (S0 + F0) GA and G3 = (S3 + F3).
3) Determined by GA, and calculated from these calculated values G0 and G3
A method for calibrating a voltage generator in an IC test apparatus, wherein an offset voltage value N0 for determining a target operation value and a gain value NG are determined based on 0 = (S0 + N0) NG and G3 = (S0 + N0) NG. . 4. A: a voltage setting device for setting a voltage value to be generated; B: an offset voltage setting device for setting an offset voltage; C: a voltage value set for the voltage setting device and the offset voltage generator An adder for adding the offset voltage set to the above, and outputting the addition result; D, a gain setter for setting a gain value; and E, a gain value set for the gain setter and an output from the adder. F, a digital-to-analog converter for converting the multiplication result output from the multiplier into an analog voltage; and G, a known input from a reference voltage generator to one input terminal. A voltage comparator to which a reference voltage having a value is applied and the analog voltage output by the digital-analog converter is applied to the other input terminal; and H, the logic of the comparison output of the voltage comparator is inverted. And a logic comparator for detecting that the analog voltage output by the digital-analog converter matches the reference voltage, and setting I, S0 or S3 in the voltage setting device and the reference voltage generator. A controller for temporarily setting an offset voltage F0 in the offset voltage setting device, a controller for temporarily setting a gain value GA in the gain setting device; and J, an offset voltage value F0 set in the offset voltage setting device in this setting state. Offset voltage varying means for varying the analog voltage supplied from the digital-analog converter to the voltage comparator; K, detecting a match between the voltages S0 and S3 output from the reference voltage generator by changing the analog voltage. An offset voltage measuring means for obtaining offset voltage values F0 and F3 satisfying the coincidence condition; The offset voltage value F0 which pressure measuring means has measured F3 by the calculated value G0 G3 G0 = (S
0 + F0) GA and G3 = (S3 + F3) GA, and G0 = (S0 + N) from these calculated values G0 and G3.
0) NG and G3 = (S3 + N0) NG, an offset voltage value N0 for providing a target operation value and an operation means for obtaining a gain value NG, and a calculation means for obtaining a gain value NG. apparatus.