JP2001274378A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor of a short gate length where a leakage current is suppressed for raised gate driving capacity. SOLUTION: On an MOSFET 20 formed on a silicon substrate 1, a gate insulating film 4 of a material other than a silicon oxide film and a gate electrode 5 positioned over the gate insulating film are provided. The material of gate insulating film has a permitting larger than the silicon oxide, while the thickness of gate insulating film is at a specified value or less so that a short channel effect equal to or less than that of an MOSFET which uses a gate insulating film of 1.5-2.0 nm in thickness whose main material is a silicon oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type field effect transistor (MOSFET: Metal Oxide Semiconductor Field E) used as a memory or logic element.
ffect Transistor).

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing a structure of an n-type MOSFET (for example, HSMomose et al. IEEE Electron Dev.
ices, vol.43, p.1233 (1996)). In FIG. 5, an element isolation region 2 and a p-type well 3 are formed on a p-type silicon substrate 1 whose main surface is a (100) plane, and an n-type MOSFET is formed so as to be surrounded by them. Source / drain extensions 6 containing n-type impurities are formed inside the source / drain regions 8 into which the n-type impurities are introduced so as to sandwich the channel region. A gate electrode 5 is formed on the channel via a gate insulating film 11, and a sidewall 7 is provided on a side wall thereof. The above n-type MO
In the SFET, when the thickness of the gate insulating film 11 is reduced, the gate capacitance increases. Therefore, the electron density induced in the channel by the application of the gate voltage increases, and the driving capability improves.
Further, since the gate electrode approaches the channel region on the substrate surface due to the reduction in thickness of the gate insulating film, the control of the channel region by the gate electrode can be enhanced. For this reason,
The short channel effect can be suppressed. As a result, in a miniaturized MOSFET, a normal transistor operation can be obtained even with a further shortened gate length.
Here, the short channel effect refers to a phenomenon accompanying the shortening of the gate length, such as a phenomenon in which the threshold voltage Vth becomes lower due to the influence of the drain / source potential.

[0003] As described above, thinning of a gate insulating film is performed by:
High driving capability and suppression of the short channel effect can be achieved, and high performance can be ensured by shortening the gate length.
However, the conventionally used silicon oxide film has a problem that the tunnel current rapidly increases when the film thickness becomes 3 nm or less. In the conventional example, the gate insulating film is 1.5 n
Even when m is shorter, the drain current increases as the gate length becomes shorter, so that the transistor operates normally as a single transistor. However, when integrated as an LSI, the leakage current of the gate greatly affects the power consumption during standby, and thus there is a limit in reducing the thickness of the gate insulating film using a silicon oxide film. For this reason, it is said that the limit of thinning the gate insulating film is 1.5 nm to 2.0 nm.

As a method of overcoming the above-mentioned situation, instead of a silicon oxide film having a relative dielectric constant of 3.9 which has been conventionally used, a gate made of a material having a relative dielectric constant larger than 3.9 is used. It is conceivable to form an insulating film. Even if such a material is used and the gate capacitance is increased by thinning, the actual film thickness can be made larger than the silicon oxide film when compared with the same capacitance. Therefore, the leak current can be reduced, and the above problem can be avoided.

[0005]

However, in the above discussion, only the effect of the gate capacitance determined by the film thickness in the vertical direction and the relative dielectric constant of the MOSFET is taken into consideration, and the effects in other directions are not taken into consideration. . For this reason, the two-dimensional effect when the gate length is actually made minute is unknown. That is, device characteristics have not been considered by taking into account the effect of adding the dimension in the gate length direction to the dimension in the vertical direction. For this reason, it is unclear which range of the gate insulating film thickness and relative permittivity can be suppressed to a range where the short channel effect and the leak current can be tolerated.

Accordingly, the present invention is directed to a semiconductor device using a high dielectric constant material for a gate insulating film in place of a silicon oxide film, wherein the semiconductor device has a short gate length with improved driving capability and reduced short channel effect. It is intended to provide a device.

[0007]

In a semiconductor device according to a first aspect of the present invention, a MOSFE formed on a silicon substrate is provided.
In T, a gate insulating film mainly made of a material other than the silicon oxide film, which is located on the silicon substrate, and a gate electrode located on the gate insulating film are provided. In this semiconductor device, the material forming the gate insulating film has a relative dielectric constant higher than that of silicon oxide, and the thickness of the gate insulating film is 1.5 nm or more, which is mainly composed of a silicon oxide film.
It is set to a predetermined value or less so as to have a short channel effect equal to or less than a short channel effect in a MOSFET using a gate insulating film of 2.0 nm (claim 1).

By using a gate insulating film having a relative dielectric constant larger than that of silicon oxide, a large capacitance can be ensured with a film thickness larger than that of a silicon oxide film. For this reason, it is possible to prevent a leak current that increases in a range of a thickness of 3 nm or less as seen in a conventional gate insulating film using silicon oxide. Further, the driving ability by the gate can be increased. Further, according to the above configuration, the thickness of the gate insulating film is reduced so that the short channel effect is equal to or less than the short channel effect in the MOSFET using the silicon oxide film having a thickness of 1.5 nm to 2.0 nm. . For this reason, even if the gate length is shorter than the current MOSFET of a gate insulating film using a silicon oxide film having a thickness of about 3 nm, the channel control by the gate can be maintained in a normal range. For this reason, even if the gate length is shortened from the current state as described above, the threshold voltage V
The phenomenon that th decreases due to the influence of the drain / source potential is eliminated. As a result, both miniaturization and high performance of the semiconductor device can be realized. Note that the thickness of the silicon oxide film of 1.5 to 2.0 nm is the minimum thickness that can be realized with the current gate insulating film. MOSFE using a silicon oxide film of this minimum thickness as a gate insulating film
At T, the gate length for normal transistor operation is still the minimum gate length at present, and is currently the most desirable from the viewpoint of miniaturization of the semiconductor device. Therefore, in the present invention, the thickness of the gate insulating film of the high dielectric constant material is set based on the current most desirable thickness of the gate insulating film for realizing miniaturization of the semiconductor device.

In a semiconductor device according to a second aspect of the present invention, in a MOSFET formed on a silicon substrate, a gate insulating film mainly made of a material other than a silicon oxide film and located on the silicon substrate; A gate electrode located on the insulating film. In this MOSFET, the material forming the gate insulating film has a relative dielectric constant larger than that of silicon oxide, and is the thickness of the gate insulating film, and the limit gate length that is the lower limit gate length for normal transistor operation is satisfied. MOS using a gate insulating film having a thickness of 1.5 nm to 2.0 nm and a silicon oxide film as a main material
The thickness range of the gate insulating film is set to be equal to or less than that of the FET (claim 2).

According to this configuration, (a) the gate length can be reduced to the current minimum gate length or less, which is useful for miniaturization of a semiconductor device, and (b) a high capacitance due to its high dielectric constant. (C) Leakage current can be suppressed due to the thick film thickness. With the above structure, the short channel effect is within a range where a normal transistor operation can be performed.

In the semiconductor device according to the first and second aspects, the thickness range of the gate insulating film is obtained by subtracting the threshold voltage Vth in the saturation region from the threshold voltage Vlin.th in the linear region. The limit gate length, which is the gate length at which the threshold voltage difference ΔVth becomes a predetermined value, is an MO using a gate insulating film having a thickness of 1.5 nm to 2.0 nm mainly composed of a silicon oxide film.
It is set to be equal to or less than the SFET (claim 3).

In the above, the threshold voltage difference ΔVth is
ΔVth = Vlin.th−Vth. When the short channel effect increases, the threshold voltage difference ΔVth increases because the reduction of Vth occurs more than the reduction of Vlin.th. That is, a large threshold voltage difference ΔVth means a large short channel effect. Further, the above-mentioned limit gate length means that even if the gate length is reduced to the limit gate length, the short-channel effect can be suppressed to a predetermined value or less that allows normal transistor operation. In a MOSFET having a gate insulating film having a thickness of 1.5 nm to 2.0 nm and having a silicon oxide film as a main material, although a leak current is large, even when the gate length is in a very short range, a short channel effect is suppressed and normal operation is performed. Actions can be taken. In the semiconductor device according to the second aspect, the short channel effect can be suppressed to a normal range even when the limit gate length is set to a very short range as described above,
Further, even in such a range, the thickness of the gate insulating film is sufficiently large, so that leakage current can be suppressed. Further, due to the high relative dielectric constant, the film thickness can be adjusted to be thin to further strengthen the channel control.

In the semiconductor device according to the second aspect, the limit gate length is a gate length at which the threshold voltage difference ΔVth becomes 50 mV.

According to this configuration, a gate length at which the threshold voltage difference ΔVth = 50 mV is adopted as one index of the short channel effect. MOS having a gate insulating film having a thickness of 1.5 nm to 2.0 nm mainly composed of a silicon oxide film
For the FET, the gate length at which the threshold voltage difference ΔVth = 50 mV can be obtained by device simulation. For other dielectrics, the gate length at which the threshold voltage difference ΔVth = 50 mV can be obtained by device simulation using the relative dielectric constant as a parameter. The above-mentioned MOSFET of the present invention has a ΔVth of 1.5 to 2.0 mm in the case of a silicon oxide film.
= 50 mV, that is, a gate insulating film that realizes a limit gate length equal to or less than the limit gate length which is the gate length. Therefore, sufficient miniaturization can be realized while suppressing the short channel effect.

In the semiconductor device according to the first and second aspects, the main material constituting the gate insulating film is barium titanate (BaSrTiO ₃ ), and the thickness thereof is 31 nm or less.

Barium titanate has a relative dielectric constant of 200 to 3
Since it is as high as 00, a sufficiently high capacity can be ensured even when the film thickness is increased. However, when the film thickness is too large, the channel dominance of the gate is reduced and the short channel effect is increased. The film thickness 31 nm is 1.5 nm to
MOSFET using 2.0nm thick silicon oxide film
In this case, the thickness is necessary to make the limit gate length equal to or less than the limit gate length, which is the gate length at which ΔVth = 50 mV. By setting the thickness of barium titanate to 31 nm or less, the short channel effect can be suppressed to a normal range even if the limit gate length is sufficiently reduced, and a low leak current and high driving capability can be secured.

The semiconductor device according to the first and second aspects described above.
In addition to the above barium titanate,
For example, (a) titanium oxide having a film thickness of 19 nm or less
(TiO _Two), (B) Oxidation whose film thickness is 11 nm or less
Tantalum (Ta_TwoO_Five), Zirconium oxide (ZrO)_Two)
And hafnium oxide (HfO_Two),
(C) Silicon nitride (Si) having a thickness of 4 nm or less_Three
N_Four) And alumina (Al_TwoO_Three),
Can be used (claims 6 to 8). Gate insulating film
The upper limit of the film thickness of each material is 1.5 nm to 2.0 nm.
In a MOSFET using a silicon oxide film, ΔVth =
Equal to or equal to the limit gate length, which is a gate length of 50 mV
This is the thickness required for the lower limit gate length.

In the semiconductor device according to the first and second aspects, a silicon oxide film having a thickness of 0.5 nm or less in contact with the gate insulating film and the silicon substrate is further provided.

A high dielectric material other than silicon oxide reacts with a silicon substrate during heat treatment or the like, and may not be used in some cases. In such a case, the reaction can be suppressed by interposing a thin silicon oxide film therebetween. The silicon oxide film having a thickness of 0.5 nm or less forms a combined capacitance in series with the gate insulating film of a high dielectric substance. Since the thickness of the silicon oxide film is 0.5 nm or less, the capacity of the silicon oxide film does not significantly decrease. For this reason, the combined capacitance in series is only about a fraction of the capacitance of the high dielectric substance alone, and the concept of the present invention can be applied without any problem. Therefore, it is possible to suppress a leak current and a short channel effect, and to secure a high driving capability. Further, a reduction in the order of the interface at the interface with the silicon substrate can also be realized. That is, by using a silicon oxide film having a thickness of 0.5 nm or less, the disadvantages caused by changing the material of the gate insulating film can be eliminated and stabilized.
The above effects can be ensured. If the thickness of the silicon oxide film exceeds 0.5 nm, the capacitance becomes small, the combined capacitance in series with the high dielectric substance decreases, and the driving capability by the gate decreases.

In the first and second semiconductor devices, a silicon oxide film having a thickness of 0.5 nm or less is provided between the gate insulating film and the gate electrode so as to be in contact with the gate insulating film and the gate electrode.

When a reaction occurs between the material forming the gate electrode and the gate insulating film during heat treatment or the like, a high dielectric material other than silicon oxide cannot be actually used. In such a case, a chemically stable state can be maintained by interposing a silicon oxide film of 0.5 nm or less as described above. As described above, there is no problem in terms of capacity. Also in the above structure, when the thickness of the silicon oxide film exceeds 0.5 nm, the combined capacitance in series with the high dielectric substance is reduced, and the driving capability of the gate is reduced.

[0022]

Next, an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) Here, an n-type MOSFET will be described as an example, but the effect of thinning the gate insulating film is the same for a p-type MOSFET. FIG. 1 is a schematic sectional view showing the configuration of the n-type MOSFET of the present embodiment. In FIG. 1, an element isolation region 2 and a p-type well 3 are formed on a p-type silicon substrate 1 whose main surface is a (100) plane, and an n-type MOSFET 20 is formed so as to be surrounded by them. n
A source / drain extension 6 containing an n-type impurity is formed inside the source / drain region 8 into which the type impurity is introduced so as to sandwich the channel region. A gate electrode 5 is formed on the channel with a gate insulating film 4 interposed therebetween, and a sidewall 7 is provided on a side wall thereof. The gate insulating film 4 is formed of a high dielectric constant material having a relative dielectric constant εr. Further, a silicide 9 is formed on the source / drain region and the gate electrode in FIG. The silicide 9 is provided to reduce the electric resistance in a region that is not in contact with the bottom of the plug for conducting with the upper wiring. Although the silicide 9 is formed in FIG. 1, the silicide 9 may or may not be provided for the present invention. The same applies to the silicide 9 on the gate electrode 5.

Here, the gate insulating film 4 can be formed by a sputtering method, a chemical vapor deposition method or the like. The thickness t of the gate insulating film is set according to the relative dielectric constant εr of the high dielectric constant material constituting the gate insulating film, as described below. Where the thickness is t and the relative permittivity is ε
The equivalent thickness teq of the silicon oxide film of the gate insulating film composed of the high dielectric constant material of r is defined by teq = t / (εr / 3.9). 2. The relative dielectric constant εr of the above high dielectric constant material is 3.
When it is larger than 9, teq of the gate insulating film having the same thickness t as the silicon oxide film t becomes smaller than t. As with the gate insulating film using a silicon oxide film, the gate capacitance increases as the thickness of the above-described gate insulating film decreases, so that the electron density induced in the channel region by the application of the gate voltage increases, and the driving capability increases. Improves. However, even if teq is reduced because εr is larger than 3.9, but the actual film thickness t is too large, the gate electrode and the channel region do not come close to each other. Can not. That is, the short channel effect cannot be suppressed.

Next, the result of setting the actual film thickness t by performing device simulation will be described. FIG.
By changing the relative dielectric constant εr of the gate insulating film in the range of 3.9 to 300 and changing the actual film thickness, teq = 1.5 nm
FIG. 5 is a diagram showing a relationship between a threshold voltage Vth and a gate length and a relationship between ΔVth and a gate length for a MOSFET having a constant value. The correspondence between the relative permittivity εr in FIG. 2 and specific materials is shown below. First, εr = 3.9 corresponds to a silicon oxide film. εr = 25 represents tantalum oxide (Ta ₂ O ₅ ),
Zirconium oxide (ZrO ₂ ), hafnium oxide (Hf
O ₂ ). Further, εr = 60 corresponds to titanium oxide (TiO ₂ ). Barium titanate (BaSrTiO ₃ ) corresponds to εr = 200-300. In FIG. 2, a threshold voltage Vth is a threshold voltage in a saturation region (drain voltage 1.0 V). The threshold voltage difference ΔVth is the difference between the threshold voltage Vlin.th in the linear region (drain voltage 0.05 V) and the threshold voltage Vth in the above-mentioned saturation region. That is, the threshold voltage difference ΔVth = Vlin.th−Vth.

As is apparent from FIG. 2, when the relative permittivity εr increases, the threshold voltage Vth decreases and the threshold voltage difference ΔVth increases, indicating that the short channel characteristics are degraded. . That is, even if teq is the same, the relative dielectric constant ε
As r increases, the gate length for normal transistor operation increases. Therefore, the limit gate length Lmin, which is the lower limit gate length for normal transistor operation, is defined as the gate length at which the threshold voltage difference ΔVth = 50 mV, and the actual thickness t of the high dielectric constant gate insulating film is The relationship with Lmin was determined. The results are shown in FIG. FIG. 3 shows the limit gate length L when the actual film thickness of the gate insulating film is said to be the limit of thinning the oxide film when the actual film thickness is 1.5 nm and 2.0 nm.
min is also shown. From FIG. 3, when εr of the high dielectric constant gate insulating film is determined, Lmin is improved as compared with the case of a silicon oxide film having a thickness of 1.5 nm or 2.0 nm if the actual film thickness t is not reduced below a certain value. You can know if not. The limit of the actual film thickness for each relative permittivity εr is as follows. (A) To improve Lmin over a silicon oxide film having a thickness of 2.0 nm: about 11 nm or less when εr = 25,
When εr = 60, it may be about 19 nm or less, when εr = 200, about 28 nm or less, and when εr = 300, it may be about 31 nm or less. Although not shown in FIG. 3, when εr = 7.5 corresponding to a silicon nitride film, the thickness may be set to about 4 nm or less. (B) To improve Lmin over a silicon oxide film having a thickness of 1.5 nm: when εr = 25, about 9 nm or less, εr
= 60 nm or less when εr = 200, and about 2 nm or less when εr = 300.
What is necessary is just to make it 8 nm or less. When εr = 7.5 corresponding to the silicon nitride film, the thickness may be set to about 3 nm or less.

By using the high dielectric constant film having the actual film thickness as described above for the gate insulating film, the channel length can be shortened without deteriorating the short channel characteristics.

Second Embodiment In the first embodiment, the high-dielectric-constant gate insulating film has a single-layer structure, and is therefore composed of a film having one kind of εr. In the semiconductor device of this embodiment, as shown in FIG. 4, a gate insulating film having a multilayer structure in which a low dielectric constant buffer layer such as a silicon oxide film having a thickness of 0.5 nm or less is provided on the silicon substrate side is used. . By adopting the multi-layered gate insulating film having a silicon oxide film having a thickness of 0.5 nm or less, it is possible to reduce the order of interfaces formed between the gate insulating film and the silicon substrate and to suppress a reaction due to heat. Can be. In addition, since the thickness of the silicon oxide film is as small as 0.5 nm or less, the capacity of this portion does not significantly decrease. Therefore, the combined capacitance of the high-dielectric and the silicon oxide film in series does not decrease by orders of magnitude as compared with the capacitance of the high-dielectric alone. Therefore, a sufficiently high gate driving capability can be ensured. Even in the above-described multilayer structure, unless the actual thickness t of the high-dielectric-constant gate insulating film is set to the value shown in Embodiment 1 or less, there is a merit of introducing a high-dielectric-constant material to the gate electrode side. Can not. Although not shown,
The same applies to a structure in which a low dielectric constant buffer layer is provided on the gate electrode side.

Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. Not limited. The scope of the present invention is shown by the description of the claims, and further includes all modifications within the meaning and scope equivalent to the description of the claims.

[0030]

According to the present invention, the film thickness can be made appropriate when a high dielectric constant material is used as the gate insulating film of the MOSFET. For this reason, it is possible to not only secure a large driving force due to an increase in the capacity of the gate, but also to strengthen the control of the channel by the gate and suppress the short channel effect. As a result, a normal transistor operation can be obtained even with a finer gate length, and the performance of a miniaturized MOSFET can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a configuration sectional view of an n-type MOSFET according to a first embodiment of the present invention.

FIG. 2 is a diagram showing characteristics of the n-type MOSFET shown in FIG. 1 and showing an effect of a gate length Lg on a threshold voltage Vth and a threshold voltage difference ΔVth.

FIG. 3 is a diagram for explaining a setting range of an actual film thickness of a high dielectric constant gate insulating film of the n-type MOSFET shown in FIG. 1;
FIG. 4 is a diagram showing the relationship between the actual thickness of a high-dielectric-constant gate insulating film.

FIG. 4 is a configuration sectional view of an n-type MOSFET according to a second embodiment of the present invention.

FIG. 5 is a configuration sectional view of a conventional n-type MOSFET.

[Explanation of symbols]

Reference Signs List 1 silicon substrate, 2 element isolation region, 3 p-type well, 4 high-permittivity gate insulating film, 5 gate electrode, 6
n-type extension, 7 sidewalls, 8 n
Source / drain, 9 silicide, 10 silicon oxide film (low dielectric constant buffer layer), 11 gate insulating film,
20 MOSFET.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshiyuki Oishi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Katsuomi Shiozawa 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Ryo Denki Co., Ltd. (72) Inventor Kohei Sugihara 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Sanishi Electric Co., Ltd. F term (reference) 5F040 DA01 DA06 DC01 DC10 EC01 EC13 ED01 ED03 ED04 ED05 EF02 EK01 FA03 FB01 FC02 FC19

Claims (10)

[Claims] 1. A MOS field-effect transistor formed on a silicon substrate, comprising: a gate insulating film located on the silicon substrate, the main material being a material other than a silicon oxide film; A material constituting the gate insulating film has a relative permittivity larger than that of silicon oxide, and a thickness of the gate insulating film is a thickness mainly including a silicon oxide film. A semiconductor device having a predetermined value or less so as to have a short channel effect equal to or less than a short channel effect in a MOSFET using a gate insulating film of 1.5 nm to 2.0 nm. 2. A MOS field-effect transistor formed on a silicon substrate, comprising: a gate insulating film located on the silicon substrate, the main material being a material other than a silicon oxide film; A material constituting the gate insulating film has a relative dielectric constant greater than that of silicon oxide, and a thickness of the gate insulating film, which is a lower limit gate for normal transistor operation. The thickness range of the gate insulating film is set so that the limit gate length, which is a long gate length, is equal to or less than that of a MOSFET using a silicon oxide film as a main material and having a thickness of 1.5 nm to 2.0 nm. Is set,
The semiconductor device according to claim 1. 3. The threshold voltage difference ΔVth obtained by subtracting the threshold voltage Vth in the saturation region from the threshold voltage Vlin.th in the linear region becomes a predetermined value. The limit gate length, which is the gate length, is set to be equal to or less than that of a MOSFET using a gate insulating film having a thickness of 1.5 nm to 2.0 nm and containing a silicon oxide film as a main material. 3. The semiconductor device according to 2. 4. The semiconductor device according to claim 3, wherein said limit gate length is a gate length at which said threshold voltage difference ΔVth becomes 50 mV. 5. The semiconductor device according to claim 1, wherein a main material constituting said gate insulating film is barium titanate (BaSrTiO ₃ ), and its thickness is 31 nm or less. 6. The semiconductor device according to claim 1, wherein a main material constituting said gate insulating film is titanium oxide (TiO ₂ ), and its thickness is 19 nm or less. 7. The gate insulating film is mainly composed of tantalum oxide (Ta ₂ O ₅ ) and zirconium oxide (Zr).
O ₂ ) or hafnium oxide (HfO ₂ ), the film thickness of which is 11 nm or less.
5. The semiconductor device according to any one of 4. 8. A main material constituting the gate insulating film,
Silicon nitride (Si _ThreeN_Four) And alumina (Al_TwoO_Three)
And the film thickness is 4 nm or less.
The semiconductor device according to claim 1, wherein 9. The semiconductor device according to claim 1, further comprising a silicon oxide film having a thickness of 0.5 nm or less in contact with said gate insulating film and said silicon substrate. 10. The semiconductor device according to claim 1, further comprising a silicon oxide film having a thickness of 0.5 nm or less in contact with said gate insulating film and said gate electrode.