JP2001273042A - Mos regulator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS regulator circuit with a high ratio of a ripple elimination. SOLUTION: The transistor 7 wired with the current mirror 5 is connected with what consists of a differential configuration of the MOS transistor 1, 2, the P channel MOS transistor pair comprising the current mirrors 4, 5, 6, the N channel MOS transistor pair, the output MOS transistor 9 and a resistor to decide an output voltage, the transistor 8 is connected with wired current mirror 5 and current mirror 6 and connected with a gate of the output transistor 9. Transistor 9 becomes the MOS regulator circuit with the high ratio of the ripple elimination with a reduced impedance, and expanded and improved frequency characteristic of transistor 9 because transistor 9 is connected with the transistor 7 and 8 through an emitter follower. Furthermore, a dynamic range of output transistor 9 can be expanded by connecting the transistor 16 with output transistor 9 and current mirror 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an M-type power supply.
It relates to an OS regulator circuit.

[0002]

2. Description of the Related Art In a conventional MOS regulator circuit, the gate of an output MOS is controlled by an active load or a fluctuation of a current output to constitute a MOS regulator circuit of a negative feedback amplifier.

[0003] Regarding a conventional MOS regulator circuit,
This will be described below with reference to the drawings. Figure 2 shows a conventional MO
5 shows an S regulator circuit. In FIG. 2, transistors 1 and 2 are N-channel transistors M constituting a differential amplifier.
The OS transistor 3 is a current source for supplying current to the differential amplifier, and 4 and 5 are N-channel MOS transistors 1 and 2
Current mirrors that respectively mirror the drain currents of
Reference numeral 6 denotes a current mirror for mirroring the current of the current mirror 4 and is connected to the current mirror 5. Reference numeral 9 denotes an output transistor for connecting a gate to the connected current mirror 5 and the current mirror 6. 10, 11 are resistors for determining the output voltage, 12 is an input terminal VIN for applying a reference voltage, and 13 is a terminal VOU for outputting an output voltage from the transistor 9.
T and 14 are a power supply voltage and 15 is a ground.

The operation of the MOS regulator circuit configured as described above will be described below. Input terminal 1
When the reference voltage VREF is applied to the differential amplifier 2, the differential amplifier performs feedback, and the gate voltage V
B becomes the same as the reference voltage VREF. When the gate voltage of the transistor 2 of the differential pair is determined, the resistors 10 and 11
The output voltage is obtained at the output terminal 13 by the ratio of.

If the output voltage decreases, the gate voltage of the transistor 2 also decreases. Therefore, a difference occurs in the gate voltage of the differential amplifier, and the current of the current mirror 5 decreases, while the current of the current mirror 6 increases. As a result, the gate voltage of the connected transistor 9 decreases, the drain current of the transistor 9 increases, feedback is applied to increase the output voltage, and the output is stabilized.

Conversely, when the output voltage rises, the gate voltage of transistor 2 rises. Therefore, a difference occurs in the gate voltage of the differential amplifier, and the current of the current mirror 5 increases, and conversely, the current of the current mirror 6 decreases. As a result, the gate voltage of the connected transistor 9 increases, the drain current of the transistor 9 decreases, feedback is applied to lower the output voltage, and the output is stabilized.

[0007]

When the conventional circuit (FIG. 2) is used, the frequency characteristics deteriorate due to the LPF characteristics determined by the parasitic capacitance of the gate of the output transistor. For this reason, there has been a problem that the amplification degree of the differential amplifier decreases and the ripple elimination rate decreases. An object of the present invention is to solve the above-mentioned conventional problems and to provide a MOS regulator circuit having a high ripple rejection ratio.

[0008]

In order to achieve this object, in a MOS regulator circuit according to the present invention, a first transistor having a gate to which a reference voltage is applied from an input terminal and a source of the first transistor are connected. A differential amplifier comprising a second transistor connected to the source, a source of the first and second transistors and a current source connected in common, and a current flowing through drains of the first transistor and the second transistor. As a current source, a first current mirror connected to the drain of the first transistor, and a second current mirror connected to the drain of the second transistor.
Current mirror, a third current mirror connected using the first current mirror as a current source, a third transistor connected to the second and third current mirrors by a gate, and a drain of the third transistor. Is grounded and the second
A fourth transistor mirror-connected to a current mirror of the third transistor, a drain of the fourth transistor is connected to a source of the third transistor, and a source and a gate of the third transistor are connected to a drain of the fourth transistor. The connected fifth transistor and the drain of the fifth transistor are connected to one end of the first resistor and the output terminal, and the other end of the first resistor is connected to the gate of the second transistor forming the differential amplifier. And one end of a second resistor, and the other end of the second resistor is grounded.

With this configuration, the transistor 7 serves as a current source for the source of the transistor 8 and has an emitter follower structure. Therefore, the input impedance of the output transistor 9 decreases, the frequency characteristic of the ripple elimination ratio improves, and the ripple elimination ratio of the output transistor 9 improves.

Although the above-described circuit configuration improves the ripple elimination rate, it has a problem that the dynamic range of the gate of the transistor 5 is narrowed. Therefore, the sixth transistor is connected to the source of the third transistor and the gate of the fifth transistor.
It is preferable that the drains of the transistors are connected, and the gate of the sixth transistor is connected to the third current mirror. With this configuration, the current of the gate of the fifth output transistor decreases, so that the dynamic range can be widened.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a MOS regulator circuit according to the embodiment.

In FIG. 1, reference numerals 1 and 2 denote N-channel MOS transistors constituting a differential amplifier, 3 denotes a current source for supplying a current to the differential amplifier, and 4 and 5 denote drain currents of the N-channel MOS transistors 1 and 2. The current mirror 6 is a current mirror for mirroring the current of the current mirror 4 and is connected to the current mirror 5. 7
Is a transistor that mirrors the current of the current mirror 5,
Reference numeral 8 denotes a connected current mirror 5 and a transistor for connecting a gate to the current mirror 6. 9 is an output transistor connected to transistor 7 and transistor 8;
11 is a resistor for determining an output voltage, 12 is an input terminal VIN for applying a reference voltage, 13 is a terminal VOUT for outputting an output voltage from the transistor 9, 14 is a power supply voltage, and 15 is a ground.

The operation of the MOS regulator circuit configured as described above will be described below. Input terminal 1
When the reference voltage VREF is applied to the differential pair 2, the differential amplifier performs feedback, and the gate voltage of the transistor 2 of the differential pair becomes the same as the reference voltage VREF. When the gate voltage of the transistor 2 of the differential pair is determined, an output voltage is obtained at the output terminal 13 by the ratio of the resistors 10 and 11.

If the output voltage drops, the gate voltage of transistor 2 also drops. Therefore, a difference occurs in the gate voltage of the differential amplifier, and the current of the current mirror 5 decreases, while the current of the current mirror 6 increases. As a result, the gate voltage of the connected transistor 9 decreases, the drain current of the transistor 9 increases, feedback is applied to increase the output voltage, and the output is stabilized.

Conversely, when the output voltage rises, the gate voltage of transistor 2 rises. Therefore, a difference occurs in the gate voltage of the differential amplifier, and the current of the current mirror 5 increases, and conversely, the current of the current mirror 6 decreases. As a result, the gate voltage of the connected transistor 9 increases, the drain current of the transistor 9 decreases, feedback is applied to lower the output voltage, and the output is stabilized.

FIG. 3 is a graph showing the frequency characteristics of the ripple elimination ratio of the conventional circuit and the circuit of the present invention. As can be seen from this figure, in the circuit configuration of the present invention, the output transistor 9 is in an emitter follower connection of the transistors 7 and 8, and the impedance is reduced, so that the frequency characteristic is extended and the ripple rejection is improved.

In the above circuit configuration, the gate dynamic range is narrowed by connecting the gates of the output transistor 9 to the transistors 7 and 8. Therefore, it is desirable to newly connect the transistor 16 to the gate of the transistor 9 and take measures to expand the dynamic range.

[0018]

As described above, according to the present invention, the current source and the MO for the emitter follower are connected to the gate of the output MOS transistor.
By connecting the S transistor, the frequency characteristics of the output MOS transistor can be extended, and a MOS regulator circuit having a high ripple elimination rate can be realized. At this time, the dynamic range of the gate of the output MOS transistor can be expanded by further connecting the MOS transistor connected to the current mirror to the gate of the output MOS transistor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a MOS regulator circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a MOS regulator circuit according to a conventional embodiment.

FIG. 3 is a graph showing a frequency characteristic of a ripple rejection ratio.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N-channel MOS transistor 2 N-channel MOS transistor 3 Current source 4 Current mirror 5 Current mirror 6 Current mirror 7 P-channel MOS transistor 8 P-channel MOS transistor 9 P-channel MOS transistor 10 Resistance 11 Resistance 12 Input terminal 13 Output terminal 14 Power supply voltage 15 Ground 16 N-channel MOS transistor

Continued on the front page F term (reference) 5H430 BB01 BB09 BB11 EE06 FF02 FF13 GG08 HH03 5J090 AA01 AA58 CA32 CA47 DN02 FA04 FA20 HA10 HA17 HA25 KA02 KA05 KA09 MA01 MA21 MN01 TA03 5J091 AA01 AA20 KA20 KA05 KA05 FA04 MA21 TA03

Claims (2)

[Claims] A first transistor to which a reference voltage is applied from an input terminal to a gate, a second transistor connected by a source to the source of the first transistor, and a source of the first and second transistors. And a current source connected in common with the first transistor and a second transistor connected to the drain of the first transistor, using a current flowing through the drains of the first transistor and the second transistor as current sources. One current mirror and the second current mirror
A second current mirror connected to the drain of the transistor, a third current mirror connected using the first current mirror as a current source, and a gate connected to the second and third current mirrors. A third transistor, a drain of the third transistor is grounded, a fourth transistor mirror-connected to the second current mirror, and a drain of the fourth transistor and a source of the third transistor. A fifth transistor connected by a gate to a source of the third transistor connected to a drain of the fourth transistor, and a drain of the fifth transistor is connected to one end of a first resistor and an output of the fifth transistor. And the other end of the first resistor and one end of the second resistor are connected to the gate of the second transistor that forms the differential amplifier. And, the second end of the resistor is MOS regulator circuit, characterized in that it consists of construction which is grounded. 2. A structure in which a drain of a sixth transistor is connected to a source of the third transistor and a gate of the fifth transistor, and a gate of the sixth transistor is connected to the third current mirror. 2. The MOS regulator circuit according to claim 1, comprising: