JP2001267559A5

JP2001267559A5 -

Info

Publication number: JP2001267559A5
Application number: JP2000074751A
Authority: JP
Filing date: 2000-03-16
Publication date: 2004-12-16
Anticipated expiration: 2020-03-16

Description

【０００６】
この例は、例えばＮＡＮＤゲートを構成するＣＭＯＳトランジスタ回路Ｑ３は、低閾値電圧トランジスタで構成し、その低閾値電圧トランジスタ回路に対して、電流供給用の高閾値電圧トランジスタＱ１，Ｑ２を設ける。そして、活性動作状態では、電流供給用トランジスタＱ１，Ｑ２を導通状態にし、電源VDDから電源用大容量Ｃ１０，Ｃ２０を介して低閾値電圧トランジスタ回路Ｑ３に電流を供給する。その場合、トランジスタ回路Ｑ３は、低閾値電圧であるので高速動作が可能である。一方、非活性状態（低消費電力状態）では、電流供給用トランジスタＱ１，Ｑ２に制御信号ＳＬ=Hレベル、／ＳＬ＝Ｌレベルをそれぞれ印加して、トランジスタＱ１，Ｑ２を非導通状態にする。これらのトランジスタＱ１，Ｑ２は高い閾値電圧であるので、完全に非導通にしてオフリーク電流をなくすことができるので、低閾値電圧トランジスタ回路Ｑ３がオフリーク電流の発生により電流を供給することはなく、内部トランジスタ回路Ｑ３の電力消費を防止することができる。また、特開平１１−２６１３８２号には、発振周波数を制御する別のトランジスタを設けることなく小さな回路面積で済む半導体発振回路が開示される。スタンバイ時には、半導体発振回路に含まれるインバーター回路を構成するＰＭＯＳトランジスタとＮＭＯＳトランジスタにそれぞれ印加するコントロール電圧を制御することで、少なくとも一方のトランジスタをオフ状態にし、半導体発振回路の発振を停止させ、低消費電力が実現されることが記載されている。 [0006]
In this example, for example, a CMOS transistor circuit Q3 constituting a NAND gate is constituted by low threshold voltage transistors, and high threshold voltage transistors Q1 and Q2 for current supply are provided for the low threshold voltage transistor circuit. Then, in the active operation state, the current supply transistors Q1 and Q2 are turned on, and a current is supplied from the power supply VDD to the low threshold voltage transistor circuit Q3 via the large capacity C10 and C20 for power supply. In that case, the transistor circuit Q3 can operate at high speed because it has a low threshold voltage. On the other hand, in the inactive state (low power consumption state), control signals SL = H level and / SL = L level are applied to current supply transistors Q1 and Q2, respectively, to render transistors Q1 and Q2 nonconductive. Since these transistors Q1 and Q2 have high threshold voltages, they can be completely turned off to eliminate the off leak current. Therefore, the low threshold voltage transistor circuit Q3 does not supply current due to the occurrence of off leak current, and the internal Power consumption of the transistor circuit Q3 can be prevented. Japanese Patent Application Laid-Open No. 11-261382 discloses a semiconductor oscillation circuit requiring a small circuit area without providing another transistor for controlling the oscillation frequency. At the time of standby, at least one of the transistors is turned off by controlling the control voltage applied to each of the PMOS transistor and the NMOS transistor that constitute the inverter circuit included in the semiconductor oscillation circuit to stop the oscillation of the semiconductor oscillation circuit. It is described that power consumption is realized.

Claims

In the MOS transistor formed on the surface of the semiconductor substrate,
Source and drain regions formed on the surface of the semiconductor substrate;
A floating gate provided between the source and drain regions on the semiconductor substrate via an insulating film;
The floating gate has an input gate provided through an insulating film and a plurality of threshold control gates,
The ratio of capacitances between the plurality of threshold control gates and the floating gate is set to a predetermined ratio,
The activation state is set to a first threshold voltage for the input gate by applying a first voltage to the threshold control gate, and the second state is applied to the threshold control gate for a non-activation state. And a second threshold voltage higher than the first threshold voltage with respect to the input gate.

In the MOS transistor formed on the surface of the semiconductor substrate,
Source and drain regions formed on the surface of the semiconductor substrate;
A first gate provided between the source and drain regions on the semiconductor substrate via an insulating film;
An input gate provided via a capacitance in the first gate and a threshold control gate;
The activation state is set to a first threshold voltage for the input gate by applying a first voltage to the threshold control gate, and the second state is applied to the threshold control gate for a non-activation state. And a second threshold voltage higher than the first threshold voltage with respect to the input gate.

In claim 2 ,
The capacitor is an impurity region formed on the surface of the semiconductor substrate and constituting the input gate and the threshold control gate, and a second gate connected to the first gate and provided on the impurity region via an insulating film. And a MOS transistor characterized by:

In claim 2 ,
A plurality of the threshold control gates are provided, and a ratio of the capacitances of the plurality of threshold control gates is set to a predetermined ratio.

In claim 1 or 2 ,
The MOS transistor is an N-channel transistor and a P-channel transistor connected between two power supplies, and a low level and a high level voltage as the first voltage are respectively supplied to the threshold control gates of the second and third transistors. A high level and low level voltage are respectively applied as voltages, and an input signal is commonly supplied to the input gate.

In the MOS transistor formed on the surface of the semiconductor substrate,
Source and drain regions formed on the surface of the semiconductor substrate;
A floating gate provided between the source and drain regions on the semiconductor substrate via an insulating film;
And an input gate provided on the floating gate via an insulating film,
2. A MOS transistor for high-speed operation, wherein the floating gate and the input gate are short-circuited, and for a low power consumption operation transistor, the floating gate and the input gate are isolated.