JP2001267462A - Chip supporting substrate for semiconductor package, semiconductor device and method for manufacturing the same - Google Patents
Chip supporting substrate for semiconductor package, semiconductor device and method for manufacturing the sameInfo
- Publication number
- JP2001267462A JP2001267462A JP2000081674A JP2000081674A JP2001267462A JP 2001267462 A JP2001267462 A JP 2001267462A JP 2000081674 A JP2000081674 A JP 2000081674A JP 2000081674 A JP2000081674 A JP 2000081674A JP 2001267462 A JP2001267462 A JP 2001267462A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- chip
- semiconductor
- supporting substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体ハ゜ッケーシ゛用チ
ップ支持基板、半導体装置及び半導体装置の製造方法に
関する。[0001] 1. Field of the Invention [0002] The present invention relates to a chip support substrate for a semiconductor package, a semiconductor device, and a method for manufacturing a semiconductor device.
【０００２】[0002]
【従来の技術】半導体の集積度が向上するに従い、入出
力端子数が増加している。従って、多くの入出力端子数
を有する半導体パッケージが必要になった。一般に、入
出力端子はパッケージの周辺に一列に配置するタイプ
と、周辺だけではなく内部まで多列に配置するタイプが
ある。前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋ
ａｇｅ）が代表的である。これを多端子化する場合は、
端子ピッチを縮小することが必要であるが、０．５ｍｍ
ピッチ以下の領域では、配線板との接続に高度な技術が
必要になる。後者のアレイタイプは比較的大きなピッチ
で端子配列が可能なため、多ピン化に適している。従
来、アレイタイプは接続ピンを有するＰＧＡ（Ｐｉｎ
Ｇｒｉｄ Ａｒｒａｙ）が一般的であるが、配線板との
接続は挿入型となり、表面実装には適していない。この
ため、表面実装可能なＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒ
ｒａｙ）と称するパッケージが開発されている。2. Description of the Related Art As the degree of integration of semiconductors increases, the number of input / output terminals increases. Therefore, a semiconductor package having a large number of input / output terminals is required. In general, there are a type in which input / output terminals are arranged in a line around the package and a type in which the input / output terminals are arranged in multiple lines not only around the periphery but also inside. The former is a QFP (Quad Flat Pack)
age) is typical. If you want to use multiple terminals,
It is necessary to reduce the terminal pitch, but 0.5mm
In the area below the pitch, advanced technology is required for connection with the wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged at a relatively large pitch. Conventionally, an array type has a PGA (Pin) having connection pins.
Grid Array) is generally used, but the connection with the wiring board is of an insertion type and is not suitable for surface mounting. For this reason, a surface mountable BGA (Ball Grid Ar
ray) has been developed.
【０００３】一方、電子機器の小型化に伴って、パッケ
ージサイズの更なる小型化の要求が強くなってきた。こ
の小型化に対応するものとして、半導体チップとほぼ同
等サイズの、いわゆるＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ／Ｓ
ｃａｌｅ Ｐａｃｋａｇｅ）が提案されている。これ
は、半導体チップの周辺部でなく、実装領域内に外部配
線基板との接続部を有するパッケージである。具体例と
しては、パンプ付きポリイミドフィルムを半導体チップ
の表面に接着し、チップと金リード線により電気的接続
を図った後、エポキシ樹脂等をポッティングして封止し
たもの、（ＮＩＫＫＥＩ ＭＡＴＥＲＩＡＬＳ ＆ ＴＥ
ＣＨＮＯＬＯＧＹ ９４．４、Ｎｏ．１４０、ｐ１８−
１９）や、仮基板上でトランスファーモールドしたもの
（Ｓｍａｌｌｅｓｔ Ｆｌｉｐ−Ｃｈｉｐ−Ｌｉｋｅ Ｐ
ａｃｋａｇｅ ＣＳＰ、Ｔｈｅ Ｓｅｃｏｎｄ ＶＬＳＩ
Ｐａｃｋａｇｉｎｇ Ｗｏｒｋｓｈｏｐ ｏｆ Ｊａｐａ
ｎ、ｐ４６−５０、１９９４）等がある。このほか外部
配線基板との接続部を半導体チップの周辺部に配してあ
るが接続端子のピッチが狭い、小型のＦ−ＢＧＡ（Ｆｉ
ｎｅ Ｐｉｔｃｈ Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）も開
発されている。[0003] On the other hand, with the miniaturization of electronic equipment, the demand for further miniaturization of the package size has increased. As a countermeasure for this miniaturization, a so-called CSP (Chip Size / S) having almost the same size as a semiconductor chip is used.
call package) has been proposed. This is a package having a connection portion with an external wiring board in a mounting region, not in a peripheral portion of a semiconductor chip. As a specific example, a polyimide film with a pump is adhered to the surface of a semiconductor chip, an electrical connection is made between the chip and a gold lead wire, and then an epoxy resin or the like is sealed by potting. (NIKKEI MATERIALS & TE)
CHNOLOGY 94.4, No. 140, p18-
19) and those obtained by transfer molding on a temporary substrate (Smallest Flip-Chip-Like P)
package CSP, The Second VLSI
Packaging Workshop of Japan
n, p46-50, 1994). In addition, a small F-BGA (Fi
Ne Pitch Ball Grid Array) has also been developed.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来提
案されている半導体パッケージの多くは、小型で高集積
度化に対応でき、かつ、パッケージクラックを防止し信
頼性に優れしかも生産性に優れるものではない。本発明
は、パッケージクラックを防止し信頼性に優れる小型の
半導体パッケージの製造を可能とする半導体パッケージ
用チップ支持基板、半導体装置及び半導体装置の製造方
法を提供するものである。However, most of the semiconductor packages proposed in the prior art are small in size, capable of coping with high integration, prevented from cracking the package, and excellent in reliability and productivity. Absent. SUMMARY OF THE INVENTION The present invention provides a semiconductor package chip supporting substrate, a semiconductor device, and a method of manufacturing a semiconductor device that can manufacture a small semiconductor package that prevents package cracks and has excellent reliability.
【０００５】[0005]
【課題を解決するための手段】上記問題点を解決するた
め本発明は、 A．絶縁性支持基板の一表面には複数の配線が形成され
ており、前記配線は少なくとも半導体チップ電極と接続
するインナー接続部及び半導体チップ搭載領域部を有す
るものであり、 Ｂ．前記絶縁性支持基板には、前記絶縁性支持基板の前
記配線が形成されている箇所であって前記インナー接続
部と導通するアウター接続部が設けられる箇所に、開口
が設けられており、 Ｃ．前記絶縁性支持基板の前記半導体チップ搭載領域内
における前記配線相互間に、少なくとも１個の貫通穴が
設けられており、 Ｄ．前記絶縁性支持基板の前記半導体チップ搭載領域内
における前記配線相互間及び半導体チップが搭載される
箇所に、コア材が耐熱性樹脂からなる多孔質フィルムで
あり前記コア材の両面に接着剤層が形成された両面接着
フィルムが載置形成されていることを特徴とするもので
ある。本発明の半導体装置は、前記半導体パッケージ用
チップ支持基板と、前記支持基板の両面接着フィルムの
面に搭載された半導体チップと、前記半導体チップを封
止する樹脂封止を備えることを特徴とするものである。
本発明の半導体装置の製造方法は、半導体パッケージ用
チップ支持基板の両面接着フィルムの面に半導体チップ
を接着する工程、半導体チップ電極を配線のインナー接
続部とワイヤボンディングにより接続する工程、半導体
チップを樹脂封止する工程、前記支持基板の開口にイン
ナー接続部と導通するアウター接続部を設ける工程を備
える。To solve the above problems, the present invention provides: B. A plurality of wirings are formed on one surface of the insulating support substrate, and the wirings have at least an inner connection part connected to a semiconductor chip electrode and a semiconductor chip mounting area part; B. an opening is provided in the insulating support substrate at a position where the wiring is formed on the insulating support substrate and at a position where an outer connection portion that is electrically connected to the inner connection portion is provided; B. at least one through hole is provided between the wirings in the semiconductor chip mounting region of the insulating support substrate; A core material is a porous film made of a heat-resistant resin, and an adhesive layer is provided on both surfaces of the core material, between the wirings and at a location where the semiconductor chip is mounted in the semiconductor chip mounting region of the insulating support substrate. The formed double-sided adhesive film is mounted and formed. The semiconductor device according to the present invention includes the semiconductor package chip support substrate, a semiconductor chip mounted on a surface of a double-sided adhesive film of the support substrate, and a resin seal for sealing the semiconductor chip. Things.
The method of manufacturing a semiconductor device according to the present invention includes a step of bonding a semiconductor chip to a surface of a double-sided adhesive film of a chip supporting substrate for a semiconductor package, a step of connecting a semiconductor chip electrode to an inner connection portion of a wiring by wire bonding, and a step of connecting the semiconductor chip. The method includes a step of sealing with a resin, and a step of providing an outer connection portion that is electrically connected to the inner connection portion in the opening of the support substrate.
【０００６】[0006]
【発明の実施の形態】絶縁性支持基板としては、ポリイ
ミド樹脂、エポキシ樹脂、ポリアミドイミド樹脂等のプ
ラスチックフィルム、ポリイミド樹脂、エポキシ樹脂、
ポリアミドイミド、ビスマレイミド・トリアジン樹脂等
のプラスチックをガラス織布・不織布等の基材に含浸・
硬化したもの等が使用できる。絶縁性支持基板の一表面
に複数の配線を形成するには、銅箔をエッチングする方
法、所定の箇所に銅めっきをする方法、それらを併用す
る方法等が使用できる。絶縁性支持基板に外部接続部、
貫通穴などの開口を設けるには、ドリル加工やパンチン
グなどの機械加工、エキシマレ−ザや炭酸ガスレ−ザな
どのレ−ザ加工等により行うことができる。また、接着
性のある絶縁基材等に開口部をあらかじめ設け、それを
銅箔等の配線形成用金属箔と張り合わせる方法、銅箔付
きまたはあらかじめ配線が形成された絶縁基材に開口部
を設ける方法、それらを併用する等が可能である。イン
ナー接続部と導通するアウター接続部は、絶縁性支持基
板開口部に、はんだボール、めっき等によりバンプ等を
形成することにより作製することができる。これは外部
の基板等に接続される。半導体チップ搭載領域部は、で
きるだけ均一に配線パターンが配置されていることが好
ましい。具体的には、半導体チップ搭載領域部の絶縁性
支持基板には、任意の点を含む半径１ミリメートルの範
囲に少なくとも１つ以上の配線が形成されているように
配線が形成されていることが好ましい。しかし、配線だ
けでこのような条件が満足できない場合は、別に独立の
ダミーパターン、位置合わせ用マーク、文字・符合など
の金属パターンを設けてもよい。DESCRIPTION OF THE PREFERRED EMBODIMENTS Insulating support substrates include plastic films such as polyimide resin, epoxy resin and polyamide-imide resin, polyimide resin, epoxy resin, and the like.
Plastics such as polyamide imide, bismaleimide and triazine resin are impregnated into glass woven and non-woven fabric substrates.
A cured product can be used. In order to form a plurality of wirings on one surface of the insulating support substrate, a method of etching a copper foil, a method of plating a predetermined portion with copper, a method of using them in combination, or the like can be used. External connection part on insulating support substrate,
An opening such as a through hole can be provided by mechanical processing such as drilling or punching, or laser processing such as an excimer laser or a carbon dioxide laser. Also, a method is provided in which an opening is provided in advance on an adhesive insulating substrate or the like, and the opening is bonded to a metal foil for forming a wiring such as a copper foil. It is possible to provide them, use them together, or the like. The outer connection portion that is electrically connected to the inner connection portion can be manufactured by forming a bump or the like on the opening of the insulating support substrate by solder ball, plating, or the like. This is connected to an external substrate or the like. It is preferable that the wiring patterns are arranged as uniformly as possible in the semiconductor chip mounting area. Specifically, the wires are formed on the insulating support substrate in the semiconductor chip mounting region so that at least one wire is formed in a range of 1 mm in radius including an arbitrary point. preferable. However, when such a condition cannot be satisfied only by the wiring, an independent dummy pattern, a positioning mark, a metal pattern such as a character or a code may be provided separately.
【０００７】両面接着フィルムのコア材である多孔質フ
ィルムの気孔率は５〜９５％であることが好ましい。５
％未満であると連続した気孔が得にくくなり、リフロー
時の蒸気圧を低減する効果が小さくなる。また、９５％
を超えると多孔質フィルムの機械的強度が低下する。多
孔質フィルムの透湿係数は５００ｇ／（m2・日）以上で
あることが好ましい。透湿係数が５００ｇ／ｍ2／日未
満であると吸湿した水分が加熱時に脱湿しにくく、リフ
ロークラックを引き起す恐れがある。反対に、透湿係数
を５００ｇ／ｍ2／日以上とすることで、比較的大きな
吸水率、例えば３〜５重量％である多孔質フィルムおよ
び／または接着剤層が使用できるようになる。さらに２
５℃での貯蔵弾性率が１０ＭＰａ以上であることが好ま
しい。また、前記多孔質フィルムを形成する耐熱性樹脂
としては、ポリエーテルサルフォン樹脂、ポリイミド樹
脂、ポリアミド樹脂、ポリアミドイミド樹脂、ポリエー
テルイミド樹脂、ポリエステル樹脂、ポリサルフォン樹
脂、ポリエーテルエーテルケトン樹脂、エポキシ樹脂、
アクリル樹脂、ポリウレタン樹脂、ポリテトラフルオロ
エチレン樹脂等の樹脂が好適である。また、前記耐熱性
樹脂の吸水率は０．１〜５重量％であることが好まし
い。吸水率が０．１重量％未満の耐熱性樹脂は接着剤層
との接着力が低い場合がある。吸水率が５重量％を超え
るとリフロー工程で加熱された場合の脱湿量が上記透湿
量を上回り、リフロークラックを引き起す恐れがある。
多孔質フィルムの作製方法は、特に制限するものではな
く、相転換法や延伸法、溶融法、焼結法など公知の分離
膜の製造方法を用いることができる。また、繊維状の樹
脂を漉いた不織布や織った織布も多孔質フィルムとして
使用可能である。The porosity of the porous film as the core material of the double-sided adhesive film is preferably 5 to 95%. 5
%, It is difficult to obtain continuous pores, and the effect of reducing the vapor pressure during reflow is reduced. 95%
If it exceeds, the mechanical strength of the porous film decreases. The moisture permeability coefficient of the porous film is preferably 500 g / (m 2 · day) or more. If the moisture permeability coefficient is less than 500 g / m 2 / day, the absorbed moisture is less likely to be dehumidified during heating, which may cause a reflow crack. Conversely, by setting the moisture permeability coefficient to 500 g / m 2 / day or more, it becomes possible to use a porous film and / or an adhesive layer having a relatively large water absorption, for example, 3 to 5% by weight. 2 more
The storage elastic modulus at 5 ° C. is preferably 10 MPa or more. The heat-resistant resin forming the porous film includes polyether sulfone resin, polyimide resin, polyamide resin, polyamideimide resin, polyetherimide resin, polyester resin, polysulfone resin, polyetheretherketone resin, and epoxy resin. ,
Resins such as acrylic resin, polyurethane resin, and polytetrafluoroethylene resin are preferred. Further, the water absorption of the heat resistant resin is preferably 0.1 to 5% by weight. A heat-resistant resin having a water absorption of less than 0.1% by weight may have low adhesive strength to the adhesive layer. If the water absorption exceeds 5% by weight, the amount of dehumidification when heated in the reflow step exceeds the above-mentioned amount of moisture transmission, which may cause reflow cracks.
The method for producing the porous film is not particularly limited, and a known method for producing a separation membrane such as a phase inversion method, a stretching method, a melting method, and a sintering method can be used. Further, a nonwoven fabric or a woven fabric made of a fibrous resin can also be used as the porous film.
【０００８】両面接着フィルムのコア材である多孔質フ
ィルムの両面に形成される接着剤層としては熱硬化性樹
脂組成物であることが好ましく、その硬化物の貯蔵弾性
率が２５℃で１０〜２０００MPａ、２６０℃で３〜５０
ＭＰａであることが好ましい。貯蔵弾性率が２５℃で２
０００ＭＰａを超えるものと２６０℃で５０ＭＰａを超
えるものでは、半導体チップと半導体パッケージ用チッ
プ支持基板との熱膨張係数の差によって発生する熱応力
を緩和させる効果が小さくなり、剥離やクラックを発生
する恐れがある。一方、貯蔵弾性率が２５℃で１０ＭＰ
ａ未満では両面接着フィルムの取扱性や接着剤層の厚さ
精度が悪くなり、２６０℃で３ＭＰａ未満ではリフロー
クラックを発生しやすくなる。このような熱硬化性樹脂
組成物としては、エポキシ樹脂及びその硬化剤、エポキ
シ基含有アクリル系共重合体、硬化促進剤を含む組成物
が好適である。エポキシ樹脂としては、二官能以上で、
好ましくは分子量が５０００未満、より好ましくは分子
量３０００未満のものが使用できる。硬化剤としては、
アミン類、ポリアミド、酸無水物、ポリスルフィッド、
三弗化ほう素及びフェノール性水酸基を１分子中に２個
以上有する化合物が使用できる。エポキシ基含有アクリ
ル系共重合体はエポキシ当量が２０００〜１５０００ｇ
／ｍｏｌでガラス転移温度（Ｔｇ）が−１０℃以上でか
つ重量平均分子量が８０００００以上である共重合体で
あることが好ましい。硬化促進剤としてはイミダゾール
類を用いることが好ましい。The adhesive layer formed on both sides of the porous film as the core material of the double-sided adhesive film is preferably a thermosetting resin composition, and the cured product has a storage elastic modulus of 10 to 10 at 25 ° C. 2000MPa, 3-50 at 260 ° C
It is preferably MPa. Storage modulus is 2 at 25 ° C
In the case of exceeding 000 MPa and the case of exceeding 50 MPa at 260 ° C., the effect of relieving the thermal stress caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the chip supporting substrate for the semiconductor package becomes small, and there is a possibility that peeling or cracking may occur. There is. On the other hand, the storage elastic modulus is 10MP at 25 ° C.
If it is less than a, the handleability of the double-sided adhesive film and the thickness accuracy of the adhesive layer will be poor, and if it is less than 3 MPa at 260 ° C., reflow cracks will easily occur. As such a thermosetting resin composition, a composition containing an epoxy resin and its curing agent, an epoxy group-containing acrylic copolymer, and a curing accelerator is preferable. As an epoxy resin, it is bifunctional or more,
Preferably, those having a molecular weight of less than 5000, more preferably less than 3000 can be used. As a curing agent,
Amines, polyamides, acid anhydrides, polysulfides,
Compounds having two or more boron trifluoride and phenolic hydroxyl group in one molecule can be used. The epoxy group-containing acrylic copolymer has an epoxy equivalent of 2000 to 15000 g.
/ Mol and a glass transition temperature (Tg) of −10 ° C. or higher and a weight average molecular weight of 800,000 or higher are preferred. It is preferable to use imidazoles as the curing accelerator.
【０００９】接着剤層には、接着剤層の取扱い性の向
上、熱伝導性の向上、溶融粘度の調整、チクソトロピッ
ク性の付与などを目的として無機フィラーを配合するこ
とができる。無機フィラーとしては、水酸化アルミニウ
ム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネ
シウム、ケイ酸カルシウム、ケイ酸マグネシウム、酸化
カルシウム、酸化マグネシウム、アルミナ粉末、窒化ア
ルミニウム粉末、ほう酸アルミウイスカ、窒化ホウ素粉
末、結晶性シリカ、非晶性シリカなどが挙げられる。熱
伝導性向上のためには、アルミナ、窒化アルミニウム、
窒化ホウ素、結晶性シリカ、非晶性シリカ等が好まし
い。溶融粘度の調整やチクソトロピック性の付与の目的
には、水酸化アルミニウム、水酸化マグネシウム、炭酸
カルシウム、炭酸マグネシウム、ケイ酸カルシウム、ケ
イ酸マグネシウム、酸化カルシウム、酸化マグネシウ
ム、アルミナ、結晶性シリカ、非晶性シリカ等が好まし
い。An inorganic filler can be added to the adhesive layer for the purpose of improving the handleability of the adhesive layer, improving the thermal conductivity, adjusting the melt viscosity, imparting thixotropic properties, and the like. As inorganic fillers, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina powder, aluminum nitride powder, aluminum borate whisker, boron nitride powder, crystalline Silica and amorphous silica. Alumina, aluminum nitride,
Boron nitride, crystalline silica, amorphous silica and the like are preferred. For the purpose of adjusting melt viscosity and imparting thixotropic properties, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, crystalline silica, Crystalline silica and the like are preferred.
【００１０】異種材料間の界面結合をよくするためにカ
ップリング剤を配合することもでき、特にシランカップ
リング剤が好適である。さらに、イオン性不純物を吸着
して吸湿時の絶縁信頼性をよくする目的でイオン捕捉剤
を配合することができる。イオン捕捉剤としては、銅が
イオン化して溶け出すのを防止するため銅害防止剤とし
て知られる化合物、例えばトリアジンチオール化合物、
ビスフェノール系還元剤がある。ビスフェノール系還元
剤としては、２，２’−メチレン−ビス（４−メチル−
６−第３−ブチルフェノール）、４，４’−チオ−ビス
（３−メチル−６−第３−ブチルフェノール）等が挙げ
られる。また、無機イオン吸着剤としては、ジルコニウ
ム系化合物、アンチモンビスマス系化合物、マグネシウ
ムアルミニウム系化合物等が挙げられる。In order to improve the interfacial bonding between different kinds of materials, a coupling agent can be blended, and a silane coupling agent is particularly preferable. Further, an ion scavenger can be blended for the purpose of adsorbing ionic impurities and improving insulation reliability during moisture absorption. As an ion scavenger, a compound known as a copper harm inhibitor to prevent copper from being ionized and dissolved, for example, a triazine thiol compound,
There is a bisphenol-based reducing agent. As the bisphenol-based reducing agent, 2,2′-methylene-bis (4-methyl-
6-tert-butylphenol), 4,4'-thio-bis (3-methyl-6-tert-butylphenol) and the like. Examples of the inorganic ion adsorbent include a zirconium compound, an antimony bismuth compound, and a magnesium aluminum compound.
【００１１】多孔質フィルムをコア材としその両面に接
着剤層を形成する方法は特に制限するものではない。例
えば、ラミネート、コーティング、ディッピングなどの
公知の方法で形成することができる。好ましい方法とし
てはラミネートとコーティングであり、両面接着フィル
ムの厚さを精度よく制御することが可能である。特にラ
ミネートは予め接着剤層のみを形成しておくことができ
るため量産性にすぐれる。このときの多孔質フィルムと
接着剤層の厚さは特に制限するものではないが、これら
を合わせた両面接着フィルムのトータルの厚さは１０〜
５００μｍが好ましい。１０μｍ以下では熱応力の緩和
効果が小さくなり剥離やクラックを生ずる恐れがある。
５００μｍを超えるとリードまたはワイヤボンディング
がしづらくなり、また半導体装置の厚さが厚くなる。こ
れらから、さらに好ましくは５０〜２５０μｍである。The method for forming the adhesive layer on both sides of the porous film as the core material is not particularly limited. For example, it can be formed by a known method such as lamination, coating, and dipping. Preferred methods are lamination and coating, and it is possible to precisely control the thickness of the double-sided adhesive film. In particular, the laminate is excellent in mass productivity because only the adhesive layer can be formed in advance. The thickness of the porous film and the adhesive layer at this time is not particularly limited, but the total thickness of the double-sided adhesive film combining these is 10 to
500 μm is preferred. If it is 10 μm or less, the effect of relaxing the thermal stress is reduced, and there is a possibility that peeling or cracking may occur.
If the thickness exceeds 500 μm, lead or wire bonding becomes difficult, and the thickness of the semiconductor device increases. From these, it is more preferably 50 to 250 μm.
【００１２】多孔質フィルムの両面に接着剤層をラミネ
ートして形成する場合の接着剤層は、予め接着剤組成物
の各成分を溶剤に溶解ないし分散してワニスとしキャリ
アフィルム上に塗布、加熱し溶剤を除去することにより
得られる。キャリアフィルムとしては、ポリテトラフル
オロエチレンフィルム、ポリエチレンテレフタレートフ
ィルム、離型処理したポリエチレンテレフタレートフィ
ルム、ポリエチレンフィルム、ポリプロピレンフィル
ム、ポリメチルペンテンフィルム、ポリイミドフィルム
などのプラスチックフィルムが使用できる。キャリアフ
ィルムはコア材へのラミネート前に剥離してもよいし、
キャリアフィルムとともにコア材にラミネートし使用時
に剥離することもできる。When the adhesive layer is formed by laminating an adhesive layer on both sides of the porous film, the components of the adhesive composition are dissolved or dispersed in a solvent in advance to form a varnish, which is coated on a carrier film and heated. It is obtained by removing the solvent. As the carrier film, a plastic film such as a polytetrafluoroethylene film, a polyethylene terephthalate film, a release-treated polyethylene terephthalate film, a polyethylene film, a polypropylene film, a polymethylpentene film, and a polyimide film can be used. The carrier film may be peeled off before lamination to the core material,
It can also be laminated on a core material together with a carrier film and peeled off at the time of use.
【００１３】ワニス化の溶剤は、比較的低沸点の、メチ
ルエチルケトン、アセトン、メチルイソブチルケトン、
２−エトキシエタノール、トルエン、ブチルセルソル
ブ、メタノール、エタノール、２−メトキシエタノール
などを用いるのが好ましい。また、塗膜性を向上するな
どの目的で、高沸点溶剤を加えても良い。高沸点溶剤と
しては、ジメチルアセトアミド、ジメチルホルムアミ
ド、メチルピロリドン、シクロヘキサノンなどが挙げら
れる。ワニスの製造は、無機フィラーの分散を考慮した
場合には、らいかい機、３本ロール及びビーズミル等に
より、またこれらを組み合わせて行なうことができる。
フィラーと低分子量物をあらかじめ混合した後、高分子
量物を配合することにより、混合に要する時間を短縮す
ることも可能となる。また、ワニスとした後、真空脱気
によりワニス中の気泡を除去することが好ましい。多孔
質フィルムの両面に接着剤層をコーティングにより形成
する場合は、このワニスをそのまま用いることができ
る。The varnishing solvent may be a relatively low boiling point methyl ethyl ketone, acetone, methyl isobutyl ketone,
It is preferable to use 2-ethoxyethanol, toluene, butyl cellosolve, methanol, ethanol, 2-methoxyethanol and the like. Further, a high boiling point solvent may be added for the purpose of improving the coating properties. Examples of the high boiling point solvent include dimethylacetamide, dimethylformamide, methylpyrrolidone, cyclohexanone and the like. The production of the varnish can be carried out by a mill, a three-roll mill, a bead mill or the like, or a combination thereof, in consideration of the dispersion of the inorganic filler.
By mixing the filler and the low molecular weight material in advance and then blending the high molecular weight material, the time required for mixing can also be reduced. After the varnish is formed, it is preferable to remove bubbles in the varnish by vacuum degassing. When an adhesive layer is formed on both surfaces of the porous film by coating, the varnish can be used as it is.
【００１４】両面接着フィルムの表面すなわち接着剤層
の表面は凹凸形状をなしていることが好ましい。表面が
凹凸であると半導体チップまたは半導体パッケージ用チ
ップ支持基板に貼り付ける際に、空気の巻き込みによる
気泡（ボイド）を低減することができる。このような凹
凸形状を接着剤層表面に形成する方法は特に限定しない
が、例えば上記キャリアフィルムとして凸凹形状を有す
るフィルム上に接着剤層を成形することによりそのレプ
リカとして凹凸を有する接着剤層を得ることができる。It is preferable that the surface of the double-sided adhesive film, that is, the surface of the adhesive layer has an uneven shape. When the surface is uneven, air bubbles (voids) due to entrainment of air can be reduced when affixed to a semiconductor chip or a chip supporting substrate for a semiconductor package. The method of forming such an uneven shape on the surface of the adhesive layer is not particularly limited.For example, by forming the adhesive layer on a film having an uneven shape as the carrier film, the adhesive layer having the unevenness as a replica thereof is formed. Obtainable.
【００１５】本発明の半導体パッケージ用チップ支持基
板を使用した半導体装置は、前記絶縁性支持基板の前記
半導体チップ搭載領域内における前記配線相互間及び半
導体チップが搭載される箇所に前記両面接着フィルムが
載置形成される。さらに両面接着フィルムの面に半導体
チップが搭載され、前記半導体チップを樹脂で封止した
構成である。In the semiconductor device using the chip supporting substrate for a semiconductor package of the present invention, the double-sided adhesive film is provided between the wirings and at a position where the semiconductor chip is mounted in the semiconductor chip mounting area of the insulating supporting substrate. It is mounted and formed. Further, a semiconductor chip is mounted on the surface of the double-sided adhesive film, and the semiconductor chip is sealed with a resin.
【００１６】本発明の半導体パッケージ用チップ支持基
板を使用して半導体装置を製造するには、本発明の半導
体パッケージ用チップ支持基板の前記半導体チップ搭載
領域内における前記配線相互間及び半導体チップが搭載
される箇所に両面接着フィルムを、熱圧着機等により加
熱しながら圧力を加えて接着する。このときの温度は１
３０〜２００℃、圧力は０．１５〜０．３ＭＰａである
ことが好ましいが、より好ましくは温度１３０〜１５０
℃、圧力０．２〜０．２５ＭＰａである。露出している
配線には、無電解ニッケルめっき及び無電解金めっきを
順次施すことが好ましく、前記無電解ニッケルめっき及
び無電解金めっきは、両面接着フィルムを前記半導体パ
ッケージ用チップ支持基板に転載形成する前であっても
後であってもよい。また、無電解めっきではなく、電解
めっきを使用してもよい。さらに前記両面接着フィルム
の面に半導体チップを接着し、半導体チップ電極を前記
支持基板のインナー接続部とワイヤーボンディング等に
より接続し、半導体チップの少なくとも半導体チップ電
極面を樹脂封止し、前記支持基板に設けられた開口にイ
ンナー接続部と導通するアウター接続部を設けることに
より半導体パッケージを製造することができる。In order to manufacture a semiconductor device using the semiconductor package chip supporting substrate of the present invention, the wiring between the wirings and the semiconductor chip are mounted in the semiconductor chip mounting area of the semiconductor package chip supporting substrate of the present invention. A pressure is applied to the double-sided adhesive film while heating with a thermocompression bonding machine or the like to adhere to the portion to be formed. The temperature at this time is 1
The temperature is preferably 30 to 200 ° C. and the pressure is preferably 0.15 to 0.3 MPa, more preferably 130 to 150 MPa.
° C and a pressure of 0.2 to 0.25 MPa. The exposed wiring is preferably sequentially subjected to electroless nickel plating and electroless gold plating, and the electroless nickel plating and electroless gold plating are formed by transferring a double-sided adhesive film to the semiconductor package chip supporting substrate. It may be before or after. Also, instead of electroless plating, electrolytic plating may be used. Further, a semiconductor chip is bonded to the surface of the double-sided adhesive film, a semiconductor chip electrode is connected to an inner connection portion of the support substrate by wire bonding or the like, and at least a semiconductor chip electrode surface of the semiconductor chip is resin-sealed. A semiconductor package can be manufactured by providing an outer connection portion that is electrically connected to the inner connection portion in the opening provided in the semiconductor package.
【００１７】[0017]
【実施例】図１により、本発明の一実施例について説明
する。ポリイミド接着材をポリイミドフィルムの両面に
塗布した、厚さ０．０７５ｍｍのポリイミドボンディン
グシート１に、アウター接続部２及び貫通穴（ａ）３、
貫通穴（ｂ）４を形成する。貫通穴（ａ）３、貫通穴
（ｂ）４はそれぞれ、後の工程で両面接着フィルムが転
載形成される箇所及び封止材と接する箇所に形成されて
いる。次に厚さ０．０１８ｍｍの銅箔（日本電解株式会
社製、商品名：SLP−１８）を接着後、インナー接続部
５とアウター接続部２までの展開配線６（これら２，
５，６をまとめて金属パターンと称す）を通常のエッチ
ング法で形成ずる（図１ａ）。さらに、露出している配
線に常法により無電解ニッケルめっき（厚さ：５μ
ｍ）、無電解金めっき（厚さ：０．８μｍ）を順次施
す。次に絶縁性支持基板の半導体チップ搭載領域内にお
ける配線相互間及び半導体チップが搭載される箇所に、
コア材の厚さが２５μｍ、前記コア材の両面に形成され
る接着剤層の厚さがそれぞれ１２.５μｍとなる厚さ５
０μｍの両面接着フィルム７を熱圧着機により温度１５
０℃、圧力０．２５ＭＰａ、時間２秒の条件下で接着す
る（図１ｂ）。両面接着フィルムとして接着剤層は、下
記の組成を用いた。 エポキシ樹脂：ビスフェノールＡ型エポキシ樹脂（エピ
コート８２８、油化シェルエポキシ株式会社製商品名）
４５重量部、クレゾールノボラック型エポキシ樹脂
（ＥＳＣＮ１９５、住友化学工業株式会社製商品名）１
５重量部 エポキシ樹脂の硬化剤：フェノールノボラック樹脂（プ
ライオーフェンＬＦ２８８２、大日本インキ化学工業株
式会社製商品名）４０重量部 エポキシ基含有アクリル系共重合体：ＨＴＲ−８６０Ｐ
−３（帝国化学産業株式会社製商品名）１５０重量部 硬化促進剤：１−シアノエチル−２−フェニルイミダゾ
ール（キュアゾール２ＰＺ−ＣＮ、四国化成工業株式会
社製商品名）０．５重量部 シランカップリング剤：γ−グリシドキシプロピルトリ
メトキシシラン（ＮＵＣＡ−１８７、日本ユニカー株式
会社製商品名）０．７重量部 上記組成をメチルエチルケトンに撹拌溶解し固形分４０
重量％の接着剤ワニスとした。この接着剤ワニスを、厚
さ７５μｍの離型処理したポリエチレンテレフタレート
フィルム上に塗布し、１４０℃で５分間加熱乾燥して膜
厚が１２．５μｍの塗膜とし、接着剤フィルムを作製し
た。この接着剤フィルムの硬化物の貯蔵弾性率を動的粘
弾性測定装置（レオロジー社製、ＤＶＥ−Ｖ４）を用い
て測定（サンプルサイズ 長さ２０ｍｍ、幅４ｍｍ、膜
厚５０μｍ、昇温速度５℃／分、引張りモード 自動静
荷重）した結果、２５℃で３６０ＭＰａ、２６０℃で４
ＭＰａであった。この接着剤フィルムを接着剤層として
コア材である厚さ５０μｍのポリエーテルサルフォン多
孔質フィルム（東洋濾紙株式会社製）の両面に８０℃、
０．３ＭＰａで熱ラミネートし、両面接着フィルムを得
て、これを用いた。そして次に半導体チップ８を支持基
板の所定の位置に温度２２０℃、圧力３０ｋＰａ、時間
５秒の条件の下で接着し、アフターキュア（１８０℃、
１時間）を行う（図１ｃ）。さらに、半導体チップ電極
とインナー接続部とを金ワイヤ９をボンディングして電
気的に接続する（図１ｄ）。このようにして形成したも
のをトランスファーモールド金型に装填し、封止材１０
（日立化成工業株式会社製、商品名：ＣＥＬ７７００）
を用いて封止する（図１ｅ）。その後、アウター接続部
となる開口にはんだボール１１を配置し溶融接合させる
（図１ｆ）。以上のようにして出来上がったフレーム状
のものをパンチにより個々のパッケージに分離して半導
体パッケージが出来上がる（図１ｇ）。FIG. 1 shows an embodiment of the present invention. An outer connecting portion 2 and a through hole (a) 3 are formed on a 0.075 mm thick polyimide bonding sheet 1 in which a polyimide adhesive is applied to both surfaces of a polyimide film.
A through hole (b) 4 is formed. The through-holes (a) 3 and the through-holes (b) 4 are formed at a place where the double-sided adhesive film is transferred and formed in a later step and a place where the through-hole (b) 4 comes into contact with the sealing material. Next, after bonding a copper foil (product name: SLP-18, manufactured by Nippon Electrolysis Co., Ltd.) having a thickness of 0.018 mm, the developed wiring 6 (these wirings 2 and 2) up to the inner connecting portion 5 and the outer connecting portion 2 are formed.
5 and 6 are collectively called a metal pattern) by an ordinary etching method (FIG. 1A). Furthermore, electroless nickel plating (thickness: 5 μ
m) and electroless gold plating (thickness: 0.8 μm) is sequentially applied. Next, between the wirings in the semiconductor chip mounting area of the insulating support substrate and at the place where the semiconductor chip is mounted,
A thickness 5 in which the thickness of the core material is 25 μm, and the thickness of the adhesive layers formed on both surfaces of the core material is 12.5 μm, respectively.
0 μm double-sided adhesive film 7 is heated at a temperature of 15
Bonding is performed under the conditions of 0 ° C., a pressure of 0.25 MPa and a time of 2 seconds (FIG. 1b). The following composition was used for the adhesive layer as a double-sided adhesive film. Epoxy resin: bisphenol A type epoxy resin (Epicoat 828, trade name of Yuka Shell Epoxy Co., Ltd.)
45 parts by weight, cresol novolac epoxy resin (ESCN195, trade name, manufactured by Sumitomo Chemical Co., Ltd.) 1
5 parts by weight Epoxy resin curing agent: 40 parts by weight of phenol novolak resin (Plyofen LF2882, trade name of Dainippon Ink and Chemicals, Inc.) Epoxy group-containing acrylic copolymer: HTR-860P
-3 (trade name, manufactured by Teikoku Chemical Industry Co., Ltd.) 150 parts by weight Curing accelerator: 1-cyanoethyl-2-phenylimidazole (Curesol 2PZ-CN, trade name, manufactured by Shikoku Chemical Industry Co., Ltd.) 0.5 part by weight Silane coupling Agent: γ-glycidoxypropyltrimethoxysilane (NUCA-187, trade name, manufactured by Nippon Unicar Co., Ltd.) 0.7 parts by weight The above composition was stirred and dissolved in methyl ethyl ketone to obtain a solid content of 40.
An adhesive varnish in weight% was obtained. The adhesive varnish was applied on a release-treated polyethylene terephthalate film having a thickness of 75 μm, and dried by heating at 140 ° C. for 5 minutes to form a coating film having a thickness of 12.5 μm, thereby producing an adhesive film. The storage elastic modulus of the cured product of the adhesive film was measured using a dynamic viscoelasticity measuring device (DVE-V4, manufactured by Rheology Co., Ltd.) (sample size: length 20 mm, width 4 mm, film thickness 50 μm, heating rate 5 ° C.). / Min, tensile mode automatic static load) as a result, 360 MPa at 25 ° C and 4 MPa at 260 ° C.
MPa. This adhesive film was used as an adhesive layer at 80 ° C. on both sides of a 50 μm-thick polyether sulfone porous film (manufactured by Toyo Roshi Co., Ltd.) as a core material.
The laminate was thermally laminated at 0.3 MPa to obtain a double-sided adhesive film, which was used. Then, the semiconductor chip 8 is bonded to a predetermined position of the supporting substrate under the conditions of a temperature of 220 ° C., a pressure of 30 kPa and a time of 5 seconds, and after-curing (180 ° C.,
1 hour) (FIG. 1c). Further, the semiconductor chip electrode and the inner connection portion are electrically connected by bonding a gold wire 9 (FIG. 1D). The thus formed product is loaded into a transfer mold and the sealing material 10
(Product name: CEL7700, manufactured by Hitachi Chemical Co., Ltd.)
(FIG. 1e). Thereafter, the solder balls 11 are arranged in the openings to be the outer connection portions and are fused and joined (FIG. 1f). The semiconductor package is completed by separating the frame-like product completed as described above into individual packages by punching (FIG. 1g).
【００１８】出来上がった半導体パッケージについて吸
湿リフロー試験（試験条件、温度：３０℃、湿度：７５
％ＲＨ、９６時間放置後、温度：２３０℃、ＩＲリフロ
ーを２サイクル）を実施した。その結果、リフローによ
る不良（剥離、膨れ、パッケージ内部クラック等）は全
く発生しなかった（試験サンプル数１６個）。また、耐
温度サイクル試験として、低温側を−５０℃に設定、高
温側を１２５℃に設定、そして低温高温それぞれの状態
での放置時間を３０分間に設定して実施した（試験サン
プル数２０個）。その結果、１０００サイクル後で２０
個全てに剥離、膨れ、パッケージ内部クラック等の不良
が無く良好であった。The completed semiconductor package is subjected to a moisture absorption reflow test (test condition, temperature: 30 ° C., humidity: 75).
% RH, and left for 96 hours, followed by two cycles of temperature: 230 ° C and IR reflow. As a result, no defects (peeling, swelling, cracks in the package, etc.) due to reflow occurred (16 test samples). In addition, as a temperature proof test, the low temperature side was set to −50 ° C., the high temperature side was set to 125 ° C., and the standing time in each of the low temperature and high temperature states was set to 30 minutes (20 test samples). ). As a result, after 1000 cycles, 20
All of the pieces were good without defects such as peeling, swelling and cracks inside the package.
【００１９】（比較例１）コア材として厚さ２５μｍの
ポリイミドフィルム（ユーピレックスＳ、宇部興産株式
会社製商品名）を用いた以外は実施例１と同様の方法で
両面接着フィルムを得て、半導体パッケージを作製し
た。出来上がった半導体パッケージについて同様に吸湿
リフロー試験（試験条件、温度：３０℃、湿度：７５％
ＲＨ、９６時間放置後、温度：２３０℃、ＩＲリフロー
を２サイクル）を実施した。その結果、リフローによる
不良（剥離、膨れ、パッケージ内部クラック等）は８個
発生した（試験サンプル数１６個）。また、耐温度サイ
クル試験として、低温側を−５０℃に設定、高温側を１
２５℃に設定、そして低温高温それぞれの状態での放置
時間を３０分間に設定して実施した（試験サンプル数２
０個）が、１０００サイクル後で２０個全てに剥離、膨
れ、パッケージ内部クラック等の不良が無く良好であっ
た。Comparative Example 1 A double-sided adhesive film was obtained in the same manner as in Example 1 except that a polyimide film (Upilex S, trade name of Ube Industries, Ltd.) having a thickness of 25 μm was used as a core material. A package was prepared. Similarly, for the completed semiconductor package, a moisture absorption reflow test (test condition, temperature: 30 ° C., humidity: 75%)
After leaving for 96 hours at RH, the temperature was 230 ° C. and IR reflow was performed for 2 cycles. As a result, eight defects (peeling, swelling, cracks in the package, etc.) due to reflow occurred (16 test samples). As a temperature cycle test, the low temperature side was set to -50 ° C, and the high temperature side was set to 1 ° C.
The test was carried out with the temperature set at 25 ° C. and the time for each of the low temperature and high temperature conditions set at 30 minutes (test sample number 2
0) were good without any defects such as peeling, swelling and cracks in the package after 1000 cycles.
【００２０】[0020]
【発明の効果】本発明では、半導体チップが搭載される
箇所に、コア材が耐熱性樹脂からなる多孔質フィルムで
あり前記コア材の両面に接着剤層が形成された両面接着
フィルムが載置形成されていることにより、半導体パッ
ケージを構成している材料の吸湿した水分がリフロー時
に半導体パッケージ内部で膨張した場合に、両面接着フ
ィルムのコア材が多孔質であるため蒸気圧を緩和させ
て、さらに貫通穴を通して適正に放出させるので、半導
体パッケージ内部に剥離やクラックの発生を抑制でき
る。さらに、半導体チップと半導体パッケージ用チップ
支持基板との熱膨張係数の違いから発生する熱応力が両
面接着フィルム、特に接着剤層において緩和されるた
め、耐温度サイクル試験においても半導体パッケージ内
部でのクラック等の発生を抑制できる。したがって、本
発明によりパッケージクラックを防止し信頼性の高い半
導体装置の製造が可能となる。According to the present invention, a double-sided adhesive film in which a core material is a porous film made of a heat-resistant resin and an adhesive layer is formed on both sides of the core material is placed on a portion where a semiconductor chip is mounted. By being formed, when the moisture absorbed by the material constituting the semiconductor package expands inside the semiconductor package during reflow, the vapor pressure is relaxed because the core material of the double-sided adhesive film is porous, Furthermore, since the semiconductor package is appropriately discharged through the through hole, the occurrence of peeling or cracking inside the semiconductor package can be suppressed. Furthermore, since thermal stress generated due to the difference in the coefficient of thermal expansion between the semiconductor chip and the chip supporting substrate for the semiconductor package is reduced in the double-sided adhesive film, particularly in the adhesive layer, cracks inside the semiconductor package are obtained even in the temperature cycle test. Etc. can be suppressed. Therefore, according to the present invention, a package crack can be prevented and a highly reliable semiconductor device can be manufactured.
【図１】 本発明の一実施例を説明するための半導体パ
ッケージの製造工程を示す断面図である。FIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor package for explaining an embodiment of the present invention.
１ ポリイミドボンディングシート ７ 両面接着
フィルム ２ アウター接続部 ８ 半導体
チップ ３ 貫通穴（ａ） ９ 金ワイ
ヤ ４ 貫通穴（ｂ） １０ 封止材 ５ インナー接続部 １１ はんだ
ボール ６ 展開配線DESCRIPTION OF SYMBOLS 1 Polyimide bonding sheet 7 Double-sided adhesive film 2 Outer connection part 8 Semiconductor chip 3 Through hole (a) 9 Gold wire 4 Through hole (b) 10 Sealant 5 Inner connection part 11 Solder ball 6 Deployment wiring
───────────────────────────────────────────────────── フロントページの続き (72)発明者 栗谷 弘之 茨城県下館市大字小川1500番地 日立化成 工業株式会社総合研究所内 (72)発明者 坪松 良明 茨城県つくば市和台48 日立化成工業株式 会社総合研究所内 Ｆターム(参考） 5F047 AA17 BA21 BB03 BB16 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroyuki Kuritani 1500 Ogawa, Shimodate-shi, Ibaraki Prefecture Within Hitachi Chemical Co., Ltd. F-term in the Research Institute (reference) 5F047 AA17 BA21 BB03 BB16
Claims (3)
配線が形成されており、前記配線は少なくとも半導体チ
ップ電極と接続するインナー接続部及び半導体チップ搭
載領域部を有するものであり、 Ｂ．前記絶縁性支持基板には、前記絶縁性支持基板の前
記配線が形成されている箇所であって前記インナー接続
部と導通するアウター接続部が設けられる箇所に、開口
が設けられており、 Ｃ．前記絶縁性支持基板の前記半導体チップ搭載領域内
における前記配線相互間に、少なくとも１個の貫通穴が
設けられており、 Ｄ．前記絶縁性支持基板の前記半導体チップ搭載領域内
における前記配線相互間及び半導体チップが搭載される
箇所に、コア材が耐熱性樹脂からなる多孔質フィルムで
あり前記コア材の両面に接着剤層が形成された両面接着
フィルムが載置形成されていることを特徴とする半導体
パッケージ用チップ支持基板。1. A. First Embodiment B. A plurality of wirings are formed on one surface of the insulating support substrate, and the wirings have at least an inner connection part connected to a semiconductor chip electrode and a semiconductor chip mounting area part; B. an opening is provided in the insulating support substrate at a position where the wiring is formed on the insulating support substrate and at a position where an outer connection portion that is electrically connected to the inner connection portion is provided; B. at least one through hole is provided between the wirings in the semiconductor chip mounting region of the insulating support substrate; A core material is a porous film made of a heat-resistant resin, and an adhesive layer is provided on both surfaces of the core material, between the wirings and at a location where the semiconductor chip is mounted in the semiconductor chip mounting region of the insulating support substrate. A chip supporting substrate for a semiconductor package, wherein the formed double-sided adhesive film is mounted and formed.
プ支持基板と、前記支持基板の両面接着フィルムの面に
搭載された半導体チップと、前記半導体チップを封止す
る樹脂封止を備えることを特徴とする半導体装置。2. A semiconductor package chip supporting substrate according to claim 1, further comprising: a semiconductor chip mounted on a surface of a double-sided adhesive film of the supporting substrate; and a resin seal for sealing the semiconductor chip. Semiconductor device.
プ支持基板の両面接着フィルムの面に半導体チップを接
着する工程、半導体チップ電極を配線のインナー接続部
とワイヤボンディングにより接続する工程、半導体チッ
プを樹脂封止する工程、前記支持基板の開口にインナー
接続部と導通するアウター接続部を設ける工程を備える
半導体装置の製造方法。3. A step of bonding a semiconductor chip to the surface of the double-sided adhesive film of the chip supporting substrate for a semiconductor package according to claim 1, a step of connecting a semiconductor chip electrode to an inner connection portion of a wiring by wire bonding, and a step of connecting the semiconductor chip. A method of manufacturing a semiconductor device, comprising: a step of sealing with a resin; and a step of providing an outer connection portion that is electrically connected to an inner connection portion in an opening of the support substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000081674A JP2001267462A (en) | 2000-03-17 | 2000-03-17 | Chip supporting substrate for semiconductor package, semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000081674A JP2001267462A (en) | 2000-03-17 | 2000-03-17 | Chip supporting substrate for semiconductor package, semiconductor device and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001267462A true JP2001267462A (en) | 2001-09-28 |
Family
ID=18598582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000081674A Pending JP2001267462A (en) | 2000-03-17 | 2000-03-17 | Chip supporting substrate for semiconductor package, semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001267462A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227961A (en) * | 2007-04-20 | 2007-09-06 | Hitachi Chem Co Ltd | Semiconductor packaging substrate, semiconductor package using same, and method of manufacturing them |
| JP2007227962A (en) * | 2007-04-20 | 2007-09-06 | Hitachi Chem Co Ltd | Semiconductor packaging substrate, semiconductor package using same, and method of manufacturing them |
| JP2011166076A (en) * | 2010-02-15 | 2011-08-25 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| KR20150060101A (en) * | 2013-11-25 | 2015-06-03 | 에스케이하이닉스 주식회사 | Substrate and semiconductor package having ball land, and the methods of fabricating the same |
| CN111683453A (en) * | 2020-06-02 | 2020-09-18 | 上海兆芯集成电路有限公司 | Electronic assembly |
-
2000
- 2000-03-17 JP JP2000081674A patent/JP2001267462A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227961A (en) * | 2007-04-20 | 2007-09-06 | Hitachi Chem Co Ltd | Semiconductor packaging substrate, semiconductor package using same, and method of manufacturing them |
| JP2007227962A (en) * | 2007-04-20 | 2007-09-06 | Hitachi Chem Co Ltd | Semiconductor packaging substrate, semiconductor package using same, and method of manufacturing them |
| JP4605176B2 (en) * | 2007-04-20 | 2011-01-05 | 日立化成工業株式会社 | Semiconductor mounting substrate, semiconductor package manufacturing method, and semiconductor package |
| JP4605177B2 (en) * | 2007-04-20 | 2011-01-05 | 日立化成工業株式会社 | Semiconductor mounting substrate |
| JP2011166076A (en) * | 2010-02-15 | 2011-08-25 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| KR20150060101A (en) * | 2013-11-25 | 2015-06-03 | 에스케이하이닉스 주식회사 | Substrate and semiconductor package having ball land, and the methods of fabricating the same |
| KR102134019B1 (en) * | 2013-11-25 | 2020-07-14 | 에스케이하이닉스 주식회사 | Substrate and semiconductor package having ball land, and the methods of fabricating the same |
| CN111683453A (en) * | 2020-06-02 | 2020-09-18 | 上海兆芯集成电路有限公司 | Electronic assembly |
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