JP2001256109A - 統合キャッシュポートの制御方法および装置 - Google Patents

統合キャッシュポートの制御方法および装置

Info

Publication number
JP2001256109A
JP2001256109A JP2001040587A JP2001040587A JP2001256109A JP 2001256109 A JP2001256109 A JP 2001256109A JP 2001040587 A JP2001040587 A JP 2001040587A JP 2001040587 A JP2001040587 A JP 2001040587A JP 2001256109 A JP2001256109 A JP 2001256109A
Authority
JP
Japan
Prior art keywords
address
cache
memory
data
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001040587A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001256109A5 (enExample
Inventor
Kenneth Walker Shawn
シャウン・ケネス・ウォーカー
Dean A Mulla
ディーン・エー・ムラ
L Ryon Terry
テリー・エル・リョン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2001256109A publication Critical patent/JP2001256109A/ja
Publication of JP2001256109A5 publication Critical patent/JP2001256109A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
JP2001040587A 2000-02-18 2001-02-16 統合キャッシュポートの制御方法および装置 Withdrawn JP2001256109A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US507033 2000-02-18
US09/507,033 US6704820B1 (en) 2000-02-18 2000-02-18 Unified cache port consolidation

Publications (2)

Publication Number Publication Date
JP2001256109A true JP2001256109A (ja) 2001-09-21
JP2001256109A5 JP2001256109A5 (enExample) 2005-08-11

Family

ID=24017001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001040587A Withdrawn JP2001256109A (ja) 2000-02-18 2001-02-16 統合キャッシュポートの制御方法および装置

Country Status (2)

Country Link
US (1) US6704820B1 (enExample)
JP (1) JP2001256109A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012137599A1 (ja) * 2011-04-05 2012-10-11 ルネサスエレクトロニクス株式会社 半導体装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050182884A1 (en) * 2004-01-22 2005-08-18 Hofmann Richard G. Multiple address two channel bus structure
US7769950B2 (en) 2004-03-24 2010-08-03 Qualcomm Incorporated Cached memory system and cache controller for embedded digital signal processor
US7181575B2 (en) * 2004-09-29 2007-02-20 Hewlett-Packard Development Company, L.P. Instruction cache using single-ported memories
US7809874B2 (en) * 2006-06-21 2010-10-05 International Business Machines Corporation Method for resource sharing in a multiple pipeline environment
JP2008198127A (ja) * 2007-02-15 2008-08-28 Toshiba Corp プロセッサシステム
US9009369B2 (en) 2011-10-27 2015-04-14 Apple Inc. Lookahead scheme for prioritized reads
US11768788B2 (en) 2019-07-23 2023-09-26 Hewlett-Packard Development Company, L.P. Bus endpoint isolation

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69229081T2 (de) * 1991-03-01 2000-01-05 Advanced Micro Devices, Inc. Mikroprozessor mit externem Speicher
US5630097A (en) * 1991-06-17 1997-05-13 Digital Equipment Corporation Enhanced cache operation with remapping of pages for optimizing data relocation from addresses causing cache misses
US5440713A (en) * 1992-05-29 1995-08-08 Industrial Technology Research Institute M-way N-port paged-interleaved memory system
US5640527A (en) * 1993-07-14 1997-06-17 Dell Usa, L.P. Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states
US5398211A (en) * 1993-10-14 1995-03-14 Integrated Device Technology, Inc. Structure and method for providing prioritized arbitration in a dual port memory
US5754865A (en) * 1995-12-18 1998-05-19 International Business Machines Corporation Logical address bus architecture for multiple processor systems
US5943691A (en) * 1995-12-27 1999-08-24 Sun Microsystems, Inc. Determination of array padding using collision vectors
US6279077B1 (en) * 1996-03-22 2001-08-21 Texas Instruments Incorporated Bus interface buffer control in a microprocessor
US5860017A (en) 1996-06-28 1999-01-12 Intel Corporation Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
SG63746A1 (en) * 1996-09-20 1999-03-30 Texas Instruments Inc Method and system for testing memory
US5859999A (en) 1996-10-03 1999-01-12 Idea Corporation System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
EP0845741B1 (en) * 1996-11-29 2003-04-16 Matsushita Electric Industrial Co., Ltd. Processor which can favorably execute a rounding process
US6195735B1 (en) * 1996-12-31 2001-02-27 Texas Instruments Incorporated Prefetch circuity for prefetching variable size data
US6212607B1 (en) * 1997-01-17 2001-04-03 Integrated Device Technology, Inc. Multi-ported memory architecture using single-ported RAM
US5950229A (en) * 1997-03-12 1999-09-07 Micron Electronics, Inc. System for accelerating memory bandwidth
US6275491B1 (en) * 1997-06-03 2001-08-14 Texas Instruments Incorporated Programmable architecture fast packet switch
US5961631A (en) * 1997-07-16 1999-10-05 Arm Limited Data processing apparatus and method for pre-fetching an instruction in to an instruction cache
US6085263A (en) * 1997-10-24 2000-07-04 Compaq Computer Corp. Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor
US6401176B1 (en) * 1997-11-14 2002-06-04 Agere Systems Guardian Corp. Multiple agent use of a multi-ported shared memory
US6189076B1 (en) * 1997-11-14 2001-02-13 Lucent Technologies, Inc. Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal
US6314499B1 (en) * 1997-11-14 2001-11-06 Lucent Technologies Inc. Non-preemptive memory locking mechanism in a shared resource system
US6560674B1 (en) * 1998-10-14 2003-05-06 Hitachi, Ltd. Data cache system
US6557078B1 (en) * 2000-02-21 2003-04-29 Hewlett Packard Development Company, L.P. Cache chain structure to implement high bandwidth low latency cache memory subsystem

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012137599A1 (ja) * 2011-04-05 2012-10-11 ルネサスエレクトロニクス株式会社 半導体装置
JP5559932B2 (ja) * 2011-04-05 2014-07-23 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
US6704820B1 (en) 2004-03-09

Similar Documents

Publication Publication Date Title
US5809280A (en) Adaptive ahead FIFO with LRU replacement
US6594728B1 (en) Cache memory with dual-way arrays and multiplexed parallel output
US4831520A (en) Bus interface circuit for digital data processor
US7284092B2 (en) Digital data processing apparatus having multi-level register file
US5559986A (en) Interleaved cache for multiple accesses per clock cycle in a microprocessor
US5598550A (en) Cache controller for processing simultaneous cache accesses
US4851991A (en) Central processor unit for digital data processing system including write buffer management mechanism
US7236421B1 (en) Read-modify-write memory using read-or-write banks
US6138208A (en) Multiple level cache memory with overlapped L1 and L2 memory access
US4831581A (en) Central processor unit for digital data processing system including cache management mechanism
KR20040041550A (ko) 타입 비트들을 이용한, 레벨 2 캐시에서의 ｅｃｃ 및프리디코드 비트들의 저장 추적
US5091845A (en) System for controlling the storage of information in a cache memory
US5119484A (en) Selections between alternate control word and current instruction generated control word for alu in respond to alu output and current instruction
US5226170A (en) Interface between processor and special instruction processor in digital data processing system
US5761714A (en) Single-cycle multi-accessible interleaved cache
US5550995A (en) Memory cache with automatic alliased entry invalidation and method of operation
US5854943A (en) Speed efficient cache output selector circuitry based on tag compare and data organization
JP2001256109A (ja) 統合キャッシュポートの制御方法および装置
JP2716350B2 (ja) 電子データ記憶システム
JPH04253237A (ja) 転写キャッシュ構造体およびその方法
US5276892A (en) Destination control logic for arithmetic and logic unit for digital data processor
EP0302926B1 (en) Control signal generation circuit for arithmetic and logic unit for digital processor
JP2756546B2 (ja) デジタルデータ処理システムに使用される処理装置
JPH07319768A (ja) キャッシュメモリ装置
JPH09179781A (ja) カラム書き込み確認機能を持つキャッシュ

Legal Events

Date Code Title Description
RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20040924

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20041019

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050119

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050119

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20070207