JP2001251216A - Circuit and method for capturing synchronization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decide a threshold in a synchronization capturing circuit depending on a communication environment. SOLUTION: The synchronization capturing circuit is provided with a spread code generating section 102 that provides the output of a spread code 202 started from a received phase value that is sequentially revised, a correlation arithmetic section 103 that applies a correlation arithmetic operation to a received signal 201 and the spread code 202 to provide the output of a correlation power 204, a comparison section 109 that compares the correlation power 204 with a threshold 209 to provide an output of a phase value 210 when the correlation power 204 is larger than the threshold 209, and a multiplier section 108 that outputs the threshold value 209, in response to a value of a delay profile obtained by the correlation power 204 that is calculated in the past by the correlation arithmetic section 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to performing a correlation operation while sequentially changing the phase of a spreading code by using the same spreading code as that used on the transmission side, and calculating a correlation power and a threshold obtained by the correlation operation. The present invention relates to a synchronization acquisition circuit of a wireless communication system using a spread spectrum technique for comparing a value with a value, storing the value in a memory for holding an allocation path candidate, and selecting a path to be allocated to a demodulation unit from the contents of the memory.

[0002]

2. Description of the Related Art Conventionally, as a threshold value determining method for path selection, for example, “Fukumoto et al.,“ RA in W-CDMA ”
Experimental Study of KE Synthesis Path Search ", IEICE Technical Report, RCS98-30". In the above document, an average delay profile is obtained by averaging correlation values corresponding to each phase of a spread code output from a matched filter over a plurality of slots. A constant multiple of the power averaged over the remaining paths excluding the top four paths with the largest signal power from the obtained delay profile is used as the path selection threshold.

[0003]

The synchronization acquisition method described in the above document requires a buffer for holding a correlation value for each phase in order to obtain an average delay profile, and selects a path based on the contents held in the buffer. Is determined, but there is a problem that the circuit scale increases when the phase range for obtaining the delay profile becomes large.

[0004]

According to the present invention, in order to solve the above-mentioned problems, a first signal generator for outputting a first signal starting from a sequentially changed phase value to be inputted, and a first signal to be inputted, are provided. A correlation operation unit that performs a correlation operation on the received signal and the first signal to output a correlation power value, and compares the correlation power value with the value of the second signal to determine whether the correlation power value is the second signal When the value is larger than the value of the second signal, a comparison unit that outputs a phase value as a candidate for an initial phase value, and a second signal according to a value of a delay profile obtained from a correlation power value calculated in the past by a correlation calculation unit. And a second signal generator that outputs

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Explanation of First Configuration) FIG. 1 is a block diagram showing a first embodiment. The illustrated synchronization acquisition circuit includes a reception signal input terminal 101, a spreading code generation unit 102, a correlation calculation unit 103, an average power calculation unit 104, a forgetting coefficient input terminal 105, a weighted average processing unit 106, a constant input terminal 107, and a multiplication unit 108. , A comparison unit 109, and a path candidate holding unit 110.

A reception signal input terminal 101 receives a signal input from an antenna, multiplies the carrier signal by a carrier frequency, removes the carrier signal, and transmits the reception signal from which the carrier signal has been removed to a baseband through a band limiting filter. The received signal 201, which is converted into a signal and the converted baseband received signal is converted from an analog signal to a digital signal by an A / D converter, is input.

The spread code generation unit 102 receives a signal indicating a phase value and a correlation calculation range from a processor (not shown) for managing the operation of the synchronization acquisition circuit, and spreads the spread codes by the number of correlation calculation ranges from the phase value. 202 is generated. at the same time,
This phase value is output as the phase value 203. Spreading code 2
02 is, for example, a PN code, a Gold code, or the like.

[0008] Correlation operation section 103 receives signal input terminal 1
Correlation operation is performed on the received signal 201 input from 01 and the spread code 202 output from the spread code generator 102, and a correlation power value 204 corresponding to the phase value 203 is output.

[0009] The average power calculation unit 104 includes the correlation calculation unit 10.
The average of the correlation power values 204 corresponding to the respective phase values 203 output from No. 3 is output as an average correlation power value 205.

A forgetting coefficient input terminal 105 receives a forgetting coefficient signal 206 as a forgetting coefficient λ (0 ≦ λ ≦ 1) used in the weighted averaging process from a processor (not shown) for managing the operation of the synchronization acquisition circuit. .

The weighted average processing section 106 performs a weighted average of the average correlation power value 205 output from the average power calculation section 104 and the forgetting coefficient signal 206 input from the forgetting coefficient input terminal 105 to obtain a weighted average value 207. Is output.

A constant signal 208 having a predetermined constant K (0 <K) is input to a constant input terminal 107 from a processor (not shown) for managing the operation of the synchronization acquisition circuit.

The multiplying unit 108 includes a weighted average value 207 output from the weighted average processing unit 106 and a constant input terminal 107
Is multiplied by a constant signal 208 input thereto, and the multiplied value is output as a threshold value 209.

The comparing section 109 compares the correlation power value 204 output from the correlation calculating section 103 with the threshold value 209 output from the multiplying section 108. Comparing section 109 compares phase value 203 output from spreading code generating section 102 with correlation power value 204 corresponding to phase value 203 when correlation power value 204 is equal to or greater than threshold value 209 as a result of the comparison. Are output as the phase value 210 and the correlation power value 211 as they are.

The path candidate holding section 110 holds path candidate data 212 in which the phase value 210 output from the comparing section 109 and the correlation power value 211 are paired data.

(Description of First Operation) In the above configuration,
The operation of the present invention will be described. The operation of the present invention is shown in FIG.
As shown in (1), it comprises a pre-process S-1, a synchronization acquisition process S-2, and a post-process S-3.

S-1. Pre-processing (FIG. 2) As shown in FIG. 2, the pre-processing S-1 is a weighted average processing S-1.
a and a multiplication process S-1b. Each process will be described with reference to FIG.

S-1a. Weighted Average Processing (FIG. 2) The weighted average processing section 106 performs the following weighted average processing. In the average correlation power value 205 output from the average power calculation unit 104, the average correlation power value obtained by the previous synchronization acquisition process (the process described later) is set as the average correlation power value α. The previous weighted average processing result output as the weighted average value 207 is defined as the weighted average processing result β. The forgetting coefficient input from the forgetting coefficient input terminal 105 by a processor (not shown) that manages the operation of the synchronization acquisition circuit is defined as a forgetting coefficient λ. At this time, the weighted average processing result β ′
Is obtained from the average correlation power value α, the previous weighted average processing result β, and the forgetting coefficient λ by the weighted averaging processing using the forgetting coefficient, as in Expression (1). β ′ = (α + λβ) / (1 + λ) Expression (1) The obtained weighted average processing result β ′ is the weighted average value 2
07 is output.

S-1b. Multiplication process (FIG. 2) In the multiplication unit 109, a weighted average value 207 output from the weighted average processing unit 106 and a constant input from a processor (not shown) for managing the operation of the synchronization acquisition circuit. Multiply by the constant K input from the terminal 109. The multiplication unit 109 uses the multiplied value as a threshold value K used in the current synchronization acquisition process.
It is output as a threshold value 209 of β ′.

S-2. Synchronization Acquisition Processing (FIG. 2) In the above preprocessing, after the threshold value 209 is obtained, the synchronization acquisition processing is started. As shown in FIG. 2, the synchronization acquisition process S-2 includes a spread code generation process S-2a, a correlation operation process S-2b, a comparison process S-2c, and a path candidate holding process S-2.
d, the average power calculation processing S-2e. The synchronization acquisition process is performed by the number of phase values output from a processor (not shown) that manages the operation of the synchronization acquisition circuit.
The above five processes are performed in a cyclic manner. Each process will be described with reference to FIG.

S-2a. Spreading Code Generation Processing (FIG. 2) The spreading code generator 102 receives the phase value and the correlation calculation range, and generates the spreading codes 202 by the number of correlation calculation ranges starting from the phase value. I do. Also, this phase value is referred to as phase value 2
03 is output. Here, the input phase value and the correlation calculation range are output from a processor (not shown) that manages the operation of the synchronization acquisition circuit, and this phase value is determined in advance every time the spreading code generation processing is performed. The phase value is changed by the set value. Here, the spreading code 202 is, for example, a PN code, a Gold code, or the like.

S-2b. Correlation Calculation Processing (FIG. 2) The correlation calculation section 103 calculates a correlation between the spread code 202 output from the spread code generation section 102 and the reception signal 201 input from the reception signal input terminal 101. And the phase value 2
And outputs a correlation power value 204 corresponding to “03”.

S-2c. Comparison Processing (FIG. 2) In the comparison section 109, the correlation power value 204 corresponding to the phase value 203 output from the correlation calculation section 103, the threshold value 209 obtained in the above preprocessing, and Compare. Comparison section 109
Then, when the correlation power value 204 is equal to or larger than the threshold value 209,
The phase value 203 and the correlation power value 204 output from the spreading code generator 102 are compared with the phase value 210 and the correlation power value 211.
Is output to the path candidate holding unit 109.

S-2d. Path candidate holding processing (FIG. 2) In the path candidate holding section 110, the comparing section 109 sets the correlation power value 204 to be equal to or more than the threshold value 209, and
When 09 outputs the phase value 210 and the correlation power value 211, the following three processes are performed. By these processes, the path candidate holding unit 110 stores the path candidate data 21 in which the phase value 210 and the correlation power value 211 are paired data.
Hold 2. Here, the path candidate data 212 is composed of a plurality of path candidate values, and holds path candidate values for a predetermined number of buffers in descending order of the correlation power value.

In the first process, path candidate data 212 in which a phase value 210 and a correlation power value 211 are paired is held in a buffer. As a holding method, the path candidate data 212 including a plurality of path candidate values is rearranged in descending order of the correlation power value of each path candidate value and stored in the buffer.

In the second process, when there is a path candidate value 212 composed of a plurality of path candidate values that is equal to the phase value of each path candidate value, the correlation power value is the largest among these path candidate values. The path candidate value 212 leaving only the path candidate value having a value is held in the buffer.

In the third process, when the path candidate value 212 including a plurality of path candidate values exceeds a predetermined number of buffers, the path candidate value having the smallest correlation power value from the path candidate value 212 is discarded. And hold it in the buffer.

S-2e. Average Power Calculation Processing (FIG. 2) In the average power calculation section 104, the previously added and held value corresponding to the phase value 203 and the phase value 203 output from the correlation calculation section 103 are calculated. Is added to the correlation power value 204 corresponding to. Here, the correlation power value 204 is
Part of the delay profile.

S-3. Post-Process (FIG. 2) As shown in FIG. 2, post-process S-3 is a process including an average power calculation process S-3a and a path candidate selection process S-3b. Each process will be described with reference to FIG.

S-3a. Average Power Calculation Processing (FIG. 2) In the average power calculation section 104, when the synchronization acquisition processing is completed, the average value calculated by adding the values previously held corresponding to the respective phase values and holding the values is calculated. do. The calculated average value is output to the weighted average processing unit 106 as the average correlation power value 205 to prepare for the calculation of the threshold value 209 in the next synchronization acquisition processing.

S-3b. Path candidate selection processing (FIG. 2) Processor (not shown) for managing the operation of the synchronization acquisition circuit
Thus, the path candidate data 212 held in the path candidate holding unit 110 is selected as a path candidate that has been synchronously captured. Here, when the number of required path candidates is one,
The phase value is selected from the path candidate values having the largest correlation power value. When the number of required path candidates is plural, the phase value is sequentially selected from the path candidate values having a large correlation power value. This phase value is used as an initial phase value of a spread code used for correlation calculation with a received signal at the time of demodulation.

(Explanation of First Effect) According to the first embodiment described in detail above, (1) the threshold value can be determined before the synchronization acquisition processing. (2) The threshold value used for the synchronization acquisition process can be determined adaptively according to the communication environment. (3) Since the threshold value used for the synchronization acquisition processing is adaptively determined by the weighted average processing using the forgetting coefficient of the average power obtained from the past delay profile, a highly accurate communication environment can be estimated. (4) By using the average power obtained from the past delay profile as the value used for the weighted averaging process, if the desired signal power is large, the threshold value can be set high and the probability of selecting an interference wave as a path candidate is increased. If the desired signal power is small, the listening value can be set low, so that the probability of selecting the desired signal power as a path candidate can be increased.

(Explanation of Second Configuration) FIG. 3 is a block diagram showing a second embodiment. Portions common to the previous embodiment are denoted by the same reference numerals and description thereof is omitted. The path selection determination circuit of the illustrated synchronization acquisition circuit includes a reception signal input terminal 101, a spread code generation unit 102, a correlation calculation unit 103, an interference power input terminal 111, an average processing unit 112, a first constant input A terminal 113, a first multiplication unit 114, a comparison unit 109, and a path candidate holding unit 110
And

Each of the interference power input terminals 111 has a finger circuit (not shown) corresponding to each path of the received signal.
Interference power 2 that is obtained as interference power x (x = 0 to X)
13 is input. Here, the finger circuit is a circuit that performs a correlation operation when demodulating a received signal using a spreading code.

In the averaging unit 112, the interference power x (x = x) of the interference power 213 input to the interference power input terminal 111
0 to X) to calculate the average interference power 21
4 is output.

The first constant input terminal 113 receives a constant signal 215 having a predetermined coefficient L (0 <L) from a processor (not shown) for managing the operation of the synchronization acquisition circuit.

In the first multiplication section 114, the averaging section 11
2 is multiplied by the first constant signal 215 input from the constant input terminal 113, and the first multiplied value is output as the threshold 209.

The comparator 109 compares the correlation power value 204 output from the correlation calculator 103 with the threshold 209 output from the first multiplier 114 instead of the multiplier 108. When the correlation power value 204 is equal to or larger than the threshold value 209 as a result of the comparison, the comparing unit 109 compares the phase value 203 output from the spreading code generation unit 102 with the phase value 203.
And the correlation power value 204 corresponding to
0 and output as the correlation power value 211. The contents of the processing are the same as in the previous embodiment.

(Description of Second Operation) In the above configuration,
The operation of the present invention will be described. The operation of the present invention is shown in FIG.
As shown in (1), it comprises a pre-process S-1, a synchronization acquisition process S-2, and a post-process S-3. Portions common to the previous embodiment are denoted by the same reference numerals and description thereof is omitted.

S-1. Pre-Processing (FIG. 4) As shown in FIG. 4, the pre-processing S-1 performs a process including an averaging process S-1c and a first multiplication process S-1d. Each process will be described with reference to FIG.

S-1c. Averaging Processing (FIG. 4) The averaging processing section 112 performs the following averaging processing. In the averaging unit 112, the interference power 21 including the interference power x (x = 0 to X) input from the interference power input terminal 111
3 and multiplies the average interference power 214 by the multiplication unit 1
14 is output.

Here, the interference power 213 is calculated, for example, by a finger circuit (not shown) that performs a correlation operation for each path of the received signal, and calculates an average of the correlation values and an average of the correlation values. The difference from the correlation value delayed so as to be equal to the phase value in the value is taken, and this difference value is set to a value converted into a power value.

S-1d. First Multiplication Process (FIG. 4) The first multiplication unit 114 manages the average interference power 214 output from the average processing unit 112 and the operation of the synchronization acquisition circuit (not shown). 3) multiplies by a constant 215, which is a constant L input from the constant input terminal 113, and outputs a threshold value 209 used in the current synchronization acquisition processing.

S-2. Synchronization Acquisition Processing (FIG. 4) In the above preprocessing, after the threshold value 209 is obtained, the synchronization acquisition processing is started. As shown in FIG. 4, the synchronization acquisition process S-2 includes a spread code generation process S-2a, a correlation operation process S-2b, a comparison process S-2c, and a path candidate holding process S-2d.
The above four processes are performed. The synchronization acquisition process is performed by circulating the above four processes by the number of phase values output from a processor (not shown) that manages the operation of the synchronization acquisition circuit. These processes are the same as those in the previous embodiment, and a description thereof will be omitted.

S-3. Post-Process (FIG. 4) As shown in FIG. 4, post-process S-3 performs a process including a path candidate selection process S-3b. These processes are the same as those in the previous embodiment, and a description thereof will be omitted.

(Explanation of Second Effect) According to the second embodiment described in detail above, (1) the threshold value can be determined before the synchronization acquisition processing. (2) The threshold value used for the synchronization acquisition process can be determined adaptively according to the communication environment. (3) Since the threshold value used for the synchronization acquisition process can be obtained from the interference power of the currently received path, highly accurate interference power can be estimated. Further, by averaging the interference power of each finger, the estimation error of each finger can be averaged.

(Explanation of Third Configuration) FIG. 5 is a block diagram showing a third embodiment. Portions common to the previous embodiment are denoted by the same reference numerals and description thereof is omitted. The path selection determination circuit of the illustrated synchronization acquisition circuit includes a reception signal input terminal 101, a spread code generation unit 102, a correlation calculation unit 103, an interference power input terminal 111, an average processing unit 112, a first constant input A terminal 113, a first multiplier 114, a desired power input terminal 115, a maximum power detector 116, a second constant input terminal 117, a second multiplier 118, and a threshold selector 119. , The comparison unit 109
And a path candidate holding unit 110.

In the first multiplication unit 114, the averaging unit 11
2 is multiplied by the first constant signal 215 input from the constant input terminal 113, and the first multiplied value is replaced with the first multiplied value 216 instead of the threshold 209. Output as The contents of the processing are the same as in the previous embodiment.

Each desired power input terminal 115 has a finger circuit (not shown) corresponding to each path of the received signal.
Desired power x obtained as desired power x (x = 0 to X)
17 is input.

The maximum power detector 116 calculates the desired power x of the desired power 217 input from the desired power input terminal 115.
(X = 0 to X), and the maximum power 218
Is output.

A second constant input terminal 117 receives a second constant signal 2 having a predetermined coefficient N (0 <N) from a processor (not shown) for managing the operation of the synchronization acquisition circuit.
19 is input.

The second multiplier 118 multiplies the maximum power 218 output from the maximum power detector 116 by a second constant signal 219 input from a second constant input terminal 117 to obtain a second constant. Is output.

In the threshold value selecting section 119, the first multiplied value 216 output from the first multiplying section 114 and the second multiplied value 220 output from the second multiplying section 118 are selected and selected. , And outputs the selected value as the threshold value 209.

Comparison section 109 compares correlation power value 204 output from correlation operation section 103 with threshold value 209 output from threshold value selection section 119 instead of multiplication section 108. When the correlation power value 204 is equal to or larger than the threshold value 209 as a result of the comparison, the comparing unit 109 compares the phase value 203 output from the spreading code generation unit 102 with the phase value 20.
3 and the correlation power value 204 corresponding to the phase value 2
10 and output as a correlation power value 211. The contents of the processing are the same as in the previous embodiment.

(Description of Third Operation) In the above configuration,
The operation of the present invention will be described. The operation of the present invention is shown in FIG.
As shown in (1), it comprises a pre-process S-1, a synchronization acquisition process S-2, and a post-process S-3. Portions common to the previous embodiment are denoted by the same reference numerals and description thereof is omitted.

S-1. Pre-processing (FIG. 6) As shown in FIG. 4, the pre-processing S-1 includes an averaging process S-1c and a first multiplication process S-1d, a maximum power detection process S-1e, A process including a second multiplication process S-1f and a threshold value selection process S-1g is performed. Each process will be described with reference to FIG.

S-1d. First Multiplication Process (FIG. 4) In the first multiplication unit 114, the average interference power 214 output from the average processing unit 112 and the
A processor (not shown) for managing the operation of the synchronization acquisition circuit
The value is multiplied by a constant 215, which is a constant L input from the constant input terminal 113. However, here, instead of outputting the threshold value 209 used in the current synchronization acquisition process using the multiplied value, the first multiplied value 216 is output.

S-1e. Maximum Power Detection Processing (FIG. 6) The maximum power detection unit 116 performs the following maximum power detection processing. The maximum power detection unit 116 detects the highest power among the desired powers 217 including the desired powers x (x = 0 to X) input from the desired power input terminal 115, and determines the maximum desired power 218 as a second power. The result is output to the multiplication unit 118 of 2.

Here, the maximum desired power 218 is calculated, for example, by a finger circuit (not shown) which performs a correlation operation for each path of the received signal, and an average of these correlation values is calculated. , A value converted from the average value to a power value.

S-1f. Second Multiplication Process (FIG. 6) The second multiplication unit 118 manages the maximum desired power 218 output from the maximum power detection unit 116 and the operation of the synchronization acquisition circuit (FIG. 6). (Not shown) through a second constant input terminal 117 and multiplied by a constant 219 which is a constant L, and outputs a second multiplied value 220 to the threshold value selection unit 119.

S-1g. Threshold Value Selection Process (FIG. 6) In the threshold value selection unit 119, the first multiplication value 216 output from the first multiplication unit 114 and the output value from the second multiplication unit 118 are output. The second multiplied value 220 is compared with the second multiplied value 220. If the first multiplied value 216 is smaller than the second multiplied value 220, the second multiplied value 220 is set to the threshold 209, and the first multiplied value 216 is set. Is larger than the second multiplied value 220, the first multiplied value 216 is output to the comparing unit 109 as the threshold 209.

S-2. Synchronization Acquisition Processing (FIG. 6) In the above preprocessing, after the threshold value 209 is obtained, the synchronization acquisition processing is started. As shown in FIG. 6, the synchronization acquisition process S-2 includes a spread code generation process S-2a, a correlation operation process S-2b, a comparison process S-2c, and a path candidate holding process S-2d.
The above four processes are performed. The synchronization acquisition process is performed by circulating the above four processes by the number of phase values output from a processor (not shown) that manages the operation of the synchronization acquisition circuit. These processes are the same as those in the previous embodiment, and a description thereof will be omitted.

S-3. Post-Process (FIG. 6) As shown in FIG. 6, post-process S-3 performs a process including a path candidate selection process S-3b. These processes are the same as those in the previous embodiment, and a description thereof will be omitted.

(Explanation of Third Effect) According to the third embodiment described in detail above, (1) the threshold value can be determined before the synchronization acquisition processing. (2) The threshold value used for the synchronization acquisition process can be determined adaptively according to the communication environment. (3) Determine the lower limit of the power of the effective path from the desired power of the path currently receiving the threshold used for the synchronization acquisition processing, and determine the upper limit of the interference power from the interference power of the currently received path. By doing so, when the power of the desired signal is high, the probability of selecting an interference wave as a path candidate is reduced, and when the desired signal power is low, the threshold value can be set to a small value. In addition to increasing the probability, if the desired signal power is too small, the probability of selecting an interference wave as a path candidate can be reduced because the interference power is set to be equal to or higher than the upper limit value of the interference power.

[0065]

According to the present invention described in detail above, (1) the threshold value can be determined before the synchronization acquisition processing. (2) The threshold value used for the synchronization acquisition process can be determined adaptively according to the communication environment.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a synchronization acquisition circuit according to a first embodiment.

FIG. 2 is a flowchart of a synchronization acquisition circuit according to the first embodiment;

FIG. 3 is a block diagram illustrating a configuration of a synchronization acquisition circuit according to a second embodiment.

FIG. 4 is a flowchart of a synchronization acquisition circuit according to a second embodiment.

FIG. 5 is a block diagram illustrating a configuration of a synchronization acquisition circuit according to a third embodiment.

FIG. 6 is a flowchart of a synchronization acquisition circuit according to a third embodiment.

[Explanation of symbols]

101: reception signal input terminal, 102: spread code generation unit,
103: correlation operation unit, 104: average power operation unit, 105
... Forgetting coefficient input terminal, 106.
... constant input terminal, 108 ... multiplication unit, 109 ... comparison unit, 1
10: path candidate holding unit, 201: received signal, 202: spreading code, 203: phase value, 204: correlation power value, 205
... average correlation power value, 206 ... forgetting coefficient signal, 207 ... weighted average value, 208 ... constant signal, 209 ... threshold value, 21
0: phase value, 211: correlation power value, 212: path candidate data.

Claims (14)

[Claims] A first signal generator for outputting a first signal starting from an input sequentially changed phase value; and a correlation operation between an input received signal and the first signal, A correlation operation unit that outputs a correlation power value, and compares the correlation power value with a value of a second signal, and when the correlation power value is greater than a value of the second signal, uses the phase value as a path candidate. A comparing unit that outputs the second signal in accordance with a value of a delay profile obtained from the correlation power value calculated in the past by the correlation calculating unit. A synchronization acquisition circuit characterized in that: 2. The synchronous signal acquisition circuit according to claim 1, wherein the second signal generator averages the correlation power values corresponding to the respective phase values calculated in the past by the correlation calculator, A synchronization acquisition circuit for outputting the second signal. 3. The synchronization acquisition circuit according to claim 1, wherein
The comparison unit compares the correlation power value with a value of a second signal, and when the correlation power value is larger than a value of a second signal, the phase value and the correlation power corresponding to the phase value. And a storage unit for storing the phase value and the correlation power value as first data, and passing the phase value having a larger value of the correlation power value in the first data. And a selector for selecting as a candidate. 4. A synchronous acquisition circuit in which respective interference signal powers and desired signal powers in a plurality of paths of a received signal input in the past are extracted. A first signal generation unit that outputs a correlation signal between the received signal and the first signal, and a correlation operation unit that outputs a correlation power value; A comparing unit that compares the value of the second signal and outputs the phase value as a path candidate when the correlation power value is larger than the value of the second signal; and the interference signal power or the desired signal power. In response to the,
And a second signal generator for outputting the second signal. 5. The synchronous signal acquisition circuit according to claim 4, wherein the second signal generator calculates an average of the plurality of interference signal powers, multiplies the calculated average by a predetermined value, and multiplies the average. A synchronization acquisition circuit for outputting the calculated value as the third signal. 6. The average acquisition unit according to claim 4, wherein the second signal generation unit calculates an average value from the plurality of interference signal powers, and outputs the calculated average value. A first multiplier for multiplying the average value by a predetermined value and outputting a multiplied first multiplied value; detecting a maximum value from a plurality of the desired signal powers; A maximum value detector that outputs a value, a second multiplier that multiplies the maximum value by a predetermined value, and outputs a multiplied second multiplied value, and the first multiplied value is the second multiplied value. Is larger than the multiplied value, the first multiplied value is output as the third signal,
And a first selector for outputting the second multiplied value as the third signal when the first multiplied value is smaller than the second multiplied value. . 7. The synchronization acquisition circuit according to claim 4,
The comparison unit compares the correlation power value with a value of a second signal, and when the correlation power value is larger than a value of a second signal, the phase value and the correlation power corresponding to the phase value. And a storage unit for storing the phase value and the correlation power value as first data, and passing the phase value having a larger value of the correlation power value in the first data. A first selection unit for selecting a candidate as a candidate. 8. A first signal generating step of outputting a first signal starting from an input sequentially changed phase value, and a correlation operation between an input received signal and the first signal is performed, A correlation operation step of outputting a correlation power value, and comparing the correlation power value with a value of a second signal, and when the correlation power value is larger than a value of the second signal, using the phase value as a path candidate And a second signal generating step of outputting the second signal in accordance with a value of the delay profile obtained from the correlation power value calculated in the past in the correlation calculating step. A synchronization acquisition method characterized by the above-mentioned. 9. The synchronous signal acquisition method according to claim 8, wherein the second signal generation step averages the correlation power values corresponding to the respective phase values calculated in the past in the correlation calculation step, Outputting the second signal. 10. The synchronization acquisition method according to claim 8, wherein the comparing step compares the correlation power value with a value of a second signal, and the correlation power value is larger than a value of the second signal. A step of outputting the phase value and the correlation power value corresponding to the phase value; and further storing the phase value and the correlation power value as first data; and Selecting the phase value having a large value of the correlation power value as a path candidate. 11. A synchronization acquisition method in which respective interference signal powers and desired signal powers in a plurality of paths of a received signal input in the past are extracted, wherein the first signal starting from the sequentially changed phase value input is used. A first signal generating step of outputting a correlation signal between the received signal and the first signal, and a correlation operation step of outputting a correlation power value; Comparing the value of the second signal, and when the correlation power value is greater than the value of the second signal, outputting the phase value as a path candidate; and comparing the interference signal power or the desired signal power. In response to the,
A second signal generation step of outputting the second signal. 12. The method according to claim 11, wherein the second signal generation step calculates an average of a plurality of the interference signal powers, multiplies the calculated average by a predetermined value, and performs multiplication. Outputting the calculated value as the third signal. 13. The synchronizing acquisition method according to claim 11, wherein the second signal generating step includes an average processing step of calculating an average value from the plurality of interference signal powers and outputting the calculated average value. A first multiplication step of multiplying the average value by a predetermined value and outputting a multiplied first multiplication value; detecting a maximum value from a plurality of the desired signal powers; A maximum value detecting step of outputting a value, a second multiplying step of multiplying the maximum value by a predetermined value and outputting a multiplied second multiplied value, and wherein the first multiplied value is the second multiplied value. Is larger than the multiplied value, the first multiplied value is output as the third signal,
A first selecting step of outputting the second multiplied value as the third signal when the first multiplied value is smaller than the second multiplied value. . 14. The synchronization acquisition method according to claim 11, wherein the comparing step compares the correlation power value with a value of a second signal, and the correlation power value is larger than a value of the second signal. A step of outputting the phase value and the correlation power value corresponding to the phase value; and further storing the phase value and the correlation power value as first data; and Selecting the phase value having a large correlation power value as a path candidate in the first step.