JP3369498B2 - CDMA synchronizer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CDMA synchronizer used in a CDMA wireless communication system.

[0002]

2. Description of the Related Art CDMA (Code Division Multiple Access) is used as a multiple access system for the next-generation mobile communication system.
Is being developed. In this CDMA cellular system, it is necessary to perform a cell search for initial synchronization establishment work when the mobile station is powered on and for cell switching (handover) accompanying movement.

This cell search includes a first detection step to a third detection step, and the first detection step includes processing from the first stage to the third stage. The processing in these detection steps will be described.

In the first-stage processing in the first detection step, a perch channel which is a control channel is continuously received by a complex matched filter having a common search code as a coefficient, and a long code mask symbol is received. 1
Obtain the delay profile of the stage. However, in order to obtain a stable delay profile, a filter output is synchronously added using a memory having a one-slot time length.

In the second stage processing in the first detection step,
For example, four kinds of group short codes are simultaneously generated at the timing of the maximum path of the delay profile obtained in the processing of the first stage, and the correlation processing is performed between the group short codes and the control channel signal. This processing is executed in about 10 ms using a dedicated correlator, and the group short code to which the maximum path belongs is specified from its maximum output. As a result, the long code used for the downlink is narrowed down from 128 types to 32 types.

In the process of the third stage in the first detection step, first, the received data of the first symbol of the slot is stored in the RAM.
The complex matched filter, which has a code consisting of the common short code used in the first step and the long code corresponding to the group short code for the maximum path specified in the second step as a coefficient, with respect to the received data Perform correlation processing. This correlation processing is sequentially performed for all 32 types of long codes. Further, the above processing is repeated while shifting the slot timing to obtain the delay profile of the third stage. The delay profile is used to determine the long code and its frame timing.

In the second detection step, after registering the maximum path in the code list, attention is paid to the path having the next highest level in the delay profile of the first stage. At this time, the paths included in the delay profile of the third stage are removed.
Next, the second and third steps of the first detection process are performed on the path having the next highest level to obtain the long code and the timing / delay profile for that path. Hereinafter, in the same manner, up to 20 effective control channels are registered in the code list.

In the third detection step and the path search, the reception data of 3 symbol time is stored in the RAM and is received by the complex matched filter having the code consisting of the short code and the long code of the peripheral sector or diversity handover branch as the coefficient. Correlate the data.
At this time, the correlation values are synchronously added to create a delay profile. When performing cell search and path search at the same time during three-diversity handover communication, 10 types of delay profiles are created in consideration of two received signals.
To create these delay profiles, the complex matched filter calculation is executed by repeatedly using the received data stored in the RAM.

As described above, cell search and path search are performed in the wireless communication system.

[0010]

In the above method, a complex matched filter capable of processing only one type of code at the same time is basically used for the first and third steps of the first detection step and the path search processing. ing. However, this complex matched filter is not always suitable for the synchronization processing of the base station asynchronous system which needs to identify the long code by checking the correlation with many kinds of long codes.
In fact, it is thought that it has the following problems.

(1) Increase in processing time Since the complex matched filter is a relatively large-scale circuit,
It is difficult to provide a large number for downsizing the device.
Therefore, the operation using these must necessarily be executed sequentially. Therefore, the calculation time inevitably increases. This becomes remarkable in a synchronization holding process for creating delay profiles of many control channels.

(2) Increasing the circuit scale Since many of the processes using the complex matched filter must be executed sequentially, it is necessary to compare a plurality of delay profiles at a certain time. Synchronous holding requires a memory that stores received signals.

(3) Increase in power consumption Increase in processing time and circuit scale inevitably increases power consumption. In particular, in the third detection step of creating a delay profile while sequentially changing the code and in synchronization holding, a large amount of filter coefficients (by short code and long code) and received data are transferred from the memory to the matched filter each time the code is changed. Moreover, the peak current becomes extremely large.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a CDMA synchronizer capable of reducing the processing time, the circuit size, and the power consumption.

[0015]

SUMMARY OF THE INVENTION The essence of the present invention is to reduce the calculation time such as long code identification by processing a plurality of correlators in parallel in the configuration of the synchronization unit of the communication terminal device in the inter-base station asynchronous system. To reduce power consumption. The CDMA synchronizer of the present invention uses a plurality of complex correlators for a baseband signal extracted from a received signal, and shifts the operation timing of each complex correlator by one chip to perform a matched filter operation. A square-law detection means for square-law detecting the matched filter calculation result, and receives using the detection result of the square-law detection means.
CDMA that performs a plurality of synchronization processes for a received signal in parallel
A synchronization device, wherein the plurality of synchronization processes include synchronization acquisition and acquisition.
And each synchronization process in synchronization tracking, and for each synchronization process
While changing the allocation of the complex correlator to be used,
It adopts a configuration that performs period acquisition and synchronous tracking . CD of the present invention
The MA synchronizer adopts a configuration that suppresses an increase in operation code length by performing a low-pass filter process and a square root operation process for suppressing an unnecessary spectrum with respect to the output voltage of the square detection means by using a codec circuit. .
The CDMA synchronizer of the present invention extracts the path candidate of the received signal by detecting the maximum value of the envelope power signal obtained by the square detection means, and then detects the path of the received signal from the path candidates. The configuration is further provided with a path detecting means for The CDMA synchronizer of the present invention uses a plurality of correlators that form the correlation processing means, shares a plurality of correlators to form one DLL circuit, and
A circuit is used to control the correlation processing timing of the correlation processing means.

[0016]

DETAILED DESCRIPTION OF THE INVENTION

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of a wireless communication system including a CDMA synchronization device according to an embodiment of the present invention. The C of the present invention
The DMA synchronizer performs synchronization as described later as synchronization processing.
Performs acquisition processing, synchronization holding processing, and out-of-sync detection processing.
As described above, in the following embodiment,
Taking the name of the synchronization acquisition process, which is a typical process of the
We will call it the term acquisition device. On the base station side, the control unit 101 performs the error correction coding / decoding unit 1 so as to perform the error correction coding process and the error correction decoding process of the transmission data.
02 is controlled. The signal that has been subjected to the error correction coding processing is subjected to normal wireless transmission processing in the transmission section 103 and transmitted from the antenna 105. Also, antenna 1
The signal received via 05 is sent to the receiving unit 104,
After the normal wireless reception process is performed, the error correction code / decoding unit 102 sends the error correction code.

On the terminal side equipped with the synchronization acquisition device according to the present invention, the signal received from the antenna 106 is sent to the modulation / demodulation processing unit 107 and the synchronization processing unit 109, and demodulation processing and synchronization processing are performed respectively. That is, while the synchronization processing unit 109 performs synchronization acquisition and synchronization holding,
Modulation / demodulation processing unit 107 and error correction / voice codec unit 1
At 08, the signal is converted to voice and output from the microphone / speaker 111. Also, when sending audio,
The voice input from the speaker 111 is voice-encoded by the error correction / voice codec unit 108, and the modulation / demodulation processing unit 10
After being modulated at 7, the signal is transmitted from the antenna 106. The modulation / demodulation processing unit 107, the error correction / speech codec unit 108, and the synchronization processing unit 109 are controlled by the control unit 110.

This synchronization processing unit 109 has the configuration shown in FIG. FIG. 2 is a block diagram showing the configuration of the synchronization acquisition device according to the present embodiment. Here, 16 ksps
A case will be described where a control channel signal in which a symbol is spread 256 times at 4.096 Mcps is oversampled at 16.384 MHz and received.

In the figure, the received signal is subjected to predetermined radio reception processing via an antenna and then input from two terminals as in-phase (I) component and quadrature (Q) component baseband signals, respectively. . These baseband signals are
After being pre-processed by the fourth-order comb filter 201, the codes generated by the code generators 203, 204, 206 are processed in parallel by the 256 correlators 202, 207.

When a matched filter is used as the correlation processing means, a matched filter (0th-order hold type) for quadruple oversampling is preprocessed by the 4th-order comb filter 201 to reduce the number of adders to 1. / 4
Can be reduced to This also applies when a correlator is used in the correlation processing section. Therefore, also in the present embodiment, the number of adders can be reduced to 1/4 by preprocessing with the fourth-order comb filter 201.

In the first stage processing in the first detection step of the cell search, the code used in each of the correlator groups 202 and 207 is generated by the code generator.
The operation is performed by delaying each sample. This process is equivalent to the matched filter. The outputs of these correlators are sequentially selected at 16.384 MHz and input to shift registers 213 and 214 for one symbol time length via the voltage output square-law detection filters 208 and 209 and adders 210 and 211, and are synchronized. Is added. Thereby, a delay profile can be created. Note that this processing is sequentially performed for each input of the reception signals I and Q. The voltage output squared detection filters 108 and 109 are necessary when the envelope detection algorithm is introduced into the detection method, and suppress harmonic distortion.

The output from the shift register 213 is sent to the path detection filter 217, and the path detection filter 217.
Then, the extreme value as a path candidate is extracted from the contents of the shift register 213 which is the correlator output or the average result thereof, and only the path amplitude and time are transmitted to the DSP software. The counter 218 is a timer that measures only the length of the shift register, and the D-FF 219 is a flip-flop that uses the detection signal indicating that the path has been detected by the path detection filter 217 and the counter output.

The selector 212 selects (switches) between the output from the adder 211 and the output from the shift register 213, and the selector 216 outputs from the shift register 213 and the output from the shift register 214. Select (switch) between and.

Further, in the second stage processing in the first detection step, the correlator group 20 having 120 correlators is used.
Only 32 out of 7 are used to simultaneously examine the correlation between the received signals I and Q for 4 types of group short codes. Similarly, in the process of the third stage in the first detection process, the correlator group 2 having 120 correlators is used.
In addition to 07, eight correlators (corresponding to two codes) with a code generator are used to simultaneously examine the correlation between the received signals I and Q for 32 codes.

In the third detection step and the path search,
Using 60 correlators of the correlator group 207 having 120 correlators, a maximum of 30 paths (for example, cell search 2
Waves and path search 3DHO branches form a DLL for a total of 5 base stations × 6 paths = 30 paths) to follow a minute delay variation of each path caused by ray aging. On the other hand, other correlators simultaneously create 10 types of delay profiles (because there are received signals I and Q) from 5 base stations in parallel while making partial divisions. As described above, since the correlator is used as the correlating means instead of the matched filter, the path tracking and the path detection can be processed in parallel. As a result, it is possible to detect a better path while tracking the acquired path.

The synchronization acquisition device having the above configuration will be described in more detail. In the synchronization acquisition apparatus according to this embodiment, as described above, the correlation processing is performed using the correlator instead of the matched filter. For example, a 1024-tap matched filter operates with a shifted timing.
It is equivalent to four correlators. This configuration can be realized by providing a selector that sequentially switches the output of the correlator. At this time, it is sufficient to enable only one output while shifting the control pulse. If there is no increase in the number of circuits, the number of filters, correlators, the number of adders, and the number of memories are the same, so the circuit scales are considered to be equivalent.

Since QPSK is often used in data modulation used in an actual CDMA radio communication system, both the input signal and the despreading code have two sequences,
A complex correlator is needed. As this complex correlator, a correlator that performs envelope detection processing is used. FIG. 3 shows a part of the configuration of the synchronization acquisition device used in this case. In addition,
Regarding envelope detection, Japanese Patent Application No. Hei 9
No. 307825 (JP-A-11-127133)
It is disclosed in. This content is also included here.

The synchronization acquisition apparatus shown in FIG. 3 is basically the same as the synchronization acquisition apparatus shown in FIG. 2. In the synchronization acquisition apparatus shown in FIG. 3, instead of the correlator output bus shown in FIG. It uses a selector. That is, this synchronization acquisition device is for inputting a correlator 301, a code generator 302 that generates a code to be input to the correlator 301, and a code generated by the code generator 302 to the correlator 301 while shifting the timing. A delay unit 303, a selector 304 for switching the output from the correlator 301, and a selector 304
Squaring circuit 305 for squaring detection of the signal output via
And L that removes unnecessary signals from the signal after square-law detection
The PF 306, a square root arithmetic circuit 307 for converting the electric power value obtained by the square-law detection into a voltage value, and a square root arithmetic circuit 30.
7 and an averaging circuit 308 for averaging the voltage values of a plurality of samples obtained in 7.

Since the correlator 301 is a complex correlator as described above, an adder / subtractor and a register (two series) are required for the Q component and the I component, respectively. In the present embodiment, by using the correlator configuration as shown in FIG. 4, that is, two adder / subtractors 401 and 402 and one EXOR are provided.
By configuring with the circuit 403 and the four delay devices 404, the registers required for the normal complex correlator can be one series, and the circuit configuration can be simplified. Note that the configuration shown in FIG. 4 is a configuration for confirming that it operates as a complex correlator, and includes X, Y, Cx, and C.
y is used to perform a logical operation. As can be seen from the logic table shown in FIG. 4, the correlator having the configuration shown in FIG. 4 operates as a complex correlator. In the figure, 405 is 1,-
A multiplier for alternately multiplying by 1 is shown.

In the averaging circuit 308, for example, 16
The square-law detection output that is output in a kHz cycle is averaged to eliminate fluctuations, and the delay profile is correctly measured. For example, the correlator 301 shown in FIG. 3 has 256 correlation circuits shown in FIG. 4, which output 4 samples once at 16 kHz while being delayed by the 16.384 MHz clock. While these outputs are sequentially selected, the amplitude values are obtained by suppressing the unnecessary spectrum by the square detection filter described later.

For example, the averaging circuit is 16.384 MH.
The z operation is composed of a shift register of 1 symbol time length (1024 stages), and performs averaging by synchronous addition at 16 kHz intervals. In this case, it is necessary to consider a 4-sample delay due to the square-law detection filter when averaging. Further, in order to average only a part of the delay profile, it is preferable to operate with an appropriate burst clock while varying the shift register length.

Next, the voltage output square detection filters 208 and 209 shown in FIG. 2 will be described. The voltage output square detection filters 208 and 209 shown in FIG. 2 have the configuration shown in FIG. The voltage output square wave detection filter shown in FIG. 5 includes a square wave detection circuit 501 that square-squares the output from the correlator,
Delay device 502 that shifts the timing of input to the CORDIC circuit
And a plurality of stages of CORDIC circuits 503 that perform CORDIC operations on the output from the square detection circuit 501.

In a synchronous circuit based on squared detection, the output is the squared value of the envelope amplitude. Therefore, when this output is input to the averaging circuit as it is, in order to maintain the same dynamic range as when the amplitude is averaged, , The required memory word length is 2
It will be doubled. This is because the voltage value is 6 dB for 1 bit and the power value that is the square of the voltage value is 3 dB for 1 bit.

Therefore, it is necessary to perform a square root operation before inputting the output of the synchronizing circuit to the averaging circuit to restore the voltage value. However, when the processing is performed while suppressing the calculation error, the word length is doubled by the square calculation. Then, at the final square root circuit, the original word length is restored. Therefore,
The LPF operation after the square operation must be performed in a long word length state. Performing such processing increases the number of arithmetic circuits.

In the voltage output square-law detection filter shown in FIG. 5, the CORDIC circuit is used to simultaneously perform the 8th-order comb filtering and the square root calculation for suppressing the unnecessary spectrum of the square-law detection. That is, CORDIC circuit 5
03 performs the processing in the squaring circuit 305, the LPF 306, and the square root calculation circuit 307, so that the 8th-order comb filtering and the square root calculation can be performed at the same time. Since this circuit uses the CORDIC algorithm to perform operations with voltage values from input to output, highly accurate results can be obtained without the above-mentioned increase in operation word length.

Next, the path detection filter 217 shown in FIG.
Will be described. The path detection filter 217 shown in FIG.
"When oversampling at 4 times the chip rate,
The path is extracted from the delay profile based on the rule of "maximum value observed including four samples before and after".

This determination is performed by DSP software processing, but it requires transfer of all delay profile data and a large amount of calculation, which is a disadvantageous factor for reducing power consumption. Therefore, in the present embodiment, the path detection filter having the configuration shown in FIG. 6 is used. This path detection filter satisfies the above rule and detects a maximum value.

The path detection filter shown in FIG. 6 is a delay device 60 that shifts the input timing of the output from the shift register.
1 and a MAX selector 603 that obtains the maximum value by selecting a larger one between the output from the shift register and the current output that were previously input, and COMP that performs comparison between the maximum value and the effective threshold value. A selector 602. In addition, FIG.
A medium 604 is a counter that is a timer that measures the time when the path is detected.

This path detection filter compares the maximum values of the preceding 4 samples and the following 4 samples with the current sample value,
When the current sample value is the maximum (and a certain value or more), the current sample value can be sequentially output.

In this path detection filter, by starting the operation of the counter 604 at the start of the processing operation and simultaneously outputting the counter value at the time of sample output, not all data of the delay profile but its maximum value and time Send only to the DSP. As a result, the amount of data sent to the DSP is significantly reduced. Then, as the DSP software processing, only the processing that requires random access, such as selecting the largest one from the extracted paths (maximum values) or rearranging the largest ones, may be performed. As described above, only the process that requires random access to the memory is performed by software, and the process that can be performed by sequential access (shift register or the like) is realized by hardware as much as possible, so that low power consumption can be achieved.

Next, the DLL control unit 215 shown in FIG. 2 will be described. The timing of the path detected by the cell search changes slightly due to fading or deviation of the transmission / reception clock frequency. DLL (Delay Lock Loop)
Pays attention to the fact that the autocorrelation function of the spreading code is symmetrical as shown in FIG. 8, and adjusts the spreading code generation timing so that the correlation values before and after the regular timing are equal. In this embodiment, as shown in FIG. 7, the correlator group 207 and the DLL circuit are commonly used. FIG. 7 is a diagram showing the relationship between the correlator group 207, the shift register 214, and the DLL control unit 215 in the synchronization acquisition device shown in FIG.

The DLL time constant can be adjusted by the averaging time in the averaging unit of the DLL control unit 215. In addition, DL
The reason why the four correlator circuits are assigned to one L control unit 215 is that the correlation value of the triangular portion including two points used for the DLL control shown in FIG. Is to calculate correctly.

Each DLL control section 215 outputs a correlation value at an appropriate 16 chip time within one symbol time. DLL
The averaging unit of the control unit 215 rearranges the data in the shift register in advance during the non-output time, and synchronously adds the squared detection filter output while restarting the output and the shift register.

As described above, the DLL control unit 215 has 16
Since it can be regarded as operating at kHz sampling, 8
It is possible to control fluctuations up to kHz. Each path that is a small part of the delay profile can be regarded as a kind of narrow band signal, and its fluctuation speed is about several hundred Hz of the maximum Doppler frequency of Rayleigh fading,
This is a sufficient value.

On the other hand, as can be seen from FIG. 8, the DLL control unit 215 correctly determines the control amount (timing adjustment direction) because the correlation value of the circle is in the triangle even if ± 1/2 chips are deviated. Can be determined. This means that, on the contrary, when starting the DLL processing, the initial value of the generation time of the code generator must be set with an accuracy within ± 1/2 chip. This is the path detection accuracy required for the first stage processing in the first detection step.

Further, in this DLL configuration, since the circuit is shared with the correlator, if the DLL circuit is once stopped and other processing is executed, the contents of the correlator of the DLL circuit up to that point. Is cleared. Therefore, DL again
In order to perform L, it is basically necessary to re-draw in the first stage process in the first detection step. The time when the DLL circuit can be stopped in such a case is the time required to shift the path timing by 1/2 chip due to the Doppler shift due to the transmission / reception clock frequency shift and movement.
It is thought that it will take about 1 second when running 30 km.

In the synchronization acquisition device having the above structure,
The case of actually performing a cell search or a path search will be described. In the neighboring cell search and path search, the types of delay profiles that must be created (maximum value is 5 base stations x 2 antennas = 10 types) and the number of complementary paths (maximum value is 5 base stations x 6 = 30 passes)
Since there are many combinations of, each will not be examined here and only the case where each is the maximum will be described.

(1) First Stage Process in First Detection Step of Cell Search In the first stage process of the conventional method, in order to detect the slot timing, one slot, that is, a memory of 10 symbol length (= 10 Mword). Actually, the sampling frequency is halved and synchronous addition is performed using 5 Mword. The slot timing is detected based on the addition result, and the delay profile of the long code mask symbol portion at this slot timing is created.

In the processing procedure according to the present embodiment, in order to reduce the required memory, the correlator group 202, the path detection filter 217 and the 1-slot cycle counter 218 in FIG. Only work.

As shown in FIGS. 9 and 10, since the maximum value of the correlator output and its time are output from the path detection filter 217, the DSP detects the long code mask symbol time (which is necessary for this detection). The observation time is considered to be 1 or 2 slots). Next, only in the detected long code mask symbol time, the correlator groups 202, 2
07, the shift registers 213 and 214 are operated to perform correlation processing, and the correlation results are averaged a predetermined number of times to create a delay profile. At the last one symbol of the averaging process, the path detection filter 217 is also operated to detect the path. It should be noted that this process is sequentially performed for the two receiving antennas. In this way, since the correlation processing is performed only in the detected long code mask symbol time and the processing is stopped in the other time, it is possible to reduce the power consumption.

(2) Processing of the second and third steps in the first detection step of the cell search The processing of the second and subsequent steps is different in the sector in the delay profile created by the common search code in the first step. Only the paths are distinguished, each long code and frame timing are identified, and the received power of the maximum path is measured. Here, the received power includes SIR and is a known reference symbol (eg, pilot symbol) in a slot.
It is necessary to measure using the information of. This measurement requires about 16 slots = 1 frame. In the conventional process, the delay profile is created in order from the largest path detected in the first stage to exclude paths in the same sector.
This method has a problem in that the number of times the delay profile is created increases and the processing time and power consumption increase.

In the apparatus according to the present embodiment, the correlation processing unit is composed of a correlator capable of parallel processing. Therefore, when the code start time is known, a feature that a plurality of codes can be processed in parallel is provided. Making full use of this, processing is performed as shown in FIG.
Basically, the information is repeatedly used in the expectation that the delay profile detected in the first stage is relatively stable. This eliminates the need to create a delay profile, which was created by the iterative process using the matched filter in the third-stage process of the conventional configuration, and eliminates the need for a 9 kbyte storage memory.

First, at the slot timing of the path a0 (FIG. 10), which has the maximum amplitude in the delay profile of the first stage, the second stage processing is performed simultaneously in the part of the correlator group 207 and the shift register 214 for four codes. Perform processing to identify long code groups. Here, the long code mask symbol is received only once, and the processing of the second stage is ended.

Next, the 32 codes belonging to that long code group are assigned the third code according to the slot timing of the path a0.
Step processing is performed by a part of the correlator group 207 and the shift register 2.
Run at 14. In the third stage, the slot timing for receiving at least one frame and obtaining the maximum correlation value is detected as the frame timing while repeatedly generating the target long code in one slot cycle. Here, it is assumed that the third stage requires one frame time.

Next, attention is focused on the second largest path a1, which may be a delayed wave of the path a0. Therefore, the code of the path a0 is generated at the slot timing of the path a1 and the correlation value is calculated. If the correlation value is large, it is determined to be a delayed wave, and if the correlation value is small, the control channel is in a sector different from that of the path a0. judge. In addition,
If the path is a delayed wave, there is no time difference of more than 1 slot,
That is, if there is a delay of 1 slot or more, it is a different sector of the same cell, so this path determination process does not require determination time for one frame as in the third stage. Further, this path determination process can be executed if there is one correlator. Therefore,
At this time, the second-stage processing for the path a1 can also be executed at the same time.

In the example of FIG. 11, since the path a1 is the delayed wave of the path a0, the processing is stopped, and the path determination and the second stage processing are performed for the next largest path b0. Path b
Since 0 is an independent path, the process proceeds to the third stage as it is, and the reception level of the path b0 is measured in parallel using the frame timing of the path a0 at this time. In the third stage, since the long code for the first slot at the beginning is repeatedly generated, pilot symbols in all slots cannot be received correctly. Therefore, the reception level must be measured by generating the long code of the frame period after the process of the third stage, and it is considered that about 1 frame (16 slots) is required as the measurement time. It is preferable to perform it simultaneously with the processing of the third stage of the next pass.

In the process of the first stage, the process is repeated for each receiving antenna, but in the processes of the second and third stages, the process is performed while paying attention to a large path. That is, it suffices to create delay profiles corresponding to the number of antennas in the first-stage processing, and use this delay profile to perform level measurement processing in the order of large paths. Such processing can be executed only by selecting which of the inputs of the correlator is capable of parallel processing. Therefore,
The level measurement process can be easily performed for each pass.

(3) Third detection step of cell search and path search For example, when the cell search processing is simultaneously performed at the time of 3-diversity handover, RAK is performed using up to 30 paths.
Since E synthesis is performed, these fine timing fluctuations are tracked by the DLL circuit, and at the same time, the delay profile of the path that is a candidate for the path of the desired wave is measured using another correlator. This is because the correlation processing unit is composed of a plurality of correlators, which can reduce the processing time in cell search. Since the DLL circuit and the delay profile correlator operate at independent timings, a square-law detection filter is also prepared separately.

For example, referring to FIG. 2, the DLL
Then, the output from the correlator group 207 is input to the shift register 214 via the voltage output square detection filter 209 and the adder 211. The output from the shift register 214 is fed back to the adder 211.

On the other hand, for the delay profile creation,
The output from the correlator group 202 is passed through the voltage output square detection filter 208 and the adder 210 to shift register 213.
Entered in. The output from the shift register 213 is fed back to the shift register 214 via the selector 212, the shift register 214, and the selector 216. The output from the shift register 213 is the adder 2
Input to 10.

Further, since the delay profile correlator creates 5 types × 2 antennas = 10 types of delay profiles, the delay profile correlator is divided into 10 and is operated in parallel by the five code generators. Each part divided at this time measures only part of each delay profile, but any part can be measured by controlling the code generation timing.

However, the outputs of these delay profile correlators must be continuously input to one square-law detection filter at 16.384 MHz so that path detection can be performed all at once. Such timing restrictions are
The more delay profiles that are measured, the tighter the constraint. Further, considering the 4-sample delay of the square-law detection filter, it is necessary to insert 0 for 4 samples at the boundary of each divided portion so that they do not overlap each other by filtering.

In the above description, the case where each delay profile is measured little by little at the same time is explained, but it is also possible to measure the delay profile one by one. In this case, the control is much easier and the efficiency of using the circuit is improved.

As described above, in the synchronization acquisition apparatus according to the present embodiment, the correlation processing section is composed of the correlators and the correlators are used in common, so that various processes in cell search and path search can be performed. Can be run in parallel. Therefore, the processing time can be shortened, the circuit scale can be reduced, and the power consumption can be reduced.

The synchronization acquisition apparatus according to this embodiment can be applied to a communication terminal apparatus such as a mobile station in a digital radio communication system.

The above embodiment is merely an example of the present invention, and various modifications can be made without departing from the scope of the present invention.

[0083]

As described above, the CDMA system of the present invention is the same.
The synchronization device uses a plurality of complex correlators for the baseband signal extracted from the received signal and operates the operation type of each complex correlator.
Matching filter operation by shifting the chip by 1 chip
Correlation processing means to perform and square the matched filter calculation result
A square-law detection means for detection is provided to detect the detection of the square-law detection means.
Parallel processing of multiple received signals using the result
Since the processing is performed, the processing time can be shortened, the circuit scale can be reduced, and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a wireless communication system including a synchronization acquisition device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a synchronization acquisition device according to the above embodiment.

FIG. 3 is a block diagram showing details of the synchronization acquisition device shown in FIG.

FIG. 4 is a block diagram showing an internal configuration of a correlator in the synchronization acquisition device according to the above embodiment.

FIG. 5 is a block diagram showing an internal configuration of a voltage output square-law detection filter in the synchronization acquisition device according to the above embodiment.

FIG. 6 is a block diagram showing an internal configuration of a path detection filter in the synchronization acquisition device according to the above embodiment.

FIG. 7 is a diagram of D in the synchronization acquisition device according to the above embodiment.
Block diagram showing the configuration of the LL circuit and the correlator

FIG. 8 is a diagram for explaining DLL control.

FIG. 9 is a timing chart for explaining the processing of the first stage in the first detection step of cell search.

FIG. 10 is a diagram showing delay profiles in cell search and path search.

FIG. 11 is a timing chart for explaining the processes of the second stage and the third stage in the first detection process of the cell search.

[Explanation of symbols]

201 4th order comb filter 202,207 Correlator group 203,204,206 Code generator 208,209 Voltage output square detection filter 210,211 adder 212,216 Selector 213, 214 shift register 215 DLL control unit 217 Path detection filter 218 counter

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-4-77022 (JP, A) JP-A-3-88526 (JP, A) JP-A-1-125668 (JP, A) JP-A 2000-68897 (JP, A) JP 10-126380 (JP, A) JP 10-94041 (JP, A) JP 10-145334 (JP, A) JP 8-56384 (JP, A) Kaihei 6-244820 (JP, A) JP-A-9-64783 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 13/00-13/06 H04B 1/69- 1/713

Claims (4)

(57) [Claims] 1. Correlation processing means for performing a matched filter operation by shifting the operation timing of each complex correlator by one chip using a plurality of complex correlators for a baseband signal extracted from a received signal, and the match. comprising a square detection means for square-law detection bets filter operation result, said square
Using the detection results of the detection means, multiple
A CDMA synchronizer which performs synchronization processing in parallel,
The multiple synchronization processes are the same for synchronization acquisition and synchronization tracking.
The complex correlator used for each synchronous process
The synchronization acquisition and synchronization tracking are performed while changing the allocation of
A CDMA synchronizer characterized by the following. 2. The output voltage of the square-law detection means,
A low-pass filter process for suppressing unnecessary spectrum and a square root operation process are performed using a codec circuit, thereby suppressing an increase in operation code length.
The CDMA synchronizer according to claim 1 . 3. A path detection for extracting a path candidate of a received signal by detecting a maximum value of an envelope power signal obtained by the square detection means, and then detecting a path of the received signal from the path candidates. The CDMA synchronizer according to claim 1 , further comprising means. 4. A plurality of correlators forming the correlation processing means are used, a plurality of correlators are shared to form one DLL circuit, and the DLL circuit controls the correlation processing timing of the correlation processing means. The CDMA synchronizer according to any one of claims 1 to 3, wherein .