JP2001250918A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC for switching power supplies that has the small number of parts, low manufacturing costs, and a soft start function. SOLUTION: An input-stage circuit 2 is composed of a p-channel MOSFET 3 and a resistor R3, and the output current of the input stage circuit is narrowed with time when power is turned on, thus achieving a soft start function. In this case, the input-stage circuit that is composed of a conventional voltage follower circuit and an inverting amplification circuit is composed by one MOSFET or a two-stage current mirror circuit, thus greatly reducing the number of the parts, and hence reducing manufacturing costs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit for a switching power supply or the like, and more particularly to a semiconductor integrated circuit having a function of soft-starting a switching power supply or the like.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a switching power supply circuit having a soft start function. This configuration diagram shows a semiconductor integrated circuit 51 for a switching power supply.
(Hereinafter referred to as IC) and external CR circuits 59a,
9b, the C circuit 60, the FB circuit 57, and the IC 51
, A transformer 53, a DC power supply 58, a diode (not shown) connected to the output side of the transformer 53, an output voltage detector 55, and a feedback signal from the output voltage detector 55. And a photo coupler 56. Reference numeral 54 in the figure denotes a load. VDD is the power supply voltage of the IC 51. still,
C represents a capacitor, R represents a resistance, and FB represents feedback.

In FIG. 4, after the switching power supply circuit is activated (after the power is turned on), the power supply voltage VDD of the IC 51 rises in a short time and reaches the ultimate voltage.
1, the voltages of C52 and C53 gradually increase. At this time, a rectangular wave voltage whose pulse width increases with time is output from the OUT terminal of the IC 51, and this rectangular wave voltage is M
When given to the gate of the OSFET 52, the transformer 53
The power supplied to the load 54 via the power supply increases with time. That is, after the power is turned on, the power supply to the load 54 is soft-started.

When the voltage supplied to the load 54 decreases, the photocoupler 56 operates with the detection voltage output from the voltage detector 55, and the output current of the photocoupler 56 decreases. The reduced current is input to the FB circuit 57, and a low voltage is output from the FB circuit 57 to the FB terminal. When this low voltage is received by the IC 51, a rectangular wave voltage having a wide pulse width is output from the OUT terminal, and the load 5
The supply voltage to 4 is increased to compensate for the voltage drop, and a constant voltage is constantly supplied to the load.

FIG. 5 is a circuit diagram of a conventional switching power supply IC. This IC 51 includes a voltage follower circuit 63 composed of an OP amplifier 65 (operational amplifier),
An inverting amplifier circuit 64 composed of an OP amplifier 66;
Vibrator 67, second vibrator 68, diodes D61, D62, resistors R61, R62, R63
And a semiconductor chip 61 on which an AND circuit 70, a buffer circuit 71, and a clock circuit 69 are formed, and terminals connected to the semiconductor chip 61 by bonding wires. Each terminal is connected to an external RC circuit 59a, 5
CS terminal connected to the connection point of the resistor and the capacitor of 9b,
A CR1 terminal, a CR2 terminal, an OUT terminal as an output terminal, and a feedback signal are supplied to the photocoupler 56 and the FB.
And an FB terminal for transmission to the semiconductor chip 51 via the circuit 57.

FIGS. 6A and 6B show operation waveforms of the circuit shown in FIG. 5. FIG. 6A shows the waveform at each point, and FIG. 6B shows the waveform at point f in FIG. It is a representation. 4 and 5
The operation of the IC 51 and the waveform of each part will be described with reference to FIG. 6 and FIG. When the power is turned on, the CR circuit 5 that gradually rises from the CS terminal at point a to the voltage follower circuit 63
The voltage of the capacitor C51 of 9a (the waveform at point a in FIG. 6A) is input. The voltage at point b, which is the output voltage of the voltage follower circuit 63 (waveform at point b in FIG. 6A)
Gradually rises, and this voltage is input to the inverting amplifier circuit 64. During a period until this voltage exceeds the reference voltage E, a constant high voltage (VDD) is output. The voltage at point c, which is the output voltage of the inverting amplifier circuit 64, decreases as the voltage of the capacitor C51 increases (the waveform at point c in FIG. 6A).

The voltage at point d is the voltage of C53. Until the clock signal output from the clock circuit 69 is input to the first vibrator 67, the voltage is charged from VDD via R63, and the voltage of VDD is Has become. When the clock signal is input to the first vibrator 67, the first vibrator 67 operates to discharge C53. Therefore, the voltage at the point d decreases. When this voltage reaches a predetermined value, the discharge to the first vibrator 67 stops, a charging current flows from the input stage circuit 62 to C53, the voltage at point d rises, and returns to VDD again. At this time, since the supply voltage to the load is small, the contribution of the inflow current from the FB terminal is extremely small.

The rate of rise of the voltage at point d depends on the magnitude of the current from input stage circuit 62. The magnitude of this current is c
Depends on the voltage at the point. Therefore, in a region where the voltage at the point c decreases with time, the rate of increase of the voltage at the point d decreases with time. Therefore, the voltage drop period at point d is
It expands with time (the waveform at point d in FIG. 6A). The voltage at the point d and the clock signal from the clock circuit 69 (the waveform of ck in FIG. 6A) are supplied to the first vibrator 67.
Is input to the Q terminal of the first vibrator 67,
In synchronism with the clock signal, during the period when the voltage at the point c is VDD, a signal having a narrow constant pulse width, and during the period when the voltage at the point c decreases with time, the pulse width (W1) (c
A rectangular wave signal in which the falling period of the point is enlarged is output (the waveform at point e1 in FIG. 6A).

On the other hand, the voltage of C52 is charged via R52 until the clock signal is input to the second vibrator 68, and becomes the voltage of VDD. When the clock signal is input, the second vibrator 68 operates, and C
52 is discharged. Therefore, the voltage of C52 decreases. When this voltage reaches a predetermined value, the discharge to the second vibrator 68 stops, a charging current flows through R52, the voltage of C52 increases, and returns to VDD again. The rate of increase of the voltage of C52 is determined by the time constant of C52 × R52 and is constant. Therefore, the voltage drop period of C52 is also constant.

When the voltage of C52 and the clock signal are input to the second vibrator 68, the second vibrator 68
6A, a rectangular wave signal having a constant pulse width (W2) is output from the Q bar terminal in synchronization with the clock signal and having a phase opposite to that of the output signal from the Q terminal (point e2 in FIG. 6A). Waveform). When the rectangular wave signal output from the Q terminal and having a gradually widening pulse width and the rectangular wave signal output from the Q bar terminal and having a constant pulse width are input to the AND circuit 70,
The output signal of the AND circuit 70 has a period during which the pulse width of the Q rectangular wave signal is smaller than the pulse width of the Q bar rectangular wave signal.
When the pulse width becomes zero and increases, the pulse width (Δ
A rectangular wave signal whose W gradually spreads is output (FIG. 6).
(A) The waveform at point f). This signal is input to the buffer circuit 71, and from the buffer circuit 71, the MOSFET 5 in FIG.
2 is shaped into a gate signal that can be driven and output to the OUT terminal. From this OUT terminal, the initial pulse width is zero,
A rectangular voltage whose pulse width gradually increases is output. When the MOSFET 52 is driven by this rectangular wave voltage, as described above, a gradually increasing power is supplied to the load 54,
The power supply to the load 54 is soft-started.

As described above, in the steady state, when the voltage supplied to the load 54 decreases, the feedback voltage applied from the FB terminal also decreases, so that C5
3, the pulse width of the output voltage from the OUT terminal increases. As a result, a voltage that compensates for the reduced voltage is supplied to the load 54, and the supply voltage to the load returns to a constant voltage.

[0012]

In the conventional semiconductor integrated circuit described above, the soft start function is provided in a circuit composed of a voltage follower circuit and an inverting amplifier circuit. However, the number of parts constituting these circuits is as large as several tens. Therefore, the conventional semiconductor integrated circuit has a high manufacturing cost.

An object of the present invention is to provide a semiconductor integrated circuit having a soft start function which has a small number of parts and a low manufacturing cost by solving the above-mentioned problems.

[0014]

In order to achieve the above-mentioned object, an input stage for applying a power supply voltage to an external first CR circuit and an external second CR circuit, respectively, and applying a first capacitor voltage constituting the first CR circuit. A circuit, a first vibrator that applies an output voltage and a feedback voltage of the input stage circuit to an external capacitor via respective resistors, and outputs a positive-phase first signal based on the external capacitor voltage and a clock signal; A second vibrator for outputting a second signal having a phase opposite to that of the first signal based on a second capacitor voltage and a clock signal constituting the second CR circuit; and a logical sum of the first signal and the second signal And an AND circuit that outputs a pulse signal having a predetermined width in a predetermined time from the AND circuit. Te, wherein the input stage circuit is composed of a p-channel MOSFET, the p-channel MOSFET
A power supply voltage is applied to the source of the p-channel MOS.
The capacitor voltage of the CR circuit is applied to the gate of the FET, and from the drain of the p-channel MOSFET,
The output signal of the input stage circuit is output.

The input stage circuit is constituted by a two-stage current mirror circuit, a first stage current mirror circuit to which the power supply voltage and the capacitor voltage of the CR circuit are inputted, and an output signal of the input stage circuit. It is preferable to have a configuration including a second-stage current mirror circuit for outputting. The input stage circuit includes a two-stage current mirror circuit, and includes the power supply voltage and the CR.
A first-stage current mirror circuit to which a capacitor voltage of a circuit is input; and a second-stage current mirror circuit that outputs an output signal of the input stage circuit, wherein the feedback signal is the second-stage current mirror circuit. It is preferable that the input signal be input to the mirror circuit.

[0016]

FIG. 1 is a diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. Semiconductor integrated circuit (IC
1) shows a circuit diagram corresponding to a conventional IC 51 portion indicated by a dotted line. Further, the input stage circuit 2 corresponds to the input stage circuit 62 of FIG.
It is composed of SFET3 and resistor R3. The VDD terminal is connected to the source of the p-channel MOSFET 3, the CS terminal is connected to the gate of the p-channel MOSFET 3, the drain of the p-channel MOSFET 3 is connected to one end of the resistor R3, and the capacitor C1 is connected via the other end of R3 and the CR1 terminal. To one end of The function of the input stage circuit 2 is the same as that of the input stage circuit 62 in FIG. 5, but the number of components is greatly reduced to two. Therefore, the manufacturing cost can be significantly reduced.

In FIG. 1, when the power is turned on, the voltage of the capacitor C0 gradually increases. Therefore, a gate voltage of VDD-C0 is applied to the gate of the p-channel MOSFET 3. Since this gate voltage is higher than the threshold voltage, the p-channel MOSFE
T3 is turned on, and the p-channel MOSFET and R3
Flows into C1. When the voltage of C0 increases with time, the gate voltage decreases and the current flowing through p-channel MOSFET 3 is reduced. When the gate voltage further decreases and falls below the threshold value, the p-channel M
OSFET3 is turned off, and the current flowing through C1 stops.

The voltage at point h is initially VDD and has a waveform that decreases with time, and corresponds to the waveform after a certain area of the voltage at point c in FIG. Therefore, C1, the output of the first vibrator 4, the output of the second vibrator 5, and AND
The waveforms of the output of the circuit 6 are represented by points d, e1, and e in FIG.
The waveform is the same as the waveform of the two steps f. Therefore, a rectangular voltage having an initial pulse width of zero and a gradually increasing pulse width is output from the OUT terminal via the buffer circuit 7. When the MOSFET 52 is driven by this rectangular wave voltage, gradually increasing power is supplied to the load 54,
4 is soft-started.

The portions other than the input stage circuit 2 correspond to portions other than the input stage circuit 62 in FIG. 5, and D11 in the drawing is D6.
2, R11 is R62, R1 is R63, 4 is 67, 5 is 6
8, 6 correspond to 70, 7 to 71, and 8 to 69. Also,
In order to quickly start supplying power to the load, R3 in the figure may be deleted. FIG. 2 is a diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention. A portion corresponding to FIG. 1 has a two-stage current mirror circuit. VDD
The terminal is connected to the sources of the p-channel MOSFETs 21, 22, and 23, the CS terminal is connected to the gate of the p-channel MOSFET 21, and the drain of the p-channel MOSFET 21 is connected to the drain of the n-channel MOSFET 24.
Drain of n-channel MOSFET 24 and n-channel M
Connect to the gate of OSFET 25. p-channel MOS
The drain of the FET 22 and the gate of the p-channel MOSFET 23 are connected. The drain of the p-channel MOSFET 22 and the drain of the n-channel MOSFET 25 are connected. The source of the n-channel MOSFET 24, the source of the n-channel MOSFET 25, and the ground GND are connected. The drain of the p-channel MOSFET 23 is connected to one end of the resistor R21.

The first-stage current mirror circuit has a p-channel M
The second-stage current mirror circuit includes an OSFET 21, an n-channel MOSFET 24, and an n-channel MOSFET 25.
It comprises an SFET 23 and an n-channel MOSFET 25. The drain of the p-channel MOSFET 23 and the resistor R2
1 is connected. The input of the input stage circuit 20 is a p-channel MO
At the gate of SFET 21, the output is the other end of resistor R21.

Unlike FIG. 1, by changing the area of each MOSFET constituting the current mirror circuit, the input stage circuit 20 is changed.
(The drain current of the p-channel MOSFET 23) can be arbitrarily changed. As a result, it is possible to arbitrarily adjust the rate at which the drop period of the voltage of C1 connected to the CR1 terminal increases with time. This circuit has a larger number of components than FIG. 1, but is also greatly reduced as compared with the circuit of FIG. Therefore, the manufacturing cost can be reduced.

Incidentally, R21 in the figure may be deleted in order to quickly start supplying power to the load. FIG.
FIG. 10 is a diagram illustrating a semiconductor integrated circuit according to a third embodiment of the present invention. The FB circuit 10 and the photocoupler 11 connected to the FB terminal of the circuit of FIG. 1 are removed, and the p-channel M of the circuit of FIG.
P-channel MOSFET 32 corresponding to OSFET 22
This is a circuit in which a photocoupler 37 and an FB circuit 38, which are circuits for FB signal transmission, are added to and connected to the drain of FIG.
Incidentally, 31, 33, 34, 35 and R31 in the figure correspond to 21, 23, 24, 25 and R21 in FIG. 2, respectively.

The operation of the input stage circuit 30 when the power is turned on is the same as that of the input stage circuit 20 shown in FIG. In steady state, when the voltage applied to the load decreases,
The current flowing into the FB circuit 38 decreases, and the drain current of the p-channel MOSFET 33 decreases. This means that the output current of the input stage circuit 30 decreases. As described above, when the output current of the input stage circuit 30 decreases, the pulse width of the rectangular wave voltage output from the OUT terminal of the IC 1 increases, and the voltage supplied to the load increases. As a result, the voltage drop is compensated and a constant voltage is supplied to the load. This circuit has a significantly reduced number of components compared to the circuit of FIG. Therefore, the manufacturing cost can be reduced.

[0024]

According to the present invention, an input stage circuit composed of a conventional voltage follower circuit and an inverting amplifier circuit is provided.
By using one MOSFET or a two-stage current mirror circuit, the number of components can be greatly reduced. As a result, manufacturing costs can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 3 is a diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention;

FIG. 4 is a configuration diagram of a switching power supply circuit having a soft start function.

FIG. 5 is a circuit diagram of a conventional switching power supply IC.

6A and 6B are operating waveforms of the circuit of FIG. 5, in which FIG. 6A shows the waveform at each point, and FIG. 6B shows the waveform at the point f in FIG.

[Explanation of symbols]

Reference Signs List 1 IC 2 input stage circuit 3 p-channel MOSFET 4 first vibrator 5 second vibrator 6 AND circuit 7 buffer circuit 8 clock circuit 9 semiconductor chip 10, 38 FB circuit 11, 37 photocoupler 21, 22, 23, 31, 32, 33 p-channel MO
SFET 24, 25, 34, 35 n-channel MOSFET C0, C1, C2 Capacitor R0, R1, R2, R3, R11, R21, R31 Resistance D11 Diode

Continued on front page F-term (reference)

Claims (3)

[Claims] A power supply voltage is supplied to an external first CR circuit and a second CR circuit.
An input stage circuit for applying a first capacitor voltage constituting a first CR circuit, and an output voltage and a feedback voltage of the input stage circuit respectively applied to an external capacitor via a resistor; A first vibrator that outputs a first signal having a positive phase based on a voltage and a clock signal, and a second vibrator that has a phase opposite to the first signal based on a second capacitor voltage and a clock signal that form the second CR circuit. A second vibrator for outputting a signal, and an AND circuit for outputting a logical sum of the first signal and the second signal, wherein a pulse width increases with time after power-on, and a pulse signal having a predetermined width in a predetermined time Is output from the AND circuit, the input stage circuit is formed of a p-channel MOSFET, and the p-channel MOSF
A power supply voltage is applied to the source of ET, and the p-channel M
A semiconductor integrated circuit, wherein a capacitor voltage of the CR circuit is applied to a gate of an OSFET, and an output signal of an input stage circuit is output from a drain of the p-channel MOSFET. 2. The power supply voltage is supplied to an external first CR circuit and an external first CR circuit.
An input stage circuit for applying a first capacitor voltage constituting a first CR circuit, and an output voltage and a feedback voltage of the input stage circuit respectively applied to an external capacitor via a resistor; A first vibrator that outputs a first signal having a positive phase based on a voltage and a clock signal, and a second vibrator that has a phase opposite to the first signal based on a second capacitor voltage and a clock signal that form the second CR circuit. A second vibrator that outputs a signal; and an AND circuit that outputs a logical sum of the first signal and the second signal. The pulse width increases with time after power-on, and a pulse signal having a predetermined width is generated at a predetermined time. In the semiconductor integrated circuit outputting from the AND circuit, the input stage circuit is configured by a two-stage current mirror circuit,
A semiconductor device comprising: a first-stage current mirror circuit to which the power supply voltage and the capacitor voltage of the CR circuit are input; and a second-stage current mirror circuit that outputs an output signal of the input stage circuit. Integrated circuit. 3. The power supply voltage is supplied to an external first CR circuit and an external first CR circuit.
An input stage circuit for applying a first capacitor voltage constituting a first CR circuit, and an output voltage and a feedback voltage of the input stage circuit respectively applied to an external capacitor via a resistor; A first vibrator that outputs a first signal having a positive phase based on a voltage and a clock signal, and a second vibrator that has a phase opposite to the first signal based on a second capacitor voltage and a clock signal that form the second CR circuit. A second vibrator that outputs a signal; and an AND circuit that outputs a logical sum of the first signal and the second signal. The pulse width increases with time after power-on, and a pulse signal having a predetermined width is generated at a predetermined time. In the semiconductor integrated circuit outputting from the AND circuit, the input stage circuit is configured by a two-stage current mirror circuit,
A first-stage current mirror circuit to which the power supply voltage and the capacitor voltage of the CR circuit are input, and a second-stage current mirror circuit to output an output signal of the input stage circuit, wherein the feedback signal is A semiconductor integrated circuit which is input to the second-stage current mirror circuit.