JP2001238432A - Semiconductor power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a gate feedback signal, while original characteristics of a gate signal in a positive bias region are not impaired. SOLUTION: This semiconductor power converter has a gate drive circuit 20, which outputs a gate signal 25 of a gate positive bias voltage, when a gate control signal 22 is turned on and outputs a gate signal 25 of a gate negative bias voltage, when a gate signal is turned off to drive a semiconductor device 26. A gate negative bias detector 33 is provided, which detects the off-state of the semiconductor device 26 only when the gate signal 25, supplied to the semiconductor device 26 by the gate drive circuit 20, is not higher than a prescribed voltage in a negative bias region and outputs a gate feedback signal 32 and prevents the gate signal from flowing into the gate drive circuit 20, when the gate signal is higher than the predetermined signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor power converter for supplying necessary electric power to a motor or another load.

[0002]

2. Description of the Related Art Conventionally, a system configuration as shown in FIG. 9 has been adopted as a typical semiconductor power converter driven by an AC motor as a load.

In FIG. 9, reference numeral 1 denotes a three-phase AC motor serving as a load. The three-phase AC motor 1 has a U-phase corresponding to each of the three phases.
It is driven by six circuits: the phase positive side circuit 2, the V phase positive side circuit 3, the W phase positive side circuit 4, the U phase negative side circuit 5, the V phase negative side circuit 6, and the W phase negative side circuit 7.

A gate control signal 9 is input from a controller 8 to the positive and negative circuits of each phase. The controller 8 performs control based on control signals such as an operation start signal and an abnormality detection signal, and outputs a gate control signal 9.

Each positive side circuit, as represented by the U-phase positive side circuit 2, controls a drive voltage by turning on and off a positive side semiconductor element 11 connected to a positive side main circuit potential 10, and similarly. Each negative circuit is connected to a negative main circuit potential 12 as represented by a U-phase negative circuit 5.
The drive voltage is controlled by turning on and off the switch 3, and necessary power conversion is performed by these switches.

The positive-side semiconductor element 11 is driven by a U-phase positive-side gate signal 16 output from a U-phase positive-side gate drive circuit 15 based on a U-phase positive-side gate control signal 14. 13 is driven by a U-phase negative gate signal 19 output from a U-phase negative gate drive circuit 18 based on a U-phase negative gate control signal 17.

Meanwhile, in the semiconductor power conversion device having such a configuration, as a method for verifying a gate signal supplied from a gate drive circuit to a semiconductor element, there is a method of detecting the gate signal and verifying whether the gate signal is normal. There are many methods, one of which is an indirect method in which a detector such as a CT is installed on a gate signal line and a detection circuit for a gate signal need not be installed directly. Is not often used because of its complexity.

On the other hand, there is a method of installing a detection circuit directly on a gate signal line and measuring the voltage level thereof. A conventional configuration example of this method will be described with reference to FIG.

[0009] As shown in FIG.
9 is provided with a gate control signal 2 from the controller 8 shown in FIG.
When 2 indicates ON, the gate positive bias potential 23 is output to the semiconductor element 26 as the gate signal 25 when the gate positive bias potential 23 is OFF.

In this case, the gate control signal 22 and the gate signal 25 are insulated by the photocoupler 21.

The gate signal 25 output from the gate drive circuit 20 is taken into a gate signal detector 29. The gate signal detection circuit 29 has a gate positive bias potential 2
3 and a negative bias potential 24 are divided by a positive-side voltage dividing resistor 27 and a negative-side voltage dividing resistor 28 connected in series, and the potential at the voltage dividing point is set as a detection level. The gate signal detection circuit 29 includes a level detector 30 that compares the potential of the gate signal 25 with the detection level. The level detector 30 is turned on when the potential of the gate signal 25 is higher than the detection level, and is turned off when the potential of the gate signal 25 is lower than the detection level. Is off and the gate feedback signal 32
Is output to a controller (not shown) via the photocoupler 31. In this case, an operational amplifier or the like is used as the level detector 30.

[0012]

As described above, the gate drive circuit 20 outputs the gate negative bias potential 24 as the gate signal 25 when the gate control signal 22 is off,
On the other hand, when it is on, the gate positive bias potential 32 is output. At this time, it is desirable that the level change speed of the gate signal 25 be fast after the gate control signal 22 is turned on or off. If the change speed is low, adverse effects such as an increase in loss of the semiconductor element 26 occur.

The fact that the semiconductor element 26 actually changes between the ON state and the OFF state is a region where the gate signal 25 is in the positive gate bias, and therefore the change speed is particularly required to be high in this region.

However, as in the conventional circuit, the level detector 3
When an operational amplifier is used for 0, since a detection current always flows from the gate signal 25 to the gate signal detector 29,
There is a problem that a part of the current for turning on and off the semiconductor element 26 is used for detection, and the change speed of the gate signal 25 is accordingly reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor power conversion device capable of detecting a gate signal without impairing the original gate characteristics.

[0016]

According to the present invention, in order to achieve the above object, a semiconductor power converter is constituted by the following means.

According to a first aspect of the present invention, a gate signal of a gate positive bias voltage is output when a gate control signal output from a controller is on, and a gate signal of a gate negative bias voltage is output when a gate control signal is off. And a gate drive circuit for driving the semiconductor device by outputting a signal to the semiconductor device, wherein the semiconductor device is provided only when a gate signal supplied from the gate drive circuit to the semiconductor device becomes equal to or lower than a predetermined voltage in a negative bias region. Is turned off, a gate feedback signal is output, and a gate negative bias detector for preventing the inflow of the gate signal when the gate signal is higher than the predetermined voltage is provided.

According to a second aspect of the present invention, in the semiconductor power conversion device according to the first aspect of the present invention, the gate feedback signal output from the gate negative bias detector and the gate control signal output from the controller are combined. A gate recording means for recording is provided.

According to a third aspect of the present invention, there is provided the semiconductor power conversion device according to the first aspect of the present invention, further comprising a gate negative bias detector corresponding to each drive circuit of the plurality of semiconductor elements, and Abnormal gate negative bias error before operation that takes in the gate feedback signal output from the negative bias detector and detects an abnormality in the circuit on condition that all or some gate signals are not negatively biased before operation. Detecting means is provided.

According to a fourth aspect of the present invention, in the semiconductor power conversion device according to the first aspect of the present invention, a gate feedback signal output from a gate negative bias detector is taken in, and a dead time required by a semiconductor element is obtained. When a signal is output without securing the time, a dead time abnormality detecting means for detecting the signal and outputting a dead time abnormality detection signal is provided.

According to a fifth aspect of the present invention, in the semiconductor power conversion device according to the first aspect of the present invention, a gate feedback signal output from a gate negative bias detector is fetched to minimize a required semiconductor element. A minimum on-pulse abnormality detecting means for outputting a minimum on-pulse abnormality signal when detecting that the on-pulse width is not secured is provided.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one circuit showing a first embodiment of a power semiconductor power converter according to the present invention.
The same parts as those in FIG. 10 are described with the same reference numerals.

As shown in FIG. 1, a photocoupler 21 is provided in the gate drive circuit 20, and a gate control signal 22 input from the controller 8 in FIG.
, The gate signal 25 is output to the semiconductor element 26 using the gate positive bias potential 23 as an ON signal and the gate negative bias potential 24 as an OFF signal.

Further, a gate negative bias detector 33 is provided in the gate drive circuit 20. The gate negative bias detector 33 includes a diode 35, a current limiting resistor 36, a zener diode 37, and a photocoupler 31 connected in series between a gate signal 25 line and an emitter potential 34 line of the semiconductor element 26. The gate signal 25 is clamped by the Zener diode 37, and the photocoupler 31 is driven by a potential difference from the emitter potential 34. Further, the diode 35 and the current limiting resistor 36 operate as an input protection for the gate negative bias detector 33 composed of them.

With this configuration, the Zener diode 37
The gate feedback signal 32 is turned on when a voltage lower than the detection potential of the negative bias region defined by the following is applied.

FIG. 2 is a time chart showing operation waveforms of the gate negative bias detector.

In FIG. 2, the potential of the gate signal 25 fluctuates between the gate negative bias potential 24 and the positive bias potential 23 as shown in FIG.

At this time, since the switching of the diode 35 and the like occurs near the detection potential 38 defined by the Zener diode 37, the waveform of the gate signal 25 is slightly delayed. However, since the semiconductor element actually operates in a region where the potential is higher than the emitter potential 34, the semiconductor element 26
Has little effect on the switching characteristics.

Therefore, the gate negative bias detector 33 according to the present invention has an effect on the switching characteristics of the semiconductor element 26.
Has almost no effect.

The gate characteristic of the semiconductor element 26 requires that the gate signal rise time tr and the gate signal fall time tf in FIG. 2 be steep, so that this circuit detects the gate feedback signal 32. Above, the adverse effect on the original gate characteristics can be reduced.

As described above, according to the first embodiment, the gate feedback signal can be detected without impairing the original characteristics of the gate signal in the positive bias region.

FIG. 3 is a block diagram showing a second embodiment of the semiconductor power converter according to the present invention.

In the second embodiment, each phase circuit having the same configuration as that of FIG. 1, that is, a U-phase positive side circuit 41, a V-phase positive side circuit 42, W
Phase positive side circuit 43, U phase negative side circuit 44, V phase negative side circuit 4
5. The gate signal recorder 47 records each gate control signal input to the W-phase negative circuit 46 and each gate feedback signal output from each phase circuit.

Therefore, according to the second embodiment,
The gate feedback signal and the gate control signal detected by using the negative bias area are recorded in the gate signal recorder 47, and the data is verified afterward to determine whether the failure is caused by an abnormal gate signal. Can be determined.

FIG. 4 is a block diagram showing a main part of a third embodiment of the semiconductor power converter according to the present invention.

In the third embodiment, when all the gates are turned off before the operation, the gate feedback signal 32 output from the gate negative bias detector 33 of each phase circuit shown in FIG. It is input to a bias abnormality detector 51 to verify whether or not all the gates are normally shown.
Is output. In this case, each gate feedback signal 32 is input to the NAND circuit 52, and if any one of the gate feedback signals 32 indicates that it is not off, a gate negative bias abnormality detection signal 53 before operation is output.

In the semiconductor power converter having such a configuration, all the gate signals 25 are turned off before the operation. Therefore, when the circuit is normal, the levels of all the gate signals 25 should be the gate negative bias potential 24. In any other state, the failure of the circuit is estimated. If the operation is started in this state, not only can the device not operate normally, but also the damage may be spread to circuits other than the faulty circuit.

Therefore, before the operation, the gate feedback signal 3
2 to the pre-operation gate negative bias abnormality detector 51,
If all gate feedback signals 32 indicate gate-off in the NAND circuit 52, it is determined to be normal. If at least one gate feedback signal is not gate-off, the pre-operation gate negative bias abnormality detection signal 53 is output and operation is not started. Apply an interlock like this.

As described above, according to the third embodiment, in the state before the operation, the soundness of all the gate signals off is determined by using the gate feedback signal using the negative bias region, so that the normal negative It is possible to verify whether a bias level is applied.

FIG. 5 is a block diagram showing a main part of a fourth embodiment of the semiconductor power converter according to the present invention.

In the fourth embodiment, the positive gate feedback signal 32a output from the positive gate negative bias detector 33a and the negative gate of the negative gate negative bias detector 33b of each phase circuit shown in FIG. The feedback signal 32b is input to the dead time abnormality detector 61, and the positive side gate feedback signal 32a and the negative side gate feedback signal 32b are mutually monitored. An abnormality detection signal 62 is output.

The dead time abnormality detector 61 includes a positive one-shot circuit 63 for detecting a dead time abnormality to which the positive gate feedback signal 32a is input, and a negative gate feedback signal 3
The output of the negative one-shot circuit 64 for dead time abnormality detection and the positive one-shot circuit 63 for dead time abnormality detection to which 2b is input are applied to one input terminal, and the negative gate feedback signal 32b is applied to the other inhibit terminal. The first inhibit circuit 65, the output of the dead time abnormality detecting negative one-shot circuit 65 is applied to one input terminal, and the positive gate feedback signal 32a is applied to the other inhibit terminal. It comprises an OR circuit 67 for transmitting the logical sum of the outputs of the first inhibit circuit 65 and the second inhibit circuit 66 as a dead time abnormality detection signal 62.

By the way, while the positive gate signal 25a and the negative gate signal 25b are turned on and off alternately, there is a dead time in which both are turned off. If this time is not ensured, the device may fail. However, the semiconductor power converter having the above-described configuration can detect the abnormality.

That is, in FIG. 5, a positive gate signal 25a and a negative gate signal 25b are detected by a positive gate negative bias detector 32a and a negative gate negative bias detector 33b, and a positive gate feedback signal is detected. 32a and a negative gate feedback signal 32b.

The positive-side one-shot circuit 63 for detecting a dead time abnormality and the negative-side one-shot circuit 64 for detecting a dead time abnormality detect the rise thereof and output an ON signal for a certain period of time. 65,
When the conditions of the logic circuits of the second inhibit circuit 66 and the OR circuit 67 are satisfied, the dead time abnormality detection signal 62
Is output.

FIG. 6 is a time chart showing operation waveforms of the dead time abnormality detector.

Accordingly, as can be seen from this time chart, the positive one-shot circuit 63 for detecting a dead time abnormality is provided.
One-shot circuit 64 for detecting dead time abnormality
When a signal is output without securing a required dead time defined by the following, it can be detected.

Further, by latching this abnormality detection signal, it is possible to maintain information on a failure.

As described above, according to the fourth embodiment, by using the gate feedback signal using the negative bias region for the logic signal for turning on and off the gate, it is determined whether the dead time is normally secured. Can be detected.

FIG. 7 is a block diagram showing a main part of a fifth embodiment of the semiconductor power converter according to the present invention.

In the fifth embodiment, the gate feedback signal 32 output from the gate negative bias detector 33 in response to the input of the gate signal 25 is changed to the minimum on-pulse width abnormality detector 7.
1, the minimum on-pulse abnormality detection signal 72 when the necessary minimum on-pulse of the gate feedback signal 32 is not ensured.
Is output.

The minimum on-pulse width abnormality detector 71 is
A one-shot circuit 72 for detecting a minimum on-pulse width abnormality, which detects a fall of the gate feedback signal 32 and outputs an on-signal for a predetermined time; an output of the one-shot circuit 72 for detecting a minimum on-pulse width abnormality; And an AND circuit 74 that outputs a minimum on-pulse width abnormality detection signal 73 when the condition is satisfied.

When the semiconductor element 26 is used in a semiconductor power conversion device, there is a minimum value for the on-pulse width during firing. On the other hand, if the ignition or extinction is performed, the device may fail. However, if the semiconductor power converter having the above configuration is used,
The abnormality can be detected.

That is, in FIG. 7, the gate signal 25 is detected by the gate negative bias detector 33 of each phase, and the gate feedback signal 32 is supplied to the minimum ON pulse width abnormality detector 71.
The minimum ON pulse width abnormality detector 71 detects the fall of the gate feedback signal by a minimum ON pulse width abnormality detection one-shot circuit 73, outputs an ON signal for a certain period of time, and an AND circuit 74 outputs a minimum ON pulse width abnormality detection one shot. The logical product of the output of the shot circuit 73 and the gate feedback signal 32 is output as the minimum on-pulse width abnormality detection signal 72.

FIG. 8 is a time chart showing operation waveforms of the minimum on-pulse width abnormality detector.

As can be seen from this time chart, if a signal is output without securing the required minimum on-pulse width specified by the minimum on-pulse width abnormality detecting one-shot circuit 73, the signal is detected. be able to.

Further, by latching the abnormality detection signal, it is possible to maintain information on the failure.

As described above, according to the fifth embodiment, by using the gate feedback signal using the negative bias region for the logic signal for turning on and off the gate, whether the minimum on-pulse width is normally ensured. Can be detected.

[0060]

As described above, according to the present invention, by detecting a gate feedback signal using a negative bias region, the gate feedback signal can be obtained without impairing the original characteristics of the gate signal in the positive bias region. A semiconductor power converter that can be detected can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor power conversion device according to the present invention.

FIG. 2 is a time chart showing operation waveforms of a gate negative bias detector in the embodiment.

FIG. 3 is a block diagram showing a second embodiment of the semiconductor power conversion device according to the present invention.

FIG. 4 is a block diagram showing a main part of a semiconductor power conversion device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a main part of a fourth embodiment of the semiconductor power conversion device according to the present invention.

FIG. 6 is a time chart showing operation waveforms of the dead time abnormality detector in the embodiment.

FIG. 7 is a block diagram showing a main part of a semiconductor power conversion device according to a fifth embodiment of the present invention.

FIG. 8 is a time chart showing operation waveforms of the minimum on-pulse width abnormality detector in the embodiment.

FIG. 9 is an overall configuration diagram of a system including a semiconductor power conversion device and peripheral devices.

FIG. 10 is a block diagram showing a gate signal detector provided corresponding to each phase circuit of the conventional power converter.

[Explanation of symbols]

 20 gate drive circuit 21, 31 photocoupler 22 gate control signal 23 gate positive bias potential 24 gate negative bias potential 25 gate signal 25a positive gate signal 25b negative side Gate signal 26 Semiconductor device 32 Gate feedback signal 32a Positive gate feedback signal 32b Negative gate feedback signal 33 Gate negative bias detector 33a Positive gate negative bias detector 33b Negative gate negative bias detector 34 Emitter potential 35 Diode 36 Current limiting resistor 37 Zener diode 38 Detection potential 41, 42, 43 U-phase, V-phase, W-phase positive side circuit 44, 45, 46: U-phase, V-phase, W-phase negative side circuit 47: Gate signal recorder 51: Gate negative bias abnormality detector before operation 52: Na Circuit 53: Gate negative bias abnormality detection signal before operation 61: Dead time abnormality detector 62: Dead time abnormality detection signal 63: Positive one-shot circuit for dead time abnormality detection 64: Dead time abnormality detection Negative one-shot circuit 65, 66 Inhibit circuit 67 OR circuit 71 Minimum on-pulse width abnormality detector 72 One-shot circuit for minimum on-pulse width abnormality detection 73 Minimum abnormality on-pulse width detection signal 74 AND circuit

Claims (5)

[Claims] When a gate control signal output from a controller is on, a gate signal of a gate positive bias voltage is output;
In a semiconductor power conversion device including a gate drive circuit that outputs a gate signal of a gate negative bias voltage when a gate control signal is off and drives a semiconductor element, the gate signal supplied from the gate drive circuit to the semiconductor element is negative. A gate negative bias that detects that the semiconductor element is turned off and outputs a gate feedback signal only when the voltage falls below a predetermined voltage in the bias region, and blocks the inflow of the gate signal when the gate signal is higher than the predetermined voltage. A semiconductor power conversion device comprising a detector. 2. The semiconductor power converter according to claim 1, further comprising a gate recording means for recording a gate feedback signal output from the gate negative bias detector and a gate control signal output from the controller. Characteristic semiconductor power converter. 3. The semiconductor power conversion device according to claim 1, further comprising: a gate negative bias detector corresponding to each drive circuit of the plurality of semiconductor elements; and a gate feedback output from the gate negative bias detector. Capture the signal,
A semiconductor power conversion device comprising a pre-operation gate negative bias abnormality detecting means for detecting a circuit abnormality on condition that all or some of the gate signals are not negatively biased before operation. 4. The semiconductor power conversion device according to claim 1, wherein the gate feedback signal output from the gate negative bias detector is taken in, and the signal is output without securing the dead time required by the semiconductor element. A semiconductor power conversion device provided with dead time abnormality detection means for detecting the signal and outputting a dead time abnormality detection signal. 5. The semiconductor power conversion device according to claim 1, wherein a gate feedback signal output from the gate negative bias detector is taken in to detect that the minimum on-pulse width required by the semiconductor element is not secured. Then, a semiconductor power conversion device is provided with a minimum on-pulse abnormality detecting means for outputting a minimum on-pulse abnormality signal.