JP2001238364A - Secondary cell charger controlling semiconductor device and secondary cell charger using device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a secondary cell charging control a semiconductor device of low cost with safety, without the need for an expensive element, such as a microcomputer or the like, and a secondary cell charger. SOLUTION: The secondary cell charging control semiconductor device 1 comprises a charger 5, a diode 2 for blocking reverse current from a secondary cell to the power source VDD or the charger 5, a PNP bipolar transistor 3 for controlling the charging current from the charger 5, and a capacitor 4 for stabilizing the VDD. Due to this constitution, a cell CELL1 and a cell CELL2 are charged. The device 1 comprises a reference voltage source, a constant current circuit, a low-voltage detector for detecting a low voltage of the cell, an overvoltage detector for detecting overvoltage of the cell, a delay circuit for setting a delay time when overvoltaging is detected and when reset, and an oscillator for pulse charging up to a low-voltage recovery.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a secondary battery charger controlling semiconductor device and a secondary battery charger for charging secondary batteries for various electronic devices such as portable devices, and more particularly to a secondary battery charger. In addition, the present invention relates to an inexpensive semiconductor device for controlling a secondary battery charger and a secondary battery charger which can protect a primary or secondary battery against overcharge and have high safety.

[0002]

2. Description of the Related Art In recent years, portable electronic devices have become widespread. In such portable electronic devices, Ni-Cd or Ni-MH (Metal Hydrid) is used as a power source.
e) Rechargeable secondary batteries (batteries) are used. As a charger for charging such a secondary battery,
For example, JP-A-6-165402 and JP-A-9-2
No. 15223, Japanese Patent Application Laid-Open No. 10-14125 and the like.

Japanese Patent Application Laid-Open No. 6-165402 discloses a configuration in which a small trickle charge current and a large quick charge current are switched and supplied when charging a fast-chargeable secondary battery. The present invention prevents the life of the secondary battery from being shortened, and allows a large surge current to flow when a dendritic short circuit occurs in the battery to restore the battery to normal.

Japanese Patent Application Laid-Open No. 9-215223 discloses a device in which a switching element is provided between a power supply unit and a secondary battery, and a microcomputer uses a terminal voltage detected when the switching element is turned on / off. Thus, the charging control is performed. Further, JP-A-10-141
No. 25 discloses a battery voltage and a battery temperature, and calculates a rapid charging current value and an optimum charging time based on the detected battery voltage and battery temperature.

[0005]

As described above, for example, if the charging of the Ni-Cd and Ni-MH chargers is controlled using a microcomputer, if the primary battery is not suitable for charging an alkaline battery or the like. Even if the battery is charged, the battery and the charger can be protected from liquid leakage and explosion caused by overvoltage of the primary battery, but the problem is that the charger becomes expensive when a microcomputer is incorporated. is there. Also,
When an inexpensive charger that does not incorporate a microcomputer is used, the above-described control cannot be performed, and there is a problem that dangers such as liquid leakage and explosion cannot be avoided.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an inexpensive and safe semiconductor device for controlling a secondary battery charger and a secondary battery charger which eliminates the above problems and does not require expensive elements such as a microcomputer. To provide.

More specifically, the inventions of claims 1 to 5 are inventions of a semiconductor device for controlling a secondary battery charger, and in particular, the invention of claim 1 is that the primary or secondary battery has an overvoltage. , And controlling the charging based on the result. The invention according to claims 1 and 2 aims at proposing a method of charging by a pulse, and the invention according to claims 3 and 4 The invention aims at proposing a valid pulse duty range in that case, and the invention according to claim 5 also aims at proposing a valid pulse frequency in that case.

The invention according to claims 6 and 7 is an invention for a secondary battery charger. In particular, the invention according to claim 6 is
The present invention proposes a configuration including the semiconductor device for controlling a secondary battery charger according to any one of claims 1 to 5, and an invention according to claim 7 proposes a configuration that embodies the whole. It is intended to be.

[0009]

In order to achieve the above objects, the invention of a semiconductor device for controlling a secondary battery charger according to claim 1 of the present application detects overvoltage of one or more primary or secondary batteries. Overvoltage detection means, delay means for delaying the output of the overvoltage detection means, and control signal output means for outputting a signal for controlling on / off of the charging path of the primary or secondary battery based on the output of the delay means. In addition, the battery is charged by pulse charging up to a predetermined voltage.

Further, the invention of a semiconductor device for controlling a secondary battery charger according to claim 2 is further characterized in that the battery is charged by pulse charging up to a predetermined voltage (low voltage recovery voltage), and then fully charged. And

According to a third aspect of the present invention, there is provided a semiconductor device for controlling a secondary battery charger.
The invention of the semiconductor device for controlling a secondary battery charger according to claim 4, wherein the heat generation amount is set so as not to destroy the control transistor serving as a charging path, in particular, the duty of the pulse is set to 10% to 20%. It is characterized by doing.

According to a fifth aspect of the present invention, the frequency of the pulse is set to 10 kHz.
It is characterized in that the frequency is set to z to 100 kHz.

[0013] The secondary battery charger according to claim 6 is characterized in that:
A secondary battery charger control semiconductor device according to any one of claims 1 to 5 is provided, and the secondary battery charger according to claim 7 embodies the entire configuration thereof. And a control transistor for controlling ON / OFF of a charging path, comprising: a diode for preventing current backflow; a voltage stabilizing capacitor; and a control transistor for controlling on / off of a charging path, for controlling a secondary battery charger according to any one of claims 1 to 5. The semiconductor device is characterized in that on / off of the control transistor is controlled by an output of the control signal output means.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a secondary battery charger control semiconductor device of a secondary battery (Ni—Cd, Ni—MH, etc.) dedicated charger according to the present invention.

In FIG. 1, reference numeral 1 denotes a semiconductor device for controlling a secondary battery charger according to the present invention (detailed in FIG. 2), 5 denotes a charger,
Reference numeral 2 denotes a diode for preventing current backflow from the secondary battery to the power supply VDD or the charger 5, 3 denotes a PNP bipolar transistor for controlling a charging current from the charger 5, 4 denotes a capacitance for stabilizing VDD, a cell CELL1, and a cell. CELL2 is a primary or secondary battery.

The semiconductor device 1 for controlling a secondary battery charger has a V
DD terminal, GND terminal, OUT terminal, SENS1 terminal,
It has five SENS2 terminals, the OUT terminal is connected to the base of the PNP bipolar transistor 3 via a resistor, and the SENS1 terminal is connected to the positive electrode side of the cell CELL1 via a resistor R1 for preventing electrostatic breakdown. The SENS2 terminal is connected to a connection point between the cell CELL1 and the cell CELL2 via a resistor R2 for preventing leakage current in a semiconductor substrate constituting the semiconductor device for controlling a secondary battery charger, and the GND terminal is charged. The VDD terminal is connected to the negative side of the charger, and the VDD terminal is connected to the positive side of the charger.

FIG. 2 is a block diagram of a semiconductor device 1 for controlling a secondary battery charger according to the present invention. The semiconductor device 1 for controlling a secondary battery charger includes a reference voltage source, a constant current circuit, a cell C
A low voltage detection circuit VD2 for detecting a low voltage of the cell ELL1, and a low voltage detection circuit VD for detecting a low voltage of the cell CELL2
4. An overvoltage detection circuit VD1 for detecting an overvoltage of the cell CELL1, an overvoltage detection circuit VD3 for detecting an overvoltage of the cell CELL2, and a delay circuit Delay for setting a delay time at the time of overvoltage detection and at the time of recovery by the outputs of the overvoltage detection circuits VD1 and VD3. , Low voltage detection circuits VD2 and VD
Oscillator OSC (frequency 10 KHz, On-Duty 1) for pulse charging to the low voltage return voltage by the output of
0%). OUT terminal is CMO
S output.

FIG. 3 is a diagram showing a specific configuration example of the delay circuit Deley. As shown in the figure, the CMOS inverter has a configuration in which CMOS inverters are connected in cascade, and a constant current source 10 (current I1) and a constant current source 20
(Current I2) are connected in series, and a capacitor C is connected to the subsequent stage of the first stage CMOS inverter.

FIG. 4 is a time chart for explaining the operation of the secondary battery charger controlling semiconductor device of FIG.
FIG. 2 shows the voltage of the cell CELL1 in FIG.
ELL2, the input signals a and b of the delay circuit Deley, the output signal e, the input signals c and d of the oscillator OSC,
A time chart of the output signal f and the OUT signal to the OUT terminal is shown. Here, the oscillation pulse of the oscillator OSC has a frequency of 10 KHz and On-Duty of 10%.

Hereinafter, the state of each section of FIG. 4 will be sequentially described. (1) In the AB section, pulse charging is performed from a cell voltage of zero to a low voltage return voltage (Vrel3, Vrel4).
Pulse charging continues as long as neither cell exceeds the low voltage release voltage. The reason for the pulse charging is that if the battery is fully charged near a low voltage, the package generates a large amount of heat, and the package may be melted or burned by the heat.

(2) In the BC section, the PNP bipolar transistor 3 is charged to the overvoltage detection voltages (Vdet1, Vdet2) of each cell when the PNP bipolar transistor 3 is fully on (base potential = GND) (On-Duty 100%). If either one detects the overvoltage early, the delay circuit Del
ey works. The reason for providing the delay circuit Delay is 2
The first reason is that the noise is applied to the substrate VDD before the detection, so that the cell potential is also detected with the noise. The second reason is that immediately after detection, PN
This is because, when the P bipolar transistor 3 is turned off, the cell potential rapidly changes and returns.

(3) The section CD is an overvoltage detection delay time. This delay is made by the circuit of FIG.
The overvoltage detection delay time tVdet is defined by the following equation. tVdet = internal capacitance C × (VDD−Vth of PchMOS transistor 30) / constant current I1

That is, the overvoltage detection delay time is the time from when the internal capacitance C is charged through the constant current source 10 (constant current I1) to when the PchMOS transistor 30 falls below the conduction threshold and turns off.

(4) In the section D-E, the PNP bipolar transistor 3 is turned off (base potential = VDD). Each cell voltage is directly overvoltage recovery voltage (Vrel1, Vr
el2). The recovery delay circuit does not work unless the voltage reaches the overvoltage recovery voltage. The reason why the return delay is necessary is that, similarly to the detection delay described above, the noise is applied to the substrate VDD before the return, and thus the cell potential also returns due to the noise.

(5) The section EF is an overvoltage recovery delay time. This delay is made by the delay circuit shown in FIG. The overvoltage recovery delay time tVrel is defined by the following equation. tVrel = internal capacitance C × (VDD−Vth of NchMOS transistor 40) / constant current I2

That is, the overvoltage recovery delay time is the time from when the electric charge accumulated in the internal capacitance C is discharged through the constant current source 20 (constant current I2) until the NchMOS transistor 40 falls below the conduction threshold and turns off. is there.

(6) In the GH section, one of the cell voltages (in this case, Cell1) is equal to or lower than the low voltage recovery voltage, so that pulse charging is performed until the other cell voltage (in this case, Cell2) reaches the overvoltage detection voltage.

(7) In the HI section, the CD shown above is used.
Same as the section. (8) The IJ section is the same as the DE section described above. (9) The JK section is the same as the EF section described above. (10) In the section KL, the voltage of the cell CELL2 is equal to or higher than the low voltage reset voltage, but the voltage of the other cell Cell1 has not yet reached the low voltage reset voltage, so pulse charging is performed.

(11) The LM section is the B-M
This is the same as section C. (12) The MN section is the same as the CD section described above. (13) The NO section is the same as the DE section described above. (14) The OP section is the same as the EF section described above.

The OUT signal generated as described above is output from the OUT terminal and applied to the base of the PNP bipolar transistor 3 via a resistor. This gives P
The on / off of the NP bipolar transistor 3 is controlled, and the charging of the secondary battery can be realized with a safe and inexpensive configuration without overcharging.

Using the circuit configuration of FIG. 5, the heat generated by the PNP bipolar transistor is reduced by a base resistance of 300Ω and a PG
(Pulse generator) frequency 10 KHz, charging current 50
0 mA, 750 mA, 1 A, 10% On-Duty,
The experiment was performed by changing to 20% and 30%.

FIG. 6 shows the results of the above experiment.
FIG. 12A shows the experimental result when On-Duty is set to 10%, FIG. 10B shows the experimental result when On-Duty is set to 20%, and FIG. -The experiment result at the time of setting Duty to 30% is shown. Note that, in FIG. 3C, when the current was 1 A, the temperature of the PNP bipolar transistor 3 became 100 ° C. or more and the PNP bipolar transistor 3 was burned.

In order to prevent the PNP bipolar transistor 3 from burning, it is necessary to reduce the heat generation to 100 ° C. or less. For this purpose, as a result of the above experiment, it has been found that the on-duty of such a pulse that can withstand a charging current of 1 A takes an appropriate value of about 10% to 20%.

The circuit configuration of the above embodiment is merely an example, and another configuration may be employed as long as it has a similar function. For example, the PNP bipolar transistor may be changed to another switch-controllable element.

In the above embodiment, two cells are charged as an example, and two overvoltage detection circuits (overvoltage detection circuits VD1 and VD3) and two low voltage detection circuits (low voltage detection circuits). Circuit VD2, low voltage detection circuit V
D4) is shown, but when one cell is charged, it goes without saying that only one overvoltage detection circuit and one low voltage detection circuit are required as shown in FIG.

[0036]

According to the present invention, the following effects can be obtained. (A) According to the first to seventh aspects of the present invention, the overvoltage is detected and the on / off of the charging path is controlled based on the detection result. Even when the battery is charged, the battery and the charger can be protected from battery leakage due to overvoltage and explosion.

(B) According to the first to fifth aspects of the present invention, since the charging method using a pulse is adopted, damage to the package and the charger due to heat generation of the package can be prevented.

(C) Further, according to the first to seventh aspects of the present invention, since an expensive element such as a microcomputer is not used, an inexpensive secondary battery charger can be realized.

[Brief description of the drawings]

FIG. 1 shows a secondary battery (Ni—Cd, Ni—M) according to the present invention.
H) is a block diagram of a semiconductor device for controlling a secondary battery charger of a dedicated charger.

FIG. 2 is a block diagram of a secondary battery charger controlling semiconductor device 1 according to the present invention.

FIG. 3 is a diagram illustrating a specific configuration example of a delay circuit Deley.

FIG. 4 is a time chart for explaining an operation of the semiconductor device for controlling a secondary battery charger shown in FIG. 2;

FIG. 5 shows that the heat generation of the PNP bipolar transistor is controlled by a base resistance of 300Ω and a PG (pulse generator) frequency of 10K.
Hz, charging current 500 mA, 750 mA, 1 A, On
FIG. 11 is a diagram for explaining a circuit configuration of an experiment performed by changing −Duty to 10%, 20%, and 30%.

FIG. 6 is a diagram showing the results of an experiment performed with the circuit configuration of FIG. 5;

FIG. 7 is a diagram showing a configuration example of a secondary battery charger control semiconductor device having one overvoltage detection circuit and one low voltage detection circuit.

[Explanation of symbols]

 1: semiconductor device for controlling a secondary battery charger, 2: diode, 3: PNP bipolar transistor, 4: capacitance, 5: charger, 10, 20: constant current source, 30: PchMOS transistor, 40: NchMOS transistor.

Claims (7)

[Claims] 1. An overvoltage detecting means for detecting an overvoltage of one or more primary or secondary batteries, a delay means for delaying an output of the overvoltage detecting means, and a detecting means for detecting an overvoltage of the primary or secondary battery based on an output of the delay means. Control signal output means for outputting a signal for controlling ON / OFF of a charging path, wherein the charging signal is controlled by the control signal output means and charged to a predetermined voltage by pulse charging. A semiconductor device for controlling a charger. 2. The semiconductor device for controlling a secondary battery charger according to claim 1, wherein the battery is charged to a predetermined voltage (low-voltage recovery voltage) by pulse charging, and then fully charged. 3. The semiconductor device for controlling a secondary battery charger according to claim 1, wherein a duty of the pulse is set so as to be a heat generation amount that does not destroy a control transistor serving as a charging path. . 4. The pulse duty is 10% to 2%.
4. The semiconductor device for controlling a secondary battery charger according to claim 3, wherein the value is set to 0%. 5. The frequency of the pulse is set to 10 kHz to 10 kHz.
The semiconductor device for controlling a secondary battery charger according to any one of claims 1 to 4, wherein the frequency is set to 0 kHz. 6. A secondary battery charger comprising the semiconductor device for controlling a secondary battery charger according to any one of claims 1 to 5. 7. The secondary battery charger according to claim 1, further comprising a current backflow prevention diode, a voltage stabilizing capacitor, and a control transistor for controlling on / off of a charging path. A secondary battery charger characterized in that on / off of the control transistor is controlled by an output of the control signal output means in the control semiconductor device.