JP2001237660A - Equalizer controller and communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve convenience by easily performing equalizer setting in audio equipment of an audio system connected with an IEEE1394 bus. SOLUTION: A parametric equalizer function is applied to amplifier equipment STR. Then, a personal computer can control a parametric equalizer by transmitting/receiving a CURRENT EQ control command. Concerning equalizer setting on the personal computer, by adopting a GUI, a frequency and a gain corresponding to the setting point of equalizer characteristics can be simultaneously set by drag and drop operations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device capable of communicating with another device having a parametric equalizer function via a data bus in a predetermined communication format, and controlling the setting of the parametric equalizer of the other device. An equalizer control device that can perform
The present invention also relates to a communication system constituted by connecting the equalizer control device and another device having a parametric equalizer function via a data bus.

[0002]

2. Description of the Related Art For example, among audio equipment users, an AV system is mainly provided with an amplifier (Electronic and Visual) equipment for recording or reproducing various audio sources in addition to an amplifier equipment. I have. Then, each amplifier and A constituting such an AV system
Some V devices have an equalizer for adjusting the sound quality of output sound.

[0003] As such an equalizer, a device employing a graphic equalizer is known.
In the graphic equalizer, a band is set in advance in a divided manner, and a user can adjust a gain for each of the divided bands. Graphic equalizer
It is widely used because it is possible to visually grasp the frequency band.

[0004]

However, since the band of the graphic equalizer is divided and set in advance, the gain of each divided band must be set one by one in order to obtain the frequency characteristic desired by the user. In a sense, the operation is cumbersome. Further, such a graphic equalizer includes, for example, a plurality of operators for setting a gain by being divided for each band with respect to the device main body, or a bar indicating a gain for each band simulating a graphic equalizer. Must be displayed, and a large area must be occupied as an operation panel or a display unit. In recent years, downsizing of devices has been required, which is disadvantageous in this respect. In order to compensate for this, for example, it is necessary to adopt an operation mode in which equalizer settings are called by menu settings and settings are made by numerical values and the like.

[0005]

Therefore, the present invention is configured as follows in consideration of the above-mentioned problems. First, as an equalizer control device, a communication unit capable of communicating with an external device via a data bus in a predetermined communication format, an operation unit, and a parametric equalizer based on an operation performed on the operation unit. Parameter setting means capable of variably setting a predetermined parameter, and by executing communication with the external device having a parametric equalizer by the communication means, the parameter set by the parameter setting means is changed by the external device. And control means for executing control so as to be set for the parametric equalizer.

The communication system is configured as follows. In other words, the communication system includes at least a first device and a second device communicably connected to the first device via a data bus having a predetermined communication format and capable of performing a required operation. Shall be provided. The second device includes an operation unit, a parameter setting unit that can variably set a predetermined parameter of the parametric equalizer based on an operation performed on the operation unit, and the parameter setting unit. And transmission control means for transmitting and outputting the parameter information set by the communication device to the first device by the communication means. Further, the first device includes a parametric equalizer for performing an equalizing process on the audio information, and a control unit for performing a change setting of the parameter in the parametric equalizer based on the received and acquired parameter information. I decided that.

According to the above configuration, by connecting the equalizer control device to the external device via the data bus, the equalizer setting of the external device can be controlled by the equalizer control device. That is, the setting of the equalizer can be performed not by the operation on the external device main body but by the operation on the equalizer control device, which is assumed to be specially configured for the equalizer control. In addition, as the equalizer, a parametric equalizer is used.Since the parametric equalizer is based on an operation of determining a certain frequency as a set point and adjusting the gain of the frequency, the parametric equalizer is used as an operation for the setting. Can be made simpler than, for example, a graphic equalizer.

[0008]

Embodiments of the present invention will be described below. The following description will be made in the following order. 1. AV system 1-1. Overall configuration 1-2. STR (front panel) 1-3. STR (internal) 1-4. 1. Personal computer (internal) Data communication according to the present embodiment by IEEE1394 2-1. Overview 2-2. Stack model 2-3. Signal transmission form 2-4. Bus connection between devices 2-5. Packet 2-6. Transaction rules 2-7. Addressing 2-8. CIP (Common Isochronos Packet) 2-9. Connection management 2-10. Commands and responses in FCP 2-11. AV / C command packet 2-12. Plug 2-13. 3. Asynchronous Connection transmission procedure Equalizer control function 4-1. Equalizer setting operation 4-2. CURRENT EQ command 4-3. Processing operation

1. AV system 1-1. 1. Overall Configuration FIG. 1 shows a configuration example of an electronic device system according to an embodiment of the present invention. The electronic device system according to the present embodiment is constructed by connecting a plurality of AV devices and the like via an IEEE1394 interface data bus so as to be able to communicate with each other.

In FIG. 1, STR (Stereo Tuner Receiver) 60 and S
TR compatible CD machine 30 and personal computer 11
3 is shown.

The STR 60 functions as the center of the AV system shown in FIG. 1, and mainly has a tuner function, an external source input selection function, and an amplifier function.
For example, as shown in the figure, left and right channel speakers SP (L) (R) corresponding to stereo sound can be connected. Although the detailed configuration will be described later, ST
In R60, the broadcast signal received by the internal tuner section
Analog audio signal input and IEEE 139
A plurality of audio sources input from the outside via the four buses 116 are selected, and finally, the selected audio sources can be output as sounds from the speakers SP (L) (R).

FIG. 1 also shows a remote controller RM for operating the STR 60. The STR 60 receives an operation command signal transmitted in response to an operation performed on the remote controller RM, and performs a required operation according to the content of the operation command signal. Note that, although only the remote controller RM corresponding to the STR 60 is shown in this figure, in practice, other devices may be operated by the remote controller.

The STR-compatible CD machine 30 is shown here as a model capable of realizing various convenient system functions by being connected together with the STR 60. The STR-compatible CD machine 30 is, for example, an STR60
And the same manufacturer.

The STR-compatible CD unit 30 is a CD (Compact D)
isc) has a function as a player, and the loaded C
Playback for D is performed. Then, audio data obtained by reproducing from the CD is transferred to the IEEE 1394 bus 11.
6 can be transmitted and output.

Typical system operations obtained by the STR 60 and the STR-compatible CD machine 30 include the following. For example, if audio data of a CD being reproduced by the STR-compatible CD machine 30 is transmitted to the STR 60, the STR 60 uses the audio data of the CD as monitor sound and outputs the speaker SP (L) (R).
Can be output. Also, STR60
It is possible to provide various system component-like functions, such as power on / off interlocking with the STR-compatible CD machine 30.

Although not shown here, for example, each of the AV devices shown in FIG. 1 is provided with a power outlet for inputting power from a commercial AC power supply. Alternatively, if the battery can be driven, the battery can be stored. That is, each device can independently obtain power. As the STR-compatible device, for example, STR
Other examples, such as a compatible MD recorder / player, are shown here, but only the STR compatible CD machine 30 is shown.

1-2. STR (Front Panel) Next, a front panel part of the STR 60, which is a main component in configuring the system shown in FIG. 1, will be described.

FIG. 2 shows a front panel of the STR 60 main body. A power key 120 is provided on the lower left side of the front panel. By operating the power key 120, the power of the STR 60 is switched on / off. Note that the power-off state here refers to a so-called standby state in which the standby power supply is operating, and is different from, for example, a state in which supply of commercial AC power (or battery) is cut off. In this regard, the STR-compatible CD machine 30 described below will be described.
And the STR-compatible MD machine 1. Also,
Although detailed description is omitted here, the STR 60 also has a sleep mode for setting a sleep state, so that power saving is considered.

On the left side of the power key 120, a headphone jack 27j is provided.

A display section 75 is disposed substantially at the center of the front panel. The display unit 75 in this case is an FL tube display unit 75A for mainly displaying characters.
Is provided, and here, display for 14 characters per line is performed. A segment display section 75B is provided around the area, and predetermined contents (not shown) are displayed by the segments.

The display key 1 is located on the left side of the display section 75.
27, and a dimmer key 128 is on the left.
Is provided. The display key 127 is basically used to change the display content on the display unit 75. The dimmer key 128 is for adjusting the luminance of the decorative LED actually provided on the display unit 75 and the front panel.

A jog dial 125 is provided on the right side of the FL tube display section 75A, and a band key 121 is provided above the jog dial 125.
A tuner mode key 122, a jog selection key 123, and an enter key 124 are shown. The band key 121 and the tuner mode key 122 are keys related to the tuner function of the STR 60, and are used when switching between the reception band and the tuner mode, respectively. The jog selection key 123 is a key for selecting a menu, and the enter key 124 is used for performing a determination operation. The jog dial 125 is used together with the above keys under a predetermined operation procedure, so that the user can perform various actual operations.

As an example, every time the jog selection key 123 is pressed once, the display content of the FL tube display section 75A changes in a toggle manner as follows: FUNCTION → SOUND → SETUP. Then, for example, when the jog dial 125 is rotated in a state where FUNCTION is displayed on the FL tube display section 75A, the selection of the source to be input by the STR 60 and output as the monitor sound can be changed. At this time, the name of the input source currently selected according to the rotation operation of the jog dial 125 is displayed on the FL tube display section 75A. Depending on this operation, for example, tuner audio, analog input, and IEEE
Sources (devices) input via the E1394 bus can be sequentially selected in a predetermined order. For example, a band key 121, a tuner mode key 122, a jog selection key 123, an enter key 124
Such a key is provided with an LED for decoration on the back side, and is lit or blinked according to an operation state or the like.

The volume jog 126 is provided as a dial key for adjusting the audio signal level output from the STR 60, that is, for example, the volume output from the speakers SP (L) (R).

1-3. STR (Internal) Next, the internal configuration of the STR 60 will be described. An example of the internal configuration of the STR 60 is shown in the block diagram of FIG. In the STR 60, three types of audio signals, an audio signal transmitted via the IEEE 1394 bus 116, an audio signal of a tuner provided in the STR 60, and an external analog audio signal input from the analog input terminal 78 can be input. It is said.

IEEE 1394 interface 61
Is provided for transmitting and receiving data to and from another external device via the IEEE 1394 bus 116. Thus, the STR 60 is configured to be able to transmit and receive AV data with the outside and transmit and receive various commands. In the IEEE1394 interface 61,
It demodulates a packet received via the IEEE 1394 bus 116 and extracts data included in the demodulated packet. The extracted data is converted into data in a format suitable for internal data communication and output. For example, assume that audio data is transmitted from another AV device via the IEEE 1394 bus 116. IEEE1
The 394 interface 61 receives the transmitted audio data and performs demodulation processing on the packet. In this case, for example, the data is converted into a data format of a digital audio data interface called IEC958 and the demodulation processing unit 63 Output.

The demodulation processing section 63 performs a required demodulation processing according to, for example, the IEC958 format on the input audio data, and outputs the data to the digital filter 64.

The digital filter 64 mainly has a function of removing jitter from, for example, input audio data. The data output from the demodulation processing unit 63 has different sampling frequencies in accordance with the difference of the transmission source device and the like. In the digital filter 64, these different sampling rates are used. Is also converted to a sampling frequency of 44.1 KHz and output. Thus, 44.1
Audio data converted to a signal format with a sampling frequency of KHz is a DSP (Digital Signa
l Processor) 65. For example, when audio data in a signal format with a sampling frequency of 44.1 KHz is transmitted from the transmission source, the demodulation processing unit 63 and the digital filter 6
4, the audio data is transmitted directly from the IEEE 1394 interface 61 to the DSP 65.

The DSP 65 performs various necessary signal processing on the audio data. For example, an equalizing process according to the equalizer setting is also executed here. Then, the audio data subjected to the signal processing is converted to A /
Output to the digital filter 69 of the D / D / A unit 66.

The A / D / D / A section 66 is a circuit portion for performing analog-to-digital conversion processing and digital-to-analog conversion processing for audio signals. The audio data input to the digital filter 69 of the A / D / D / A unit 66 is converted to a signal as a voltage pulse train by being input to the D / A converter 68.
Then, it is input to the I-DAC converter 81. The I-DAC converter 81 converts the input voltage pulse train into a current. Here, although not shown, a reference level is provided in another system, and it is possible to vary the output current by operating the reference level. It can also be used for volume adjustment in the following level ranges.

In the amplifier 82, the I-DAC converter 8
1 is amplified and output to the speaker output terminal 83. Then, if the speakers SP (L) (R) are connected to the speaker output terminal 83, output as stereo sound is performed.

The tuner unit 77 is provided in the STR 60 and performs channel selection, demodulation processing, and the like on radio broadcast waves received by the antenna 76, and outputs the radio waves to the selector 79 as, for example, an analog audio signal. An analog audio signal input via the analog audio signal input terminal 78 is also input to the selector 79.

The selector 79 selects one of the tuner unit 77 and the analog audio signal input terminal 78 as an input source under the control of the system controller 70, for example, and converts the selected analog audio signal into an A / D signal.
Supply to the A / D converter 67 of the D / A section 66. The A / D converter 67 converts the input analog audio signal into digital audio data.

Here, when the digital audio data obtained by the A / D converter 67 is output as monitor sound, the D / A converter 68 → I−
The signal is output to the speakers SP (L) and (R) through the processing of the DAC converter 81 → the amplifier. Further, for example, for recording, the digital audio data obtained by the A / D converter 67 is
When it is necessary to transmit and output the digital audio data to another AV device via the four bus 116, the digital audio data is output to the modulation processing unit 80. The modulation processing unit 80 performs a modulation process conforming to the format of a digital audio data interface such as IEC958, and outputs the result to the IEEE 1394 interface 61. The IEEE 1394 interface 61 performs necessary processing such as packetization using the RAM 62, for example, to convert the data into a format conforming to the IEEE 1394 format. And IEEE1
The transmission output is performed to a target device via the 394 bus 116.

The system controller 70 includes, for example, a CP
U (Central Processing Unit), ROM 71, RAM 7
2 for controlling various operations of the STR 60.

Further, information from the receiving unit 73 and the operation unit 74 is input to the system controller 70. For example, the receiving unit 73 receives a wireless command signal transmitted from the remote controller RM, and outputs the received command signal to the system controller 70. The operation unit 74 includes, for example, various keys provided on a front panel, and operation information corresponding to an operation performed on the operation unit 74 is output to the system controller 70. The system controller 70 executes various control processes so as to obtain required operations in response to the command signal and operation information input as described above. In addition, the system controller 75 also performs display control on the display unit 75 so as to display, for example, the above-described command signal and operation information, and required contents according to the current operation status and the like. As described above, the display section 75 includes, for example, an FL tube display section and a segment display section.

1-4. FIG. 4 shows an internal configuration of the personal computer 113. The personal computer 113 shown in FIG.
Has an IEEE 1394 interface 209 as an interface for exchanging data with the outside. The IEEE 1394 interface 209 is
The connection to the IEEE 1394 bus 116 as an external data bus enables mutual communication with external devices.
The IEEE 1394 interface 209 is an IEEE 1394 interface.
The packet received via the 1394 bus 116 is demodulated, data included in the demodulated packet is extracted, and the extracted data is converted into a data format suitable for internal data communication.
Output to U201. Also, the data output under the control of the CPU 201 is input, and the packetizing and other IEEE
The modulation process according to the 1394 format is performed, and the IE
The signal is transmitted and output to the outside via the EE1394 bus 116.

The CPU 201 executes various processes according to a program stored in the ROM 202, for example. In this embodiment, in order to enable transmission and reception of various data according to the IEEE 1394 standard, the ROM
IEEE 1394 interface 20 to 202
9 is also stored. That is, the personal computer 113 is provided with a set (hardware and software) capable of transmitting and receiving data according to IEEE1394. Further, the RAM 203 appropriately stores data, programs, and the like necessary for the CPU 201 to execute various processes.

The input / output interface 204 is connected to a keyboard 205 and a mouse 206, and outputs operation signals supplied from these to the CPU 201. In addition, the input / output interface 204 includes:
A hard disk drive 207 having a hard disk as a storage medium is connected. The CPU 201 can record or read data, programs, and the like on the hard disk of the hard disk drive 207 via the input / output interface 204. In this case, the input / output interface 204 further includes a display monitor 20 for displaying images.
8 are connected. The internal bus 210 is, for example, a PC
It is constituted by an I (Peripheral Component Interconnect) or a local bus, etc., and interconnects the respective internal functional circuit units.

It should be noted that the IEEE, which is applied to this embodiment,
The example of the construction of a system interconnected by E1394 bus lines is not limited to the above-described embodiment, but is merely an example.

2. Data communication according to the present embodiment by IEEE1394 2-1. Outline Hereinafter, data communication according to the IEEE 1394 standard as the present embodiment will be described.

IEEE 1394 is one of the standards for serial data communication. As a data transmission method based on the IEEE 1394, there is an Isoch that performs periodic communication.
There are a asynchronous communication system and an asynchronous communication system that performs asynchronous communication regardless of the cycle. Generally, the Isochronous communication method is used for transmitting and receiving data, and the Asynchronous communication method is used for transmitting and receiving various control commands. And
Using one cable, transmission and reception can be performed by these two types of communication systems. Therefore, hereinafter, the present embodiment will be described based on the transmission form of the present embodiment according to the above-mentioned IEEE 1394 standard.

2-2. Stack Model FIG. 5 shows an IEEE 1394 stack model to which the present embodiment corresponds. In the IEEE 1394 format, the Asynchronous system (40
0) and the Isochronous system (500). Here, Asynchronous system (400)
And Physical Layer (301) at the bottom as a layer common to and Isochronous system (500).
(Physical layer) is provided, and a link layer is provided above the physical layer.
r (302) (link layer) is provided. Physic
The al Layer (301) is a layer for controlling signal transmission in hardware, and is a Link Layer.
(302) is a layer having a function of converting an IEEE 1394 bus into, for example, an internal bus specified for each device.

The Physical Layer (30
1), Link Layer (302), and Transaction Layer (401) described below.
Is Event / Control / Configura
Serial Bus Ma by Tion's line
Linked to the management 303. Also, AV
Cable / Connector 304 indicates physical connectors and cables for AV data transmission.

The Transaction Layer (401) is provided above the Link Layer (302) in the Asynchronous system (400). Transaction Layer (4
01) is a layer that defines a data transmission protocol as IEEE1394, and is a basic Asynchron.
As ous Transaction, WriteTransaction, Rea is described later.
d Transaction, Lock Transa
ction is defined.

Then, the Transaction Layer
er (401) for FCP (Function Control
l Protocol) (402). FCP (40
2) AV / C Command (AV / C Digital Inte
By using a control command defined as (rface Command Set) (403), it is possible to execute command control for various AV devices.

Also, the Transaction Layer
For the upper layer of r (401), Connection
Management Procedures (50
5) by using Plug (IEEE1394) described later.
Pl for setting the logical device connection relationship in
ug Control Registers (40
4) is defined.

In the upper layer of the link layer (302) in the isochronous system (500), CI
P Header Format (501) is defined, and this CIP Header Format (50) is defined.
SD-DVCR Realt in the form managed in 1)
im Transmission (502), HD-
DVCR Realtime Transmission
n (503), SDL-DVCR Realtime
Transmission (504), MPEG2-T
S Realtime Transmission (5
05), Audio and Music Realti
A transmission protocol such as me Transmission (506) is defined.

[0049] SD-DVCR Realtime Tr
answer (502), HD-DVCR R
ealtime Transmission (50
3), SDL-DVCR Realtime Tran
The transmission (504) is a digital V
This is a data transmission protocol corresponding to TR (Video Tape Recorder). SD-DVCR Realtime T
The data handled by the transmission (502) is S
D-DVCR recording format (5
08) according to the data sequence (SD
-DVCR data sequence (507))
It is said. HD-DVCR Realtime
Data handled by Transmission (503) is
HD-DVCR recording format
The data sequence (SD-DVCR datasequence (50) obtained according to the rule of (510)
9)). SDL-DVCR Realtime
The data handled by Transmission (504) is the SDL-DVCR recording form.
at (512) (SD-DVCR data sequence (5
11)).

MPEG2-TS Realtime T
transmission (505) is a transmission protocol corresponding to a tuner or the like corresponding to digital satellite broadcasting, for example, and the data handled by the transmission protocol is DVB recordin.
g format (514) or ATV recorder
data sequence (MPEG2-TS data) obtained in accordance with the ding format (515).
sequence (513)).

Also, Audio and Music
Realtime Transmission (50
6) is a transmission protocol corresponding to all digital audio equipment including the MD system of the present embodiment, for example, and the data handled by the transmission protocol is Audio and Mus.
A data sequence (Audio) obtained according to the rules of the ic recording format (517).
and Music data sequence).

2-3. FIG. 6 shows an example of the structure of a cable actually used as an IEEE 1394 bus. In this figure, connectors 600A and 600B are connected via a cable 601, and here, connectors 600A and 600B are connected.
The case where six pins of pin numbers 1 to 6 are used as the pin terminals of 00B is shown. Connectors 600A, 600
Regarding each pin terminal provided in B, pin number 1 is power supply (VP), pin number 2 is ground (VG), pin number 3 is TPB1, pin number 4 is TPB2, and pin number 5 is T
PA1 and pin number 5 are TPA2. And
The connection form of each pin between the connectors 600A and 600B is as follows: pin number 1 (VP) -pin number 1 (VP) pin number 2 (VG) -pin number 2 (VG) pin number 3 (TPB1) -pin number 5 ( TPA1) Pin number 4 (TPB2) -Pin number 6 (TPA2) Pin number 5 (TPA1) -Pin number 3 (TPB1) Pin number 6 (TPA2) -Pin number 3 (TPB2). Then, of the above-mentioned pin connection set, two pairs of twisted wires of pin number 3 (TPB1) -pin number 5 (TPA1) pin number 4 (TPB2) -pin number 6 (TPA2) are used to differentially signal. A signal line 601A for mutually transmitting the signals is formed, and two pairs of twisted wires of pin number 5 (TPA1) -pin number 3 (TPB1) pin number 6 (TPA2) -pin number 3 (TPB2) A signal line 601B for mutually transmitting signals is formed.

The two sets of signal lines 601A and signal lines 60
The signals transmitted by 1B are a data signal (Data) shown in FIG. 7A and a strobe signal (Strobe) shown in FIG. 7B. The data signal shown in FIG. 7A is output from TPB1 and TPB2 using one of the signal lines 601A and 601B, and is input to TPA1 and TPA2. The strobe signal shown in FIG. 7B is a signal obtained by performing a predetermined logical operation on a data signal and a transmission clock synchronized with the data signal, and has a frequency lower than the actual transmission clock. Have.
This strobe signal is supplied to the signal line 601A or the signal line 60.
1B, output from TPA1, 2 using the other signal line not used for data signal transmission, and TPB
Input to 1 and 2.

For example, the data signal and the strobe signal shown in FIGS. 7A and 7B are converted to a certain IEEE 1394 signal.
Assuming that the data is input to a corresponding device, the device performs a predetermined logical operation on the input data signal and strobe signal to generate a transmission clock (Clock) as shown in FIG. Then, it is used for required input data signal processing. In the IEEE 1394 format, by adopting such a hardware data transmission form, it is not necessary to transmit a high-speed cycle transmission clock between devices via a cable, and the reliability of signal transmission is improved. In the above description, the specification of 6 pins is described. However, in the IEEE 1394 format, the power supply (VP) and the ground (VG) are omitted, and the 4-pin consisting of only two sets of twisted signal lines 601A and 601B is used. There is also a specification. For example, in the MD recorder / player 1 of the present embodiment, consideration is given to providing a simpler system for the user by using the 4-pin cable.

2-4. Bus Connection Between Devices FIG. 8 schematically shows an example of a mode of connection between devices using an IEEE 1394 bus. In this figure, devices A, B,
Five devices (Node) of C, D, and E are IEEE139
The case where they are communicably connected by four buses (that is, cables) is shown. IEEE 1394
In the interface, I, like devices A, B, C
A so-called "digi-chain connection" in which connections are made in series by the EEE1394 bus is made possible. FIG.
In the case of, a so-called "branch connection" in which a certain device and a plurality of devices are connected in parallel as shown in the connection form between the device A and the devices B, D, and E is also possible. As a whole system, a maximum of 63 devices (Nodes) are used by using both the branch connection and the daisy chain connection.
Can be connected. However, depending on the daisy chain connection, a maximum of 16 units (16 pops) can be connected. Further, the terminator required for SCSI is not required for the IEEE 1394 interface. In the IEEE 1394 interface, it is possible to perform mutual communication between devices connected by the daisy chain connection or the branch connection as described above. That is, in the case of FIG.
Mutual communication between arbitrary devices among B, C, D, and E is enabled.

In a system in which a plurality of devices are connected by an IEEE 1394 bus (hereinafter, also referred to as an IEEE 1394 system), No assigned to each device is assigned.
The process of setting the deID is actually performed. This process is schematically shown in FIG. Here, in the IEEE 1394 system according to the connection form shown in FIG.
Assuming that a cable is unplugged and inserted, a power supply of a certain device in the system is turned on / off, a spontaneous generation process is performed by a PHY (Physical Layer Protocol), etc., a bus reset occurs in the IEEE 1394 system. Thereby, IEEE13 is established between the devices A, B, C, D, and E.
A process of performing a bus reset notification to all devices via the 94 bus is executed.

As a result of this bus reset notification, FIG.
As shown in (1), by performing communication (Child-Notify), a parent-child relationship is defined between adjacent device terminals. That is, Tr between devices in the IEEE 1394 system
Build the ee structure. Then, a device as a root is defined according to the construction result of the tree structure. The root is a device in which all terminals are defined as children (Ch; Child). In the case of FIG. 9B, the device B is defined as a root. Conversely, for example, the terminal of the device A connected to the device B as this route is defined as a parent (P; Parent).

After the Tree structure and the route in the IEEE 1394 system are defined as described above, subsequently, as shown in FIG. -An ID packet is output. Then, the route sequentially grants (grants) to this Node-ID, so that the IEEE
The address of each device in the E1394 system, that is, the Node-ID is determined.

2-5. Packet In the IEEE 1394 format, as shown in FIG. 10, an isochronous cycle (nomi
The transmission is performed by repeating a nal cycle) cycle. In this case, 1 Isochronous cy
cle is 125 μsec, and the band is 100
MHz. In addition, Isochronous c
It is stipulated that the cycle of the cycle may be other than 125 μsec. And this Isochr
The data is packetized and transmitted for each on cycle.

As shown in this figure, Isochrono
At the top of the us cycle, 1 Isochronou
Cycle Start indicating the start of s cycle
Packet is arranged. This Cycle Star
tPacket is an IEEE standard defined as Cycle Master, although detailed description is omitted here.
The generation timing is indicated by one specific device in the E1394 system. Cycle Start P
Following the acket, IsochronousPac
ket is preferentially arranged. Isochronous
As shown in the figure, Packets are packetized for each channel, are arranged in a time-division manner, and are transferred (Isochronous substitutions).
Also, Isochronous subactions
In Iso, the delimiter for each packet is Isochron.
A pause section called ous gap (for example, 0.05 μ
sec) is provided. Thus, IEEE 1394
In the system, one transmission line uses Isochron.
It is possible to transmit and receive nous data in multiple channels.

Here, for example, as stream data,
When it is considered that compressed audio data compressed in a predetermined format is transmitted by the Isochronous method, the compressed data is transferred at a transfer rate of 1.times.
If it is 4 Mbps, 1I which is 125 μsec
At least about 20 Mbytes of ATRAC data is transferred to the Isoc cycle every sochronous cycle cycle.
When transmitted as a long packet, chronological continuity (real-time property) is ensured. For example, when a certain device transmits stream data by isochronous communication, a detailed description thereof will be omitted here.
For an RM (Isochronous Resource Manager), I
Request the size of sochronous packets.
In the IRM, the current data transmission status is monitored and permission / non-permission is given. If the permission is given, the stream data is transmitted to the Isochronou according to the designated channel.
s Packet and can be transmitted. This is called bandwidth reservation in the IEEE 1394 interface.

In the band of Isochronous cycle, Isochronous subacti
ons using the remaining band that is not used by Async
Hourous subactions, ie Asyn
A chronous packet transmission is performed. In FIG. 10, two As of Packet A and Packet B are shown.
An example in which an asynchronous packet is transmitted is shown. Asynchronous Pac
After the ket, ack gap (0.05 μsec)
A signal called ACK (Acknowledge) accompanies the idle period. ACK is transmitted as As
In the process of “ynchronous Transaction”, in order to notify the transmitting side (Controller) that some asynchronous data has been received, the receiving side (Target) is implemented in hardware.
This is the signal output from t). Also, Asynchr
Before and after a data transmission unit consisting of an onous packet and an ACK following the same packet, a su of about 10 μsec is set.
A pause period called a "action gap" is provided. Here, the stream data is transmitted by the Isochronous Packet, and the asynchronous data is transmitted.
If the command is transmitted by the onus Packet, the stream data and the command can be apparently transmitted at the same time.

2-6. Transaction rules In the process transition diagram of FIG. 11A, Asynchrono
A basic communication rule (transaction rule) in the us communication is shown. This transaction rule is defined by the FCP. As shown in FIG. 11A, first, in step S11, Requester
The (transmission side) transmits a Request to the responder (reception side). In Responder,
When this Request is received (step S12),
First, the acknowledgment is returned to the Requester (step S13). On the transmitting side, Acknow
By receiving “edge”, it is recognized that the Request has been received on the receiving side (step S14). Thereafter, the responder responds to the request received in step S12,
nse to the Requester (step S1
5). The Requester receives the Response (Step S16), and responds to the Response.
Acknowledgment is transmitted to der (step S17). Acknow on Responder
Receiving “edge” recognizes that the response has been received by the transmission side.

Req transmitted according to FIG.
FIG. 11 shows the east Transaction.
As shown on the left side of (b), Write Requests
t, Read Request, Lock Request
It is roughly defined into three types, st. Write
Request is a command for requesting data writing, and Read Request is a command for requesting data reading. Lock Request
Will not be described in detail here, but swap com
This is a command for a pair, a mask, and the like.

The Write Request is an Asynchronous Pac, which is illustrated and described later.
Three more types are defined according to the data size of the command (operand) to be stored in the KET (AV / C Command Packet). Write Req
west (data quadlet) is Async
The command is transmitted using only the header size of the strong packet. Write Request
(Data block: data length = 4
byte), Write Request (data
block: data length @ 4 bytes)
Is to transmit a command by adding a data block to a header as an Asynchronous Packet. The two differ in whether the data size of the operand stored in the data block is 4 bytes or more.

Read Request is similarly performed,
O to store in Asynchronous Packet
Depending on the data size of perand, Read Re
quest (data quadlet), Read
Request (datablock: data le
ngth = 4 bytes), Read Request
(Data block: data length $ 4
byte) are defined.

In addition, Response Transac
The timing is shown on the right side of FIG. For the three types of Write Request described above, Write Response or No Re
spose is defined. In addition, Read Requ
east (data quadlet)
d Response (data quadlet) is defined, and ReadRequest (data blo
ck: data length = 4 bytes) or R
ead Request (data block: da
ta length @ 4 bytes)
d Response (datablock) is defined.

For the Lock Request, L
ok Response is defined.

2-7. Addressing FIG. 12 shows the addressing structure of the IEEE 1394 bus. As shown in FIG.
In the 1394 format, 64 bits are prepared as a register (address space) of a bus address. The upper 10-bit area of this register is the IEEE1394
A bus ID for identifying a bus is shown, and as shown in FIG.
Bus IDs can be set. bus
# 1023 is defined as a local bus.

In FIG. 12A, the 6-bit area following the bus address is the IEEE indicated by the bus ID.
Node of device connected to each E1394 bus
Indicates the ID. As shown in FIG. 12C, the Node IDs are 63 Nodes # 0 to # 62.
e ID can be identified. Bus ID and No.
The area of a total of 16 bits indicating the de ID is an AV
A device connected to a certain bus is specified on the IEEE 1394 system by the bus ID and the Node ID.

In FIG. 12A, a 20-bit area following the Node ID is a register space.
And 28 following this register space
The bit area is register address. The value of register space is [F
FF FFh] and reg shown in FIG.
and the contents of the register are defined as shown in FIG. register
er address designates the address of the register shown in FIG.

Briefly, in the register shown in FIG. 12E, for example, the address 512 [00 00 02
00h] Serial Bus-depen
By referencing dent Registers, Is
ochronous cycle cycle time,
Information on available channels can be obtained. Address 10
Confi starting from 24 [0 00 04 00h]
node Uniqu
Necessary information regarding the Node such as e ID and subunit ID is stored. These Node Uni
The "que ID" and "subunit ID" are necessary when the device is actually connected to the IEEE 1394 bus and the connection relationship is established.

The Node Unique ID is device information that is unique to each device and is expressed by 8 bytes.
It is assumed that there is no other device having the mode Unique ID.

The subunit ID is a Vend indicating the name of the manufacturer of the device as the Node.
er Name (module_vender_ID) and Model Name (model_
ID).

The Node Unique ID is unique to each device and is device identification information expressed by 8 bytes. Even if the devices are of the same model, it is assumed that there is no device having the same Node Unique ID. Is done. The Vendor Name is information indicating the name of the manufacturer of the Node.
lName is information indicating the model of the Node. Therefore, these Vendor Name and Mod
There will be devices that have the same el Name in common. Therefore, by referring to the contents of the Configuration ROM, the Node attached to the model is referred to.
Unique ID can be identified, and s
From the contents of the unit ID, it is possible to identify the manufacturer and model of the Node. Note that, while the Node Unique ID is indispensable, the Vendor Name and Model Name
Is an option and does not necessarily need to be set in the device.

2-8. CIP FIG. 13 shows the structure of CIP (Common Isochronos Packet). That is, the Isochron shown in FIG.
ow Packet is a data structure. As described above, ATRAC data (audio data), which is one of the recording / playback data supported by the MD recorder / player of the present embodiment, is transmitted and received by Isochronous communication in IEEE1394 communication. . That is, the amount of data enough to maintain the real-time property is determined by the Isochronous Pack.
, and store it in 1isochronous cycle
The data is sequentially transmitted for each e.

The first 32 bits (1 quadle) of the CIP
t) is a 1394 packet header. 139
In the 4-packet header, the 16-bit area is data_Length, the 2-bit area is tag, the 6-bit area is channel, and the 4
The bit is tcode, and the following four bits are sy. Then, 1 quad following the 1394 packet header
In the let area, header_CRC is stored.

2 quadl following header_CRC
The area of et serves as a CIP header. In the upper 2 bytes of the upper quadlet of the CIP header, '0'
'0' is stored, and the subsequent 6-bit area indicates an SID (transmission node number). The 8-bit area following the SID is D
BS (data block size), which indicates the size of a data block (unit data amount of packetization). Subsequently, areas of FN (2 bits) and QPC (3 bits) are set, the number of divisions at the time of packetization is indicated in the FN, and the qu added for division is indicated in the QPC.
The number of adlets is shown. SPH (1 bit) indicates the flag of the header of the source packet, and DBC stores the value of a counter for detecting packet loss.

The upper two bytes of the lower quadlet of the CIP header store “0” and “0”, respectively. Subsequently, areas of FMT (6 bits) and FDF (24 bits) are provided. The signal format (transmission format) is shown in the FMT, and the value shown here makes it possible to identify the data type (data format) stored in the CIP. Specifically, MPEG
Stream data, Audio stream data, digital video camera (DV) stream data, and the like can be identified. The data format indicated by the FMT is, for example, the CIP Header shown in FIG.
SD-DVCR managed by Format (401)
Realtime Transmission (50
2), HD-DVCR Realtime Trans
mission (503), SDL-DVCR Rea
ltime Transmission (504), M
PEG2-TS Realtime Transmit
session (505), Audio and Music
Realtime Transmission (50
6). The FDF is a format-dependent field, and is an area indicating a further subdivided classification of the data format classified by the FMT. If the data is audio-related data, for example, whether the data is linear audio data or MID
It is possible to identify whether the data is I data. For example, in the case of ATRAC data of the present embodiment, first, FMT
Indicates that the data is in the category of the audio stream data, and the FDF stores a specific value in accordance with the regulations, thereby indicating that the audio stream data is ATRAC data.

Here, if the FMT indicates MPEG, for example, the FDF stores synchronization control information called TSF (time shift flag).
DVCR (Digital Video Camera) by FMT
, The FDF is defined as shown below in FIG. Here, 5
0/60 (1 bit) defines the number of fields per second, and STYPE (5 bits) indicates whether the video format is SD or HD.
T indicates a time stamp for frame synchronization.

Following the CIP header, FMT, F
Data indicated by DF is stored by a sequence of n data blocks. When the FMT and FDF indicate that the data is ATRAC data, ATRAC data is stored in this data block area. After the data block, data_CRC is finally placed.

2-9. Connection management In IEEE1394 format, "plug"
According to the logical connection concept called IEEE 1394,
A connection relationship between devices connected by the bus is defined. FIG. 14 shows an example of a connection relationship defined by plugs. In this case, VTR1, VTR2, and set-top box (ST) are connected via an IEEE 1394 bus.
B; digital satellite broadcast tuner), monitor device (Mon
itor) and digital still camera (Camer)
The system configuration to which a) is connected is shown.

Here, as a connection form by an IEEE1394 plug, a point to point-c
connection and broadcast conn
There are two forms, the “action”. point
The to point-connection is a connection mode in which the relationship between the transmitting device and the receiving device is specified, and data transmission is performed between the transmitting device and the receiving device using a specific channel. On the other hand, broadc
The “ast connection” is for transmitting data without specifying a receiving device and a channel to be used in a transmitting device. The receiver performs reception without particularly identifying the transmission device, and if necessary, performs necessary processing according to the content of the transmitted data. In the case of FIG. 14, point to point-connect
In the state, the STB is set to be transmitted, the VTR1 is set to be received, and data is transmitted using the channel # 1, and the digital still camera is set to transmit, the VTR2 is set to receive, and the channel # 2 is set. Are set so that data transmission is performed by using the. Also, from a digital still camera, b
A state in which data transmission is set also by the broadcast connection is shown. In this case, the broadcast connection is used.
A case is shown in which the monitor device receives the data transmitted by the “tion” and performs a required response process.

The connection form (plug) as described above is based on the PCR (Plug Control) provided in the address space of each device.
orol Register). FIG. 15 (a)
oPCR [n] (output plug control register)
15B shows the structure of iPCR [n] (input plug control register).
The size of each of these oPCR [n] and iPCR [n] is 32 bits. In the oPCR shown in FIG. 15A, for example, if “1” is stored in the on-line of the upper 1 bit, the broadcast
The transmission is indicated by nection,
When '0' is stored, the channel indicated by the channel number in the 6-bit area from the upper 11th bit indicates a point to point c.
The transmission is indicated as connection. Also,
Also in the iPCR of FIG. 15B, for example, if “1” is stored for the on-line of the upper 1 bit, it indicates that the reception is performed by the broadcast connection and “0” is stored. When,
Channel of 6-bit area from upper 11th bit
The data transmitted by the channel indicated by the number is point-to-point connect
This indicates that the transmission is to be performed.

Then, the broadcastC in the oPCR shown in FIG. 15A and the iPCR shown in FIG.
The connection counter has a broadcast
When the transmission / reception is performed by the cast connection, the broadcast connection is performed.
Stores the number of nodes that have been set up with Tion. In addition, the point-to-point connect in the oPCR of FIG. 15A and the iPCR of FIG.
The point to point is included in the ion counter.
In the case where transmission / reception is performed by int connection, the number of nodes having point to point is shown.

2-10. Command and Response in FCP Data transmission by Asynchronous communication is defined by the FCP (402) shown in FIG. Therefore, here, a transaction defined by the FCP will be described.

As an FCP, Asynchronou
Write Transac specified in s communication
Tion (see FIG. 11). Therefore, the transmission of the AUX data in the present embodiment is also performed by the FCP using the Write in the Asynchronous communication.
This is performed by using Transaction. Equipment that supports FCP is Command
/ Response register, and then Command / Response as described with reference to FIG.
A transaction is realized by writing a Message to a register.

In the process transition diagram of FIG.
As a process for the MMAND transmission, as shown in step S21, the Controller is set to Transa.
Generates a request for an action and writes
A process for transmitting a Request Packet to the Target is executed. In the target, the Write Request Pa
Receives the ticket and sends the Command / Responc
Write data to the e register. At this time, the target transmits an acknowledgment to the controller, and the target transmits the acknowledgment.
r, this Acknowledge is received (S23).
→ S24). The series of processing up to this point is COMMAND
This is a process corresponding to the transmission.

Subsequently, in response to COMMAND, R
As a process for ESPONSE, the Target sends a Write Request Packet (S25). The Controller receives this, and writes data to the Command / Response register (S26). Also, Cont
In the roler, Write Request Pa
In response to the receipt of the ticket, the target receives an Ack
A nowledg is transmitted (S27). In the Target, by receiving this Acknowledg, Wr
item Request Packet is Contro
It knows that it was received by the ller (S28). In other words, CO from Controller to Target
The MMAND transmission process and the RESPONSE transmission process from the Target to the Controller responding to the MMAND transmission process are performed by FCP data transmission (Transacti
on).

2-11. AV / C command packet As described with reference to FIG. 5, Asynchronous
In communication, the FCP can communicate with various AV devices using AV / C commands. In Asynchronous communication, Writ
The three types of transactions, e, Read, and Lock, are defined as described with reference to FIG.
west / Response Packet, Read
Request / Response Packet,
Lock Request / Response Pac
ket is used. In FCP, Write Transaction is used as described above. FIG. 17 shows the Write Requests.
t Packet (AsynchronousPacket (Write Reques
t for Data Block)). In the present embodiment, the Write Request Pack
et is used as an AV / C command packet.

This Write Request Pac
top 5 quadlets in ket (1st to 5th qulets)
adlet) is a packet header. The first quadlet of the packet header
Area of upper 16 bits in
n_ID indicates the NodeID of the data transfer destination (destination). The subsequent 6-bit area is tl (transact label), which indicates a packet number. The next two bits are rt (retry c
ode), indicating that the packet is the first transmitted packet or the retransmitted packet. In the following 4-bit area, tcode (transaction code) indicates a command code. The subsequent 4-bit area is pri (prior
ity), which indicates the priority of the packet.

The upper 16-bit area in the second quadlet is the source_ID, and indicates the Node_ID of the data transfer source. Also, the second quadl
The lower 16 bits of the “et” and the total 48 bits of the entire third quadlet are destination_offse.
t, and the COMMAND register (FCP_COMM
AND register) and the address of the RESPONSE register (FCP_RESPONSE register). The above destination_
ID and destination_offset are I
This corresponds to a 64-bit address space defined in the EEE1394 format.

The area of the upper 16 bits of the fourth quadlet is defined as data_length, and data_length is described later.
The data size of a field (a region surrounded by a thick line in FIG. 17) is shown. The following lower 16-bit area is an extended_tcode area.
This area is used when extending tcode.

The 32-bit area as the fifth quadlet is a header_CRC,
A CRC calculation value for performing a checksum of the header is stored.

The sixth q following the Packet header
A data block is arranged from the uadlet, and datafi is added to the head of the data block.
An eld is formed. The upper 4 bytes of the sixth quadlet, which is the head of the datafield, include CTS (C
ommand and Transaction Set) are described. this is,
Indicates the ID of the command set of the Write Request Packet. For example, if the value of this CTS is set to [0000] as shown in the figure, d
The content described in the “atafield” is defined as an AV / C command. That is, this Wr
The item Request Packet indicates that the packet is an AV / C command packet. Therefore, in this embodiment, since the FCP uses the AV / C command, [0000] is described in this CTS.

The 4-bit area following the CTS is ctyp
e (Command type; function classification of command) or response indicating processing result (response) corresponding to command
Is described.

FIG. 18 shows the above-mentioned ctype and respo.
The definition content of nse is shown. ctype (Comman
As d), [0000] to [0111] can be used, and [0000] is CONTROL,
[0001] is STATUS, [0010] is INCU
IRY, [0011] is defined as NOTIFY,
[0100] to 0111 are currently undefined (reser
ved). CONTROL is a command to control the function from outside, STATUS is a command to check the status from outside, INQUIRY is a command to inquire whether the control command is supported, and NOTIFY is a request to notify the status change to outside. Command. As the response, [1000] to [1111] are used, and [1000] is NOT IMPLEMENTE.
D, [1001] is ACCEPTED, [1010] is REJECTED, [1011] is INTRANSIT
ION, [1100] is IMPLEMENTED / ST
ABLE, [1101] is CHANGED, [111]
0] is reserved, [1111] is INTERI
M. These respo
nse is used properly according to the type of command. For example, resp corresponding to the command of CONTROL
Once, NOTIMPLEMENTED, A
CCEPTED, REJECTED, or INTER
Any one of the four IMs is used depending on the situation on the responder side or the like.

In FIG. 17, ctype / respo
In the 5-bit area following nse, subunit-t
ype is stored. Is a subunit-type
Indicates a subunit of the destination of the COMMAND or the source of the RESPONSE (device). In the IEEE 1394 format, a device itself is called a unit, and a type of a functional device unit provided in the unit (device) is called a subunit. For example, taking a general VTR as an example, a unit as a VTR includes a tuner that receives terrestrial and satellite broadcasts,
Two subs with video cassette recorder / player
It has a unit. The subunit-type is defined, for example, as shown in FIG.
That is, [00000] is Monitor, [0000]
1] to [00010] are reserved, [0001]
1] is a disc recorder / player,
[00100] is VCR, [00101] is Tune
r, [00111] is Camera, [01000]-
[11110] is reserved, [11111]
Is un used when subunit does not exist
It is defined as it.

In FIG. 17, the above subunit-t
In the 3 bits following “ype”, the same type of subunit
Is stored, an id (Node_ID) for specifying each subunit is stored.

The opcode is stored in the 8-bit area following the id (Node_ID), and the operand is stored in the 8-bit area. opcod
e is an operation code, and information (parameters) required by the opcode is stored in the operand. These opco
de is defined for each subunit, and subunit
Each table has a unique opcode list table. For example, if the subunit is a VCR, opc
As the mode, for example, as shown in FIG. 19B, various commands such as PLAY (reproduction), RECORD (recording) and the like are defined. opera
nd is defined for each opcode.

As the datafield in FIG. 17, 32 bits of the sixth quadlet are required. If necessary, an operand can be added subsequently (Additional operation).
rands). Data field is followed by data
a_CRC is located. If necessary, use dat
It is possible to place padding before a_CRC.

2-12. Plug Here, a plug in the IEEE 1394 format will be schematically described. As used herein, the term “plug” refers to the IEEE 1394, as described above with reference to FIG.
A logical connection relationship between devices in the format.

As shown in FIG. 20, Asynchron
The data (request) such as a command valid in the ous communication is transmitted from the producer to the cons.
transmitted to the user. The product here
er and consumer are IEEE 139, respectively.
4 A device that functions as a transmitting device and a receiving device on the interface. And the consumer
In the figure, as shown by hatching in the figure, the producer
And a segment buffer in which data writing is performed. In addition, IEEE 1394
In the system, a specific device is named producer, c
Information to specify as onsumer (Connection
Management Information) is stored at a predetermined position in a plug address indicated by a shaded line in the figure. The segment buffer is arranged following the plug address. con
The address range (data amount) that can be written to the segment buffer of the summer is c as described later.
limitCountr managed by the onsumer side
defined by the register.

FIG. 21 shows the structure of the address space of the plug in the asynchronous communication. 6
The address space of the 4-bit plug is shown in FIG.
As shown in (a), the No. of 2 16 (64K)
divided into de. Then, the plug is set in the address space of each Node as shown in FIG. Then, as shown in FIG. 21C, each plug has a register (register) indicated by a shaded area.
er) and a segment buffer (S
egment Buffer). The register contains
As described below, the transmitting side (producer)
Information (for example, a transmission data size and a receivable data size) necessary for data transmission / reception management between the terminal and the receiving side (consumer) is stored. The segment buffer is an area where data transmitted from the producer to the consumer is to be written, and is defined to be, for example, a minimum of 64 bytes.

FIG. 22A shows plug addresses. That is, the same contents as those in FIG. 21C are shown. As shown in the figure, the register is arranged at the head of the plug address, and the segment buffer is arranged following the register. As a structure in the register, as shown in FIG. 22B, for example, a 32-bit producer Count re
gister is arranged, followed by 32-bit li.
mit Count register [1]-[1
4] is arranged. In other words, one producer
Count register and 14 limit C
An out register is provided. In this case, the limit Count register [1
4], an unused area is provided.

The plug structure shown in FIGS. 22A and 22B is specified by an offset address (Address Offset) as shown in FIG. 22C. That is, the offset address 0 corresponds to the consumer port (p
.., and the offset address 4, 8, 12,.
0 is the producer port [1] to
Specify [14]. The offset address 60 is res
unused (unus)
ed), and an offset address 64 indicates a segment buffer.

FIG. 23 shows the producer side and the con
The structure of the plug on both the summer side is shown. A
In the plug structure of the synchronous communication,
By writing to the producerCount register, writing to the limitCount register, and writing to the segment buffer in accordance with the transmission / reception procedure described later, Asynchr
Implement onous communication. These writings are processing as the Write Transaction described above.

[0108] producer Count regi
ster is a consumer by producer
Writing is performed on r. producer is
Producer Counter at own address
After writing information about the data transmission on the producer side to the register, the producer C
the contents of the "out register"
r's producer Count register
Write to. producer Count r
For the register, the producer is consume
The data size to be written to the r segment buffer is information on the data size to be written by one writing process. That is, producer is p
The process of notifying the data size to be written to the segment buffer of the consumer is performed by writing the producer Count register.

On the other hand, limit Count
The register is pro by the consumer
The data is written to the ducer. consum
er side, own limit Count regi
one of the s ters [1] to [14] specified in correspondence with the producer.
Write the capacity (size) of its own segment buffer to register [n], and write this limit C
The contents of "out register [n]" are
Write to t Count register [n].

On the producer side, the amount of data to be written per time is determined according to the contents written to the limit Count register [n] as described above, and, for example, the data is written to its own segment buffer. . Then, the contents written to the segment buffer are written to the consumer. Writing to the segment buffer corresponds to data transmission in asynchronous communication.

2-13. Asynchronous Connection Transmission Procedure Subsequently, the plug (produ
Assuming the structure between the “Cer-consumer” and the processing transition diagram of FIG.
A basic connection / reception procedure for connection will be described. The procedure of the transmission / reception processing shown in FIG.
Under the environment defined by the FCP, the AV / C command (Write Req
east Packet). The AUX data handled in the present embodiment is also transmitted and received in the IEEE 1394 system using this transmission / reception procedure. However, the processing shown in FIG.
Asynchronous connect only
This indicates a communication operation as an ion, and a communication process corresponding to recording and reproduction of AUX data will be described later. In addition, Asynchronous connection
Actually, the transmission and reception of the acknowledg are executed as shown in FIG. 16 in response to the command transmission, but in FIG. 24, the acknowledg is transmitted.
The illustration of the transmission / reception processing for is omitted.

In the IEEE 1394 interface, the connection relationship between the plugs (devices) is the above-mentioned p.
In addition to the producer-consumer relationship, co
There is a relationship defined as a controller-target. On the IEEE 1394 system,
The device in which the producer-consumer relationship is defined does not necessarily match the controller-target relationship in the device. That is, p
In addition to the device specified as the producer, cont
There is a case where there is a device defined as having a role of a role. However, here, the product
er-consumer relationship and contro
An example in which the relationship as ller-target matches will be described.

In the transmission procedure shown in FIG. 24, first, as shown as step S101, a connect request is transmitted from a producer to a consumer. This Connect request is made by the producer
Is a command for making a connection request to the consumer, and the address of the register of the producer is set to c.
Tell the onsumer. This Connect request is sent to the consumer as the process of step S102.
Is received, on the consumer side, prod
Recognize the address of the register of the user. Then, in step S103, co is set as the response.
nsumer is a Conne to producer
Send ct reception. Then, in step S104, the producer receives this, so that the producer-consumer for the subsequent data transmission and reception is performed.
er is established.

When the connection is established as described above, in step S105, the connection is established.
er is the limit Cou for the producer.
ntregister ((hereinafter, simply “limit C
abbreviated as “out”)). Step S1
06, which has received this, by the processing of the subsequent step S107, the limit Counter
The t writing acceptance is transmitted to the consumer. Then, as the process of step S108,
r receives the limit Count write acceptance. Through this series of processing of the limitCount write request / write acceptance, the size of data to be written to the segment buffer (segment buffer capacity) is determined thereafter.

In the following step S109, pro
The segmenter sends a segment buffer write request to the consumer. Then, step S11
0, a segment buffer write request is received, and in response to this, con
The segmenter sends a segment buffer write acceptance to the producer. The producer receives the segment buffer write acceptance in step S112. By executing the processes of steps S109 to S112, the process of once writing data from the segment buffer of the producer to the segment buffer of the consumer is completed. Here, the data written by the processing of steps S109 to S112 is the Asynchronous data shown in FIG.
It is written by one transmission by a nous packet. Therefore, Asynchronous Pack
The size of the data transferred by the
Asynchronous Pac smaller than the data size specified by Count
If necessary data transmission is not completed due to transmission by the "ket", the processing of steps S109 to S112 is repeated within a range where the capacity of the segment buffer becomes full.

Then, steps S109 to S1 described above are performed.
When the write processing to the segment buffer shown in FIG. 12 is completed, as shown in the processing of step S113, p
From producer to consumer, pro
It transmits a ducer Count register (hereinafter simply abbreviated as producer Count) write request. In the consumer, step S11
In the process of 4, the producer Count is received and its own producer Countregis is received.
ter, and as a process of the subsequent step S115, the pr
transmitted to the Oducer. In step S116, the producer determines that the producer Cou
Receive nt write acceptance. As a result of this process, the process of steps S109 to S112
The data size transferred from r to the segment buffer of the consumer is notified to the consumer.

The processing in the subsequent step S117 includes the process shown in steps S113 to S116.
r Limit in response to r Count write processing
A series of processes for Count writing are executed. That is, as shown in steps S117 to S120, the link from the consumer to the producer is
Sends a mit Count write request, and responds to this transmission from the producer to the consumer.
A mit Count write acceptance is transmitted.

The processes in steps S109 to S120 are performed by Asynchronous Connection.
, A set of procedures as data transmission processing is performed. Here, for example, the data size to be transmitted is larger than the segment buffer capacity, and one step S10
If it is determined that the data transfer has not been completed by the processes from 9 to S120, this step S109 is performed.
Steps S120 to S120 can be repeatedly executed until the data transfer is completed.

When the data transfer is completed, as shown in step S121, the producer sets c to
A disconnect request is transmitted to the onsumer. The consumer receives the disconnect request in step S122, and transmits a disconnect acceptance in step S123. In step S124, the producer is D
By receiving the disconnect request, the Async
The data transmission / reception by the Hronous Connection is completed.

[0120] 4. Equalizer control function 4-1. Equalizer setting operation As understood from the above description, the STR of the present embodiment
Reference numeral 60 has a function as an audio amplifier. The DSP 65 in the STR 60 has a function as an equalizer for adjusting the sound quality of audio data to be output as sound to, for example, speakers or headphones. The equalizer is provided with a parametric equalizer.

However, as the STR 60 of the present embodiment, for example, in consideration of design convenience, miniaturization, etc.,
The panel of the main body is provided with only necessary minimum keys as shown in FIG. 2, for example. Therefore, the setting change of this parametric equalizer is performed, for example, in STR60.
If it is attempted to use an operator provided in the main body, for example, a parameter for setting the equalizer is displayed on the display unit 74, and a procedure such as changing the parameter by operating the jog dial 125 or the like is performed. However, this makes the operation procedure complicated, and for example, F
Since the number of characters that can be displayed on the L-tube display section 74A is about 14 characters, it is difficult to understand the parameter display. That is, the equalizer setting by operating the main body is not convenient. This is the same when, for example, the equalizer setting operation is performed by the remote controller RM instead of the operator of the main body.

Here, the AV system according to the present embodiment shown in FIG. 1 can be constructed so that various operations on, for example, the STR 60 and the STR-compatible CD machine 30 can be performed by the personal computer 113. You. That is, remote control via the IEEE 1394 data interface. Therefore, in the present embodiment, the parametric equalizer of the STR 60 can be set by the personal computer 113 using this remote control.

For this reason, the personal computer 113
For example, at least, operation application software capable of performing equalizer setting of the parametric equalizer of the STR 60 is installed. Then, the application software for operation is started, and STR6 is executed as follows.
The setting of the parametric equalizer of 0 is performed by the personal computer 113 side.

If the operation application software is started on the personal computer 113 and an operation for opening an equalizer setting window is performed, for example, the personal computer 113
The CPU 201 requests the STR 60 to transmit setting information on the current parametric equalizer in accordance with a program as operation application software, and stores the setting information transmitted from the STR 60 in, for example, the RAM 203. Then, referring to the setting information held in the RAM 203, for example, an EQ setting window WD as shown in FIG.
8 is displayed.

The EQ setting window WD displays the GUI (Graphical U) for setting the parametric equalizer of the STR 60.
This is a window to be performed by ser interface).
On the upper right side of the EQ setting window WD, for example, L,
R balance setting area A1 is displayed and STR6
It is also possible to adjust the left / right balance of stereo sound at 0. This is performed, for example, by dragging the lever display in the L / R balance setting area A1 in the left-right direction.

On the lower left side, an on / off setting button A2 is displayed. This on / off setting button A2
Is a button for switching on / off the parametric equalizer function in the STR 60. Each time the on / off setting button A2 is clicked, the button is switched on / off. A bank switching button A3 is displayed on the right side of the on / off setting button A2. The bank here refers to one set of parametric equalizer settings. For example, in the STR 60, a plurality of predetermined banks are prepared, and arbitrary parameters can be set for each bank. By switching the bank, the equalizer setting can be switched. As the EQ setting window WD of the present embodiment, the bank can be switched by a click operation on the bank switching button A3.

The on / off setting button A2
An EQ setting area A4 is arranged and displayed below the bank switching button A3. This EQ setting area A
In No. 4, the characteristics of the equalizer can be changed and set by a GUI operation described below.

[0128] In the EQ setting area A4, the horizontal axis direction indicates the frequency band, and the left to right ranges from low to high. Here, for example, the lowest frequency is 100H
The maximum frequency is about 10 kHz. The direction of the vertical axis indicates the gain, which can be set within a range of ± 10 dB, for example, as shown in the figure.
As is well known, a parametric equalizer can determine, for example, a point to be an operating point so as to continuously shift along a frequency axis, and determine the determined point. The equalizer characteristic is determined by changing the gain of the equalizer.

Here, when the EQ setting window WD is opened for the first time, the waveform line Ln based on the equalizer characteristic setting currently set in the designated bank is displayed in the EQ setting area A4. Has become. For example, in the case of FIG. 25, it is assumed that when the EQ setting window WD is first opened, a waveform line Ln indicated by a broken line is initially displayed.

Also, in this embodiment, when setting the equalizer characteristics of the parametric equalizer,
Points (operation points) that are three operation points at maximum are prepared. That is, as shown in the figure, a low-frequency point Pt-L for setting the low frequency, a mid-frequency point Pt-M for setting the medium frequency, and a high-frequency point Pt for setting the high frequency.
-H is prepared. Each of these operation points can be actually made to appear, for example, by the user placing the arrow-shaped cursor Cr at an arbitrary position in the EQ setting area A4 and performing a click operation. ing. For example, instead of changing the bank setting called from the STR 60 side, if an attempt is made to newly create a setting for a certain bank, the waveform line Ln
And EQ setting area A with no set points displayed
If a click operation is performed at an arbitrary position on 4, the operation point is displayed. The operation points that have appeared are the low frequency point Pt-L, the mid frequency point Pt-M,
Which of the high frequency points Pt-H is determined by the relative positional relationship in the frequency axis direction when three are finally displayed.

Then, for example, in changing the characteristic indicated by the waveform line Ln indicated by the broken line, it is assumed that the user wants to change the setting on the high frequency side. In this case, the user places the cursor Cr at the high frequency point Pt-H displayed on the waveform line Ln indicated by the broken line as shown in the figure. Then, by performing a so-called drag operation, the high frequency point Pt-H can be moved in any direction of up, down, left, and right. In other words, depending on the drag operation on the operation point, the frequency is varied by the moving component in the horizontal direction,
The gain can be varied by the vertical movement component, and the frequency and the gain can be changed simultaneously. For example, in this figure, a state in which the high frequency point Pt-H is dragged obliquely upward is shown, and the frequency is moved slightly lower and the operation is performed so as to increase the gain. It is. Also. Such a drag operation on the operation point can be performed on another low-frequency point Pt-L and another mid-frequency point Pt-M.

When the high frequency point Pt-H is moved as described above, the waveform line Ln changes as shown by a solid line, for example, according to the position of the moved high frequency point Pt-H. Thus, the equalizer characteristic changed by the operation of moving the operation point performed by the user is visually shown. Then, the equalizer characteristics thus changed are reflected as the equalizer characteristics of the STR 60, for example, when a predetermined determination operation or the like is performed. That is, the personal computer 113 transmits the information of the changed equalizer characteristics as a command to the STR 60 via the IEEE 1394 bus. The STR 60 sets the received equalizer characteristic, and thereafter, the DSP 65 adjusts the sound quality using the set equalizer characteristic. As will be described later, in addition to the frequency (FREQENCY) and the gain (GAIN), the parameter of the equalizer characteristic includes a parameter called SLOPE which is a gradient of the waveform line Ln between operation points. For example, an appropriate value may be automatically set based on the positional relationship of each operation point, or the value may be selected and determined by some predetermined operation.

Further, the EQ setting area A4 according to the present embodiment.
There are other conceivable operations for setting the equalizer characteristics in the above, and an example thereof is shown in FIG. In the equalizer characteristic setting operation shown in FIG. 26, for example, designation of an operation point is not performed. Then, instead, as shown in FIG. 26 (a) → (b), by dragging the cursor Cr on the EQ setting area A4, a waveform line corresponding to the equalizer characteristic that the user wants to set is drawn. To do. At this time, for example, as shown as a waveform line Ln1, a broken line is displayed, for example, according to the locus of the drag operation. For example, in a drag operation using a mouse or the like, it is highly likely that a smooth curve cannot be actually drawn well, or that a waveform line cannot be drawn as intended by the user. Therefore, after the drag operation is completed, calculation is performed on the waveform line Ln1 assumed to be drawn by the user, and correction is performed so that a curve as a more ideal waveform line is obtained. Is displayed as a solid waveform line Ln2 as shown in FIG. And this waveform line Ln
The characteristic indicated by 2 is set as the finally set equalizer characteristic. When obtaining the waveform line Ln2 from the waveform line Ln1, for example, a plurality of peak points are obtained in the waveform line Ln1.
This is treated as an operation point in FIG. Then, the frequency and gain at this operation point are determined, and the slope (SLOPE) between the operation points is determined based on the waveform shape.

According to the setting operation of the parametric equalizer characteristics as shown in FIGS. 25 and 26, the set point (operation point) of the parametric equalizer is determined by a so-called drag and drop operation, and then the frequency and the gain are determined. Can be determined at the same time. Therefore, the setting operation can be simplified. Further, in the present embodiment, the fact that the type of the equalizer itself is a parametric equalizer is also a factor of simplifying the operation. That is, for example, in a graphic equalizer, it is necessary to set a gain for each frequency band divided in advance, but since it is a parametric equalizer, in the EQ setting area A4 as shown in FIGS. The setting can be changed by arbitrarily dragging.

4-2. CURRENT EQ comm
man As described above, in order to set the parametric equalizer of the STR 60 on the personal computer 113 side, the standard of the IEEE 1394 interface must be used as long as a system in which the personal computer 113 and the STR 60 are connected by the IEEE 1394 bus 116 is constructed. It is necessary to prepare a command related to the equalizer setting as a command by the API according to the above.
For this reason, in the present embodiment, the IEEE1394
A command for performing equalizer control under the interface standard is CURRENTEQ co.
mmmand is defined.

CURRENT EQ command
Is defined on the API of IEEE1394 as being additionally defined and configurable by the vendor.
VENDER DEPENDENT Command is used. In addition, the personal computer 113
However, in order to reflect the parameter setting of the equalizer in the current STR 60 and perform initial display and the like on the EQ setting window WD, it is necessary to use the CURRENT EQ co
CURRENT EQ stat
send us command and its RESPONS
By E, the parameter setting of the equalizer in the current STR 60 is obtained. Also, ST changes in response to the setting change made to the EQ setting window WD.
In order to change the parameter of the equalizer in R60, CURRENT EQ command is set as CURRENT EQ command.
and is sent. Then, next, VEN
As DER DEPENDENT Command,
CURRENT EQ status commman
d and CURRENTEQ control command
The data structure of each command is shown below.

FIG. 27 shows the CURRENT EQ sta.
3 shows a data structure of tus command.
It should be noted that the structure shown in FIG.
It shows the contents of the datafield in the Request Packet (AV / C command packet).

As shown, CURRENT EQ
The status command is CTS 4
By storing “0h” in the bit area and storing “1h” in the ctype 4-bit area,
AV / C STATUS command is indicated. And, in the 8-bit area of opcode, VENDER DEPENDENT Command
The value “00h” indicating d is stored. In the area of a total of 3 bytes following the operands [0] to [2], a Comp uniquely assigned to each vendor is provided.
Any area for storing any ID. Here, open
08h, 00h, 4 in order from rand [0] to [2]
6h is stored to indicate a particular VENDER (manufacturer). Also, here, operand [3] ~
The total 4-byte area of [6] is the Company I
The value defined by VENDER indicated by D for convenience of operation is stored. upperan
Level (F0h) is stored in d [3], and open
Produ is stored in the 2-byte area of rand [4] [5].
ct code (01h, 01h) are stored, respectively. Also, Operand [6] contains Applicat.
ion code (01h) is stored.

Then, for operand [7] and thereafter, CURRENT EQ status commmm
The substantive contents as and are stored. opera
For the nd [7], the corresponding VENDER DEPEN
The value of Opcode as DENTCommand is to be stored. And here, CU
02h indicating that it is RRENT EQ command is stored. The following operand [8] is E
This is an area for Q info Type. EQ
The info Type is an area in which a value indicating the type of the equalizer is stored, and is defined as shown in FIG. For example, from Controller to Targ
When transmitting to “et”, FFh indicating “unknown” is stored and transmitted. Then, when transmitting RESPONSE from the Target side, a required value defined according to the type of the equalizer is stored as described in the lower part of the figure. For example, 00h for Bypass, 01h for FLAT, and a 3-band equalizer (3BAND E
In the case of Q), 02h is stored, and in the case of a parametric EQ, 03h is stored.

Also, in the structure shown in FIG.
After rand [9], EQ Type Speci
fic information is stored. This EQ Type Sp
The EQ includes the EQ of the above operand [8].
Depending on the type of the equalizer indicated by the info Type, the setting status of the parameter indicating the actual equalizer characteristic is indicated by a required numerical value. This EQ infoType is RESPONSE
Is sent only when the
CURRENT EQ status c sent from
ommand is not stored.

As an example, FIG.
[8] EQ info Type is Paramet
EQ Type in the case of ric EQ (03h)
3 shows the data structure of eSpecific. Note that, in this figure, the area of each byte after operand [9] is indicated by offset addresses 00h to xxh. First, in the 1-byte area of the offset address 00h, the number of bands n (Number of B) is set.
AND) is indicated. This corresponds to the number of operation points shown in FIG. Thereafter, the parameters for each band are indicated such that a continuous area of every three bytes is set. First, offset addresses 01h to 03h
BAND (1) in the area for each byte of
-GAIN, BAND (1) -FREQNCY, B
The value actually set as AND (1) -SLOPE is stored. Then, similarly, after the offset address 04h, BAND (1) -GAI
N, BAND (1)-FREQUENCY, BAND
(1) -SLOPE BAND (n) -GAIN,
BAND (n) -FREQUENCY, BAND (n)
The value of -SLOPE is stored. That is, as parameters, GAIN, FREQNC
Y, SLOPE are given.

For example, in the case of the parametric equalizer shown in FIG. 25, since the number of operation points is 3, the number of bands is n = 3, the EQ Type S
As the specific, 03h is stored in the Number of BAND area at the offset address 00h, and the GAINs of BAND (1) to (3) are stored using the 9-byte area at the offset addresses 01h to 09h. The values of FREQUENCY and SLOPE are shown. On the lower side of the structural diagram of FIG.
CURRENT EQ s sent from the controller
Specific examples of the status command and the RESPONSE are shown. As can be seen from the values shown here, the CTS-ctyp of RESPONSE
e is 0Ch and the command is STATUS c
Ommand is set to indicate that it is a RESPONSE. As understood from this structure, the number of operation points prepared in the EQ setting area is not limited to three, but is determined in consideration of usability such as actual operability. It is good.

FIG. 28 shows a CURRENT EQ con.
3 shows a data structure of the trol command. CURRENT EQ control command
mand is the CURRENT EQ previously shown in FIG.
It has basically the same structure as the status command. However, since 00h is stored in the 1-byte area as CTS-type, AV
/ C control command. And the EQ in of operand [8]
In the area of fo Type, a value for specifying the type of the equalizer is stored, and E and subsequent to operand [9] are stored.
Targ for Q Type Specific
The value of the equalizer characteristic to be set on the et side is stored. And a CURR having such a structure
ENT EQ control command
It is made to be transmitted from the Controller to the Target. Below the structural diagram of FIG. 28, the CURRENT EQ cont for the parametric equalizer
The rol command and a specific example of the RESPONSE are shown. In RESPONSE, CTS-c
By storing 09h in a 1-byte area as a type, AV / C control command
RESPONSE for nd.

FIG. 31 shows a personal computer 113.
13 is a process transition diagram showing a process for controlling the equalizer setting of the STR 60. In this figure, the personal computer 113 is a controller, STR
60 functions as a Target. This process is executed by the CPU 201 on the personal computer 113 side, and executed by the system controller 70 on the STR 60 side.

First, it is assumed that operation application software is activated on the personal computer 113 which is the controller. Then, in accordance with a predetermined operation, in step S201, E
It is assumed that the process for opening the Q setting window WD has been started. At this time, the CP of the personal computer 113
The U201 controls the IEEE 1394 interface 61 so that the CURRENT EQ status co.
Send mmmand.

The equalizer setting information for each bank is stored in the RAM 72 included in the system controller 70 of the STR 60. The equalizing process in the DSP 65 is performed based on the equalizer setting information of the bank that is currently selected. It is supposed to be done. In the STR 60 that is the target, the CURRENT EQ is processed as the process of step S202.
Upon receiving the status command, RA
Based on the equalizer setting information of the currently selected bank stored in M72, the EQ info Type
e and a required value are stored in EQ Type Specific and RESPONSE is returned.

In the personal computer 113, as the process of step S204, first, the RESPONS
E is received. And this received RESPONS
Based on the content of the EQ Type Specific in E, the current equalizer characteristics are initially displayed, for example, in the EQ setting area A4 of the EQ setting window WD.

The processing in step S205 is performed on the personal computer 113 side as shown in FIG.
Alternatively, as described in FIG. 26, the setting is changed according to the operation of the user. That is, display control is performed so that the waveform line Ln corresponding to the changed setting is displayed in the EQ setting area A4. Also, with this, STR
For 60, the changed parameter setting contents are
Stored in Q Type Specific and CURR
ENT EQ control command is transmitted and output.

CURRENT transmitted in this manner
EQ control command is STR
On the 60 side, reception is performed by the processing of step S206. And this received CURREN
T EQ control command EQ T
Based on the content of the type specific, the equalizer setting information of the bank to be controlled is rewritten from among the equalizer setting information of each bank stored in the RAM 72 as described above. That is, the setting of the parametric equalizer is changed. Thus, the personal computer 113
The control operation of changing the equalizer setting of the STR 60 by the operation on the side is realized.

Here, the case where the equalizer of the STR 60 is controlled is described. For example, the equalizer function of the STR-compatible CD machine 30 shown in FIG. 1 or other types of AV equipment not shown is shown. If there is a device having such a configuration, it is possible to configure so that equalizer control can be performed for these devices. Also, the GUI for setting the equalizer in the personal computer is not limited to those shown in FIGS. 25 and 26. The present invention is also applicable to digital data interfaces other than the IEEE 1394 standard.

[0151]

As described above, according to the present invention, for example, S
In a system in which a device such as a TR that functions as an amplifier device having a parametric equalizer and a control device such as a personal computer are connected via a data bus, a ST
It is possible to control the setting of the R parametric equalizer. For this control,
For example, a parameter related to the equalizer setting is transmitted as a command.

The parametric equalizer has a simpler and more intuitive setting than, for example, a graphic equalizer, so that the control on the personal computer side can be made simpler.
Also, for example, a device having an equalizer is relatively small,
Even in the case where it is difficult to provide a large scale operator for the equalizer on the panel, this can be compensated for by an easy operation on the personal computer side. On the personal computer side, by using the GUI for setting the equalizer, the operation becomes simpler and easier to understand. If the GUI is used to set parameters by a drag-and-drop operation, the operation becomes more intuitive and easy to use. And furthermore,
Since the frequency and the gain corresponding to the set point of the equalizing characteristic can be set at the same time by the AND-drop operation, the change setting of the parameter by the user becomes simpler and easier.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration example of an AV system as an embodiment of the present invention.

FIG. 2 is a front view showing a state of a front panel of the STR.

FIG. 3 is a block diagram showing an example of the internal configuration of an STR.

FIG. 4 is a block diagram illustrating an example of an internal configuration of a personal computer.

FIG. 5 is an explanatory diagram showing an IEEE 1394 stack model corresponding to the present embodiment.

FIG. 6 is an explanatory diagram showing a cable structure used for IEEE1394.

FIG. 7 is an explanatory diagram showing a signal transmission form in IEEE1394.

FIG. 8 is an explanatory diagram for explaining bus connection rules in IEEE1394.

FIG. 9 shows Node I on an IEEE 1394 system.
FIG. 9 is an explanatory diagram illustrating a concept of a D setting procedure.

FIG. 10 is an explanatory diagram showing an outline of packet transmission in IEEE1394.

FIG. 11 is a process transition diagram showing basic communication rules (transaction rules) in Asynchronous communication.

FIG. 12 is an explanatory diagram showing an addressing structure of an IEEE 1394 bus.

FIG. 13 is a structural diagram of a CIP.

FIG. 14 is an explanatory diagram showing an example of a connection relationship defined by a plug.

FIG. 15 is an explanatory diagram showing a plug control register.

FIG. 16 is a process transition diagram showing Write Transaction defined in Asynchronous communication.

FIG. 17: Asynchronous Packet
It is a structural diagram of (AV / C command packet).

FIG. 18 is an explanatory diagram showing the definition of ctype / response in an Asynchronous Packet.

FIG. 19 is an explanatory diagram showing an example of the definition contents of a subunit_type and an opcode in an Asynchronous Packet.

FIG. 20 is an explanatory diagram showing a plug structure in Asynchronous communication.

FIG. 21 is an explanatory diagram showing a plug address structure in Asynchronous communication.

FIG. 22 is an explanatory diagram showing a plug address structure in Asynchronous communication.

FIG. 23 is an explanatory diagram showing processing between plugs in asynchronous communication.

FIG. 24: Asynchronous Connect
It is an explanatory view showing a transmission procedure as an ion.

FIG. 25 is an explanatory diagram showing an example of an operation mode for an EQ setting window.

FIG. 26 is an explanatory diagram showing another example of an operation mode for the EQ setting window.

FIG. 27: CURRENT EQ status co
FIG. 3 is an explanatory diagram showing a data structure of mmand.

FIG. 28: CURRENT EQ control c
FIG. 4 is an explanatory diagram showing a data structure of an ommand.

FIG. 29 is an explanatory diagram showing the definition contents of EQ info Type.

FIG. 30: EQ corresponding to a parametric equalizer
FIG. 4 is an explanatory diagram showing the definition contents of Type Specific.

FIG. 31 is a processing transition diagram showing a processing operation for realizing equalizer control on the STR 60 by the personal computer.

[Explanation of symbols]

30 STR compatible CD machine 60 STR, 61, 209
IEEE 1394 interface, 75 display unit,
113 personal computer, 201 CPU

Continued on the front page (72) Inventor Eiji Igarashi 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Yoshiyuki Takaku 6-35-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Stock In-house (72) Inventor Takashi Sasaki 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo F-term in Sony Corporation (reference) 5E501 AA02 AA20 AB30 CB09 DA13 EA08 FA02 FA03 FA06 FA09 FA14 5J100 AA09 BA01 BC01 CA29 CA30 CA31 DA07 EA02 FA04

Claims (5)

[Claims] A communication unit capable of communicating with an external device via a data bus in a predetermined communication format; an operation unit; and a predetermined unit for a parametric equalizer based on an operation performed on the operation unit. Parameter setting means capable of variably setting the parameters of the external device having a parametric equalizer, by causing the communication means to execute the communication, so that the parameter set by the parameter setting means is parametric of the external device. Control means for executing control so as to be set for the equalizer. An equalizer control device, comprising: 2. The equalizer control device according to claim 1, wherein said parameter setting means has user interface means for realizing a graphical user interface. 3. The method according to claim 1, wherein the parameter setting means includes a drag-and-drop operation performed by the operation means as the graphical user interface.
The equalizer control device according to claim 2, wherein a predetermined parameter relating to an equalizing characteristic can be variably set in accordance with a drop operation. 4. The apparatus according to claim 3, wherein said parameter setting means is capable of simultaneously setting a frequency and a gain corresponding to one set point in response to said drag and drop operation. 3. The equalizer control device according to 1. 5. At least a first device, and a second device communicably connected to the first device via a data bus in a predetermined communication format and capable of executing a required operation. A communication system comprising: an operation unit; a parameter setting unit configured to variably set a predetermined parameter of a parametric equalizer based on an operation performed on the operation unit; Transmission control means for transmitting and outputting the parameter information set by the parameter setting means to the first device by the communication means, wherein the first device performs an equalizing process on the audio information. Based on the parameter information received and obtained, Communication system characterized by comprising a control means for changing settings for parameters in trick equalizer means.