JP2001237257A - Semiconductor device and method of mounting the device - Google Patents

Semiconductor device and method of mounting the device

Info

Publication number
JP2001237257A
JP2001237257A JP2000384424A JP2000384424A JP2001237257A JP 2001237257 A JP2001237257 A JP 2001237257A JP 2000384424 A JP2000384424 A JP 2000384424A JP 2000384424 A JP2000384424 A JP 2000384424A JP 2001237257 A JP2001237257 A JP 2001237257A
Authority
JP
Japan
Prior art keywords
semiconductor device
mounting
sealing resin
mounting pad
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000384424A
Other languages
Japanese (ja)
Inventor
Asao Murakami
朝夫 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2000384424A priority Critical patent/JP2001237257A/en
Publication of JP2001237257A publication Critical patent/JP2001237257A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of high connection reliability and a method of manufacturing the same by using one-point dispense coating, which is a cheap and high-productivity resin-supply method, in LSI mounting in which a pressure-welding method is used. SOLUTION: By arranging a plurality of solder-resist protuberances 2 inside a mounting pad, applying on-point coating of sealing resist to a position at the center with respect to the arrangement of the plurality of the solder-resist protuberances 2, and mounting a semiconductor device on a circuit substrate 1 by applying heat and pressure, each top of the solder-resist protuberances 2 formed on the peripheral parts of the circuit substrate 1 is penetrated by the sealing resist, and fillets of equal amount for each are formed in the inside.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置ならび
に半導体装置の製造方法に関し、さらに詳細には、封止
樹脂が均等に充填された半導体装置およびその実装方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a semiconductor device uniformly filled with a sealing resin and a method for mounting the same.

【0002】[0002]

【従来の技術】従来、ベアチップを実装する工法とし
て、圧接工法が知られている。この工法は、たとえば特
許公報第2770821号「半導体装置の実装方法およ
び実装」に開示されているように、はんだ、導電性樹脂
等の接合材料を供給する必要がなく、LSIの電極と基
板上のパッドとを、LSIと基板の間に充填する封止樹
脂の収縮力により、機械的な接触のみで電気的に接続さ
せる構造となっている。
2. Description of the Related Art Conventionally, a pressure welding method has been known as a method for mounting a bare chip. This method does not require supply of a bonding material such as solder or conductive resin, as disclosed in, for example, Japanese Patent Publication No. 27770821 “Method and mounting of semiconductor device”. The pad is electrically connected only by mechanical contact by the contraction force of a sealing resin filled between the LSI and the substrate.

【0003】この工法は、まず、基板上のLSI搭載部
に封止樹脂を供給する。この上にLSIを搭載し、加熱
・加圧し、封止樹脂を硬化させて電極同士の接続を得
る。圧接工法では、あらかじめ基板上に供給した封止樹
脂をLSIにより押し広げながら、LSIと基板との隙
間(ギャップ)に充填させる。このようにして、封止樹
脂を押し広げLSIのギャップに均等的に充填させてフ
ィレットを形成することが難しく、この形状に関しては
封止樹脂を供給する方法の影響を強く受ける。
In this method, first, a sealing resin is supplied to an LSI mounting portion on a substrate. The LSI is mounted thereon, heated and pressed, and the sealing resin is cured to obtain connection between the electrodes. In the pressure welding method, a sealing resin supplied on a substrate in advance is filled with a gap between the LSI and the substrate while being spread by the LSI. In this way, it is difficult to form the fillet by spreading the sealing resin evenly in the gap of the LSI, and the shape is greatly affected by the method of supplying the sealing resin.

【0004】供給方法には大きく分けてディスペンサー
を使用する方法と、印刷方法とがある。ディスペンサー
を使用する方法には、1点塗布、多点塗布、多点ノズル
塗布などがある。一点塗布は、通常、搭載部中央に必要
量を一回で塗布する方法であり、最も一般的に用いられ
ている。このような一点塗布は、複数のディスペンサー
を使用した方法と比較して安価であり、しかも塗布時間
の速い方法である。
[0004] The supply method is roughly divided into a method using a dispenser and a printing method. Methods using a dispenser include one-point application, multi-point application, multi-point nozzle application, and the like. The one-point application is a method in which a required amount is applied at once to the center of the mounting portion, and is most commonly used. Such one-point coating is a method which is inexpensive as compared with a method using a plurality of dispensers and has a short coating time.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、高粘度
の樹脂を封止樹脂として使用した場合や速硬化型樹脂
(従来の熱硬化型樹脂が200℃で1分以上かかるのに
対し、この硬化条件で半分程度の硬化時間またはそれ以
下で硬化する樹脂)を封止樹脂として用いると、基板上
に塗布した樹脂の形状が残存したまま押し広げられ、そ
の後に硬化温度まで温度を印加して封止樹脂を硬化する
と、塗布の際に生じた封止樹脂の形状が残存した状態で
硬化してしまう。通常の一点塗布では、供給された封止
樹脂は表面張力により基板上で半円球状になり、このよ
うな半円球状の封止樹脂を、一般的に四角形状のLSI
で押し広げると、封止樹脂が円形状に広がるため、LS
Iのコーナー部に封止樹脂が不足した形状のフィレット
となってしまう。
However, when a high-viscosity resin is used as a sealing resin or when a fast-curing resin (a conventional thermosetting resin takes more than one minute at 200 ° C., When the resin is cured in about half of the curing time or less), it is spread out while the shape of the resin applied on the substrate remains, and then sealed by applying the temperature to the curing temperature When the resin is cured, the resin is cured in a state where the shape of the sealing resin generated at the time of application remains. In the usual one-point coating, the supplied sealing resin becomes semi-spherical on the substrate due to surface tension, and such a semi-spherical sealing resin is generally replaced with a square LSI.
, The sealing resin spreads out in a circular shape.
A fillet having a shape in which the sealing resin is insufficient at the corner of I is obtained.

【0006】従来の基板上LSI搭載部のソルダーレジ
ストパターンは、図5〜図7に示す形状が代表的なもの
であった。このような従来のパターンでは、LSI搭載
時に基板上に供給された封止樹脂の流れに対しては何ら
抵抗を与えるものではなく、一点塗布の封止樹脂の供給
では、供給形状が半円球となるため、LSIを基板上に
載置させるために下降した際に、LSIに押されて円形
状に広がる。この結果、LSIのコーナー部には封止樹
脂が不足し、これを保持した状態で硬化してしまい、コ
ーナー部に封止樹脂が存在しない実装体となってしま
う。本発明に使用される封止樹脂は、硬化時に体積が収
縮するため、これによって、バンプ電極が実装用パッド
と密着して、回路基板とLSIとの完全な導通が図れる
ようになる。したがって、前記したようなコーナー部の
少なくとも1部に、封止樹脂が不足すると、回路基板と
LSIとの間で、導通が図れない部分が生じたり、生産
時には導通が図れても、その後、断線状態となる可能性
が高い。
The conventional solder resist pattern of the LSI mounting portion on the substrate has a typical shape shown in FIGS. In such a conventional pattern, no resistance is given to the flow of the sealing resin supplied on the substrate at the time of mounting the LSI. Therefore, when the LSI descends to be mounted on the substrate, it is pushed by the LSI and spreads in a circular shape. As a result, the sealing resin is insufficient at the corners of the LSI, and is cured while holding the sealing resin, resulting in a mounted body having no sealing resin at the corners. Since the volume of the sealing resin used in the present invention shrinks when it is cured, the bump electrodes come into close contact with the mounting pads, and complete electrical connection between the circuit board and the LSI can be achieved. Therefore, if the sealing resin is insufficient at at least one of the corners as described above, a portion where electrical connection cannot be established between the circuit board and the LSI, or even if electrical connection can be established during production, but thereafter, disconnection occurs. It is likely to be in a state.

【0007】このため、たとえば特開平11 −3075
84号公報「半導体装置の製造方法」に記載されている
ように、LSIを段階的に加熱し、比較的低温領域(1
00℃前後)でこの温度を一旦保持することにより、封
止樹脂の粘度を低下させてLSI下に封止樹脂を均等に
広がらせた後に、温度を上げ、封止樹脂を硬化させる方
法が知られている。この方法を用いることにより、LS
Iの各縁端部等に均等にフィレットを形成することが可
能となった。
For this reason, for example, Japanese Patent Application Laid-Open No. 11-3075
As described in Japanese Patent Publication No. 84, “Method of Manufacturing Semiconductor Device”, an LSI is heated in a stepwise manner so that a relatively low temperature region (1
(About 00 ° C.) by temporarily holding this temperature to lower the viscosity of the sealing resin to spread the sealing resin evenly under the LSI, and then raise the temperature to cure the sealing resin. Have been. By using this method, LS
A fillet can be formed evenly at each edge of I.

【0008】しかしながら、生産性を向上させるため
に、より短時間で硬化する樹脂が採用されると、樹脂が
LSI下で濡れ広がる段階を確保することが困難とな
り、その結果、フィレット形状に影響が現れ、特に一点
塗布法を用いた場合には、コーナー部に封止樹脂が充足
されなくなってしまう。すなわち、このような場合、封
止樹脂は、たとえば四角形のLSI下に円形状に広がる
ため、コーナー部に十分な封止樹脂の量を増量すること
しか対処法はなく、こうすることによって、各辺のフィ
レット量が非常に膨大となり、MCM(multi chip mod
ule )の場合等では、隣接するLSIと干渉する虞があ
る。
However, if a resin that cures in a shorter time is employed to improve the productivity, it is difficult to secure a stage where the resin spreads under the LSI, and as a result, the shape of the fillet is affected. In particular, when the one-point coating method is used, the corner portion is not filled with the sealing resin. That is, in such a case, since the sealing resin spreads in a circular shape under a square LSI, for example, the only solution is to increase the amount of the sealing resin sufficient at the corners. The amount of fillets on the sides becomes very large, and the MCM (multi chip mod
ule), there is a risk of interference with an adjacent LSI.

【0009】このような問題点を改善するために、一点
塗布ではなく、ディスペンサーを用いて塗布を繰り返す
多点塗布法により塗布した後に、LSIを基板上に載置
させて封止樹脂を押し広げる方法がある。この方法を採
用することにより、一点塗布において見られたコーナー
部の樹脂不足は解消され、フィレットの形状は改善され
る。しかしながら、本法を採用すると、ディスペンサー
による一点塗布を複数回繰り返すため、塗布時間が長く
なり、トータルとして生産性が低下してしまうという問
題点がある。
In order to solve such a problem, after applying by a multi-point coating method in which coating is repeated using a dispenser instead of one-point coating, the LSI is placed on a substrate and the sealing resin is spread. There is a way. By adopting this method, the shortage of resin at the corners observed in one-point coating is eliminated, and the shape of the fillet is improved. However, when this method is employed, since one-point application by a dispenser is repeated a plurality of times, there is a problem that the application time is lengthened and productivity is reduced as a whole.

【0010】また、ノズルを複数設けて塗布する多点ノ
ズル塗布法を用いれば、塗布すべきポイント位置にそれ
ぞれの吐出口を複数設けたノズルが用いられるので、基
板上への供給回数は一回で済み、半導体装置の生産性は
落ちることがない。しかしながら、多点ノズル塗布法に
使用される多点ノズルは、LSIの形状が変更する度に
新しい多点ノズルが別途必要となり、しかも多点ノズル
が高価であるため、生産コストに影響するという問題点
がある。
[0010] Further, if a multi-point nozzle coating method in which a plurality of nozzles are provided and applied is used, a nozzle provided with a plurality of discharge ports at a point position to be applied is used. And the productivity of the semiconductor device does not decrease. However, the multi-point nozzle used in the multi-point nozzle coating method requires a new multi-point nozzle separately every time the shape of the LSI is changed, and the multi-point nozzle is expensive, which affects the production cost. There is a point.

【0011】また、ディスペンサーを用いない第2番目
の塗布法として、必要量を印刷する印刷方法も知られて
いる。本方法では、LSIの形状に合わせて供給するこ
とが可能であり、ディスペンスによる一点塗布のような
円形に広がるようなことはない。しかしながら、この供
給工程はLSIの搭載工程前に行う必要があるため、ポ
ットライフの短い樹脂は使用できない。また、搭載工程
の際にLSI側からの熱が逃げないように基板側を加熱
していることも多く、この熱によって供給した樹脂の硬
化反応が進行してしまうという問題点がある。
As a second coating method without using a dispenser, a printing method for printing a required amount is also known. In the present method, it is possible to supply according to the shape of the LSI, and it does not spread in a circle as in single point application by dispensing. However, since this supply step needs to be performed before the LSI mounting step, a resin having a short pot life cannot be used. In addition, the substrate side is often heated so that heat from the LSI side does not escape during the mounting process, and there is a problem that the curing reaction of the supplied resin proceeds by this heat.

【0012】このように、樹脂の供給は、コスト、生産
性等を考慮すると、ディスペンサーを用いた一点塗布が
有利であるが、フィレット形成の点で問題がある。
As described above, in consideration of cost, productivity, etc., single-point application using a dispenser is advantageous for resin supply, but there is a problem in fillet formation.

【0013】本発明の目的は、上述したような従来技術
の問題点に鑑みてなされたものであって、封止樹脂不足
あるいは過多による、回路基板とLSIとの導通の不完
全さを是正し、製造後の半導体装置の性能安定化を図る
ことのできる、半導体装置の提供およびこのような半導
体装置の実装方法を提供することを目的としている。ま
た、本発明は、圧接工法を使用した半導体装置の実装方
法において、安価で、生産性の良い樹脂供給法であるデ
ィスペンスによる1点塗布を用いて接続信頼性の高い半
導体装置の実装方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned problems of the prior art, and corrects incomplete conduction between a circuit board and an LSI due to insufficient or excessive sealing resin. It is an object of the present invention to provide a semiconductor device capable of stabilizing the performance of a semiconductor device after manufacturing and to provide a mounting method of such a semiconductor device. The present invention also provides a semiconductor device mounting method using a pressure welding method, which is a low-cost, high-productivity resin supply method and uses a single-point application by dispensing to provide a semiconductor device mounting method with high connection reliability. Is to do.

【0014】[0014]

【課題を解決するための手段】請求項1に記載の半導体
装置の発明は、略並行に設けられた実装用パッド列の間
にソルダーレジストを複数設け、前記ソルダーレジスト
は、封止樹脂が複数の突起電極を有する半導体装置を載
置する際に、前記実装用パッド列のコーナー部まで略均
等に広がるように設けたことを特徴とする。
According to a first aspect of the present invention, there is provided a semiconductor device, wherein a plurality of solder resists are provided between substantially parallel mounting pad rows, and the solder resist has a plurality of sealing resins. When the semiconductor device having the protruding electrodes is mounted, the semiconductor device is provided so as to spread almost evenly to the corners of the mounting pad row.

【0015】請求項2に記載の半導体装置の発明は、略
並行に設けられた実装用パッド列の間にソルダーレジス
トを複数設け、前記複数のソルダーレジストを、前記実
装用パッド列のコーナー部まで前記硬化前の封止樹脂が
複数の突起電極を有する半導体装置の載置により、略均
等に流れ込むように分割して設けたことを特徴とする。
According to a second aspect of the present invention, a plurality of solder resists are provided between mounting pad rows provided substantially in parallel, and the plurality of solder resists are transferred to a corner portion of the mounting pad row. It is characterized in that the sealing resin before curing is divided so as to flow substantially evenly by mounting a semiconductor device having a plurality of projecting electrodes.

【0016】請求項3に記載の半導体装置の発明は、略
並行に設けられた実装用パッド列の間に、前記実装用パ
ッド列の端部から、該端部と錯角の位置関係にあるもう
1つの前記実装用パッド列の端部近傍までを、分割して
または溝部を形成してソルダーレジストを設けて、封止
樹脂が複数の突起電極を有する半導体装置の載置により
前記実装用パッド列のコーナー部まで略均等に流れ込む
ようにしたことを特徴とする。
According to a third aspect of the present invention, there is provided a semiconductor device according to the third aspect of the present invention, wherein between the mounting pad rows provided substantially in parallel, an end angle of the mounting pad row is in an angular relationship with the end. A solder resist is provided by dividing or forming a groove portion up to the vicinity of the end of one of the mounting pad rows, and the mounting pad row is formed by mounting a semiconductor device having a sealing resin having a plurality of projecting electrodes. Characterized in that it flows almost evenly to the corners of.

【0017】請求項4に記載の半導体装置の発明は、略
並行に設けられた実装用パッド列の間に、ソルダーレジ
ストを複数設け、前記ソルダーレジストを、実装用パッ
ド列のコーナー部まで前記硬化前の封止樹脂が流れ込む
ように、対角方向に分割したことを特徴とする。
According to a fourth aspect of the present invention, a plurality of solder resists are provided between substantially parallel mounting pad rows, and the solder resist is hardened to the corners of the mounting pad rows. It is characterized by being divided in a diagonal direction so that the previous sealing resin flows.

【0018】請求項5に記載の半導体装置の実装方法の
発明は、基板上の実装用パッドが形成された搭載部の中
心部近傍に一点塗布して封止樹脂を塗布した後に、複数
の突起電極を有する半導体装置を載置し、加熱加圧して
前記半導体装置を前記基板上に実装する半導体装置の実
装方法であって、前記複数の突起電極を有する半導体装
置を載置して、前記半導体装置の周縁部まで前記封止樹
脂が均等に流れ込むように略並行に設けた前記実装用パ
ッド列内に、隆起した複数のソルダーレジストを設けて
フィレットを形成することを特徴とする。
According to a fifth aspect of the present invention, there is provided a semiconductor device mounting method, wherein a plurality of protrusions are applied after a single point application is applied to the vicinity of the center of the mounting portion on which the mounting pads on the substrate are formed, and the sealing resin is applied. A method of mounting a semiconductor device having a plurality of protruding electrodes thereon, the method comprising: mounting a semiconductor device having electrodes thereon, and heating and pressing the semiconductor device to mount the semiconductor device on the substrate. A plurality of raised solder resists are provided in the mounting pad row provided substantially in parallel so that the sealing resin flows evenly to the peripheral portion of the device, thereby forming a fillet.

【0019】請求項6に記載の半導体装置の実装方法の
発明は、請求項5において、前記半導体装置が前記基板
上に実装されたときに前記半導体装置の各頂点近傍まで
封止樹脂が行きわたるように、前記基板上の前記実装用
パッド列の内側に棒状の前記ソルダーレジストを設けた
ことを特徴とする。
According to a sixth aspect of the present invention, in the method for mounting a semiconductor device according to the fifth aspect, when the semiconductor device is mounted on the substrate, the sealing resin spreads to the vicinity of each vertex of the semiconductor device. Thus, the rod-shaped solder resist is provided inside the mounting pad row on the substrate.

【0020】請求項7に記載の半導体装置の実装方法の
発明は、請求項5において、前記基板上の前記実装用パ
ッド列の内側に、ソルダーレジストを分割して設け、前
記半導体装置が前記基板上に載置されたときに前記半導
体装置の各頂点と、略並行に載置される前記基板側の前
記実装用パッド列の端部まで封止樹脂が行きわたるよう
に、略均等に封止樹脂が流れる前記ソルダーレジストを
設けることを特徴とする。
According to a seventh aspect of the present invention, in the semiconductor device mounting method according to the fifth aspect, a solder resist is divided and provided inside the mounting pad row on the substrate, and the semiconductor device is mounted on the substrate. Each of the vertices of the semiconductor device when mounted on the semiconductor device is sealed substantially evenly so that the sealing resin reaches the end of the mounting pad row on the substrate side which is mounted substantially in parallel. It is characterized in that the solder resist through which the resin flows is provided.

【0021】請求項8に記載の半導体装置の実装方法の
発明は、請求項5において、前記基板上の前記実装用パ
ッド列の内側に、分割してまたは溝部を形成してソルダ
ーレジストを設けて、前記LSIのコーナー部まで前記
硬化前の封止樹脂が前記LSIの載置により前記LSI
のコーナー部まで略均等に流れ込むようにしたことを特
徴とする。
According to an eighth aspect of the present invention, there is provided the semiconductor device mounting method according to the fifth aspect, wherein the solder resist is provided by dividing or forming a groove inside the mounting pad row on the substrate. The sealing resin before curing is moved to the corner of the LSI by placing the LSI.
Characterized in that it flows almost evenly to the corners of.

【0022】請求項9に記載の半導体装置の実装方法の
発明は、請求項5〜8のいずれか1項において、前記複
数のソルダーレジストの厚みを、10〜30μmの範囲
に設けることを特徴とする。
According to a ninth aspect of the present invention, there is provided a semiconductor device mounting method according to any one of the fifth to eighth aspects, wherein the thickness of the plurality of solder resists is provided in a range of 10 to 30 μm. I do.

【0023】請求項10に記載の半導体装置の実装方法
の発明は、請求項5から9のいずれか1項において、前
記封止樹脂は、硬化収縮率が硬化後の熱膨張率より大き
い熱硬化型速硬化性樹脂を使用することを特徴とする。
According to a tenth aspect of the present invention, there is provided a semiconductor device mounting method according to any one of the fifth to ninth aspects, wherein the sealing resin has a curing shrinkage rate larger than a thermal expansion coefficient after curing. It is characterized by using a mold quick-setting resin.

【0024】[0024]

【発明の実施の形態】本発明は、基板上に略並行に設け
られた複数の実装用パッド3、3、・・・による実装用
パッド列内に、ソルダーレジスト2が分割して設けられ
ていることを特徴とする。このような基板を用いて、突
起電極(バンプ電極)を有するLSIを、封止樹脂を熱
硬化させて固定して実装して半導体装置を製造する。こ
の封止樹脂を前記半導体装置が前記基板上に載置された
ときに、前記半導体装置の各頂点と、略並行に載置され
る前記基板側の前記実装用パッド列の端部まで、封止樹
脂が行きわたるように略均等に封止樹脂が流れる前記ソ
ルダーレジストを設けるように、ソルダーレジストを分
割して、または溝部を形成して設けることが好ましい。
DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a solder resist 2 is divided and provided in a mounting pad row composed of a plurality of mounting pads 3, 3,... Provided substantially in parallel on a substrate. It is characterized by being. Using such a substrate, an LSI having a bump electrode (bump electrode) is fixed by thermosetting a sealing resin and mounted to manufacture a semiconductor device. When the semiconductor device is mounted on the substrate, the sealing resin is sealed up to each vertex of the semiconductor device and to an end of the mounting pad row on the substrate side which is mounted substantially in parallel. It is preferable to divide the solder resist or to form a groove so as to provide the solder resist in which the sealing resin flows almost uniformly so that the sealing resin spreads.

【0025】以下、図面を参照しながら、本発明の半導
体装置および該装置の実装方法について、説明する。図
4は、本発明の一実施形態におけるフリップチップ実装
工程を回路基板上の実装用パッド部で切断した断面図で
ある。
Hereinafter, a semiconductor device of the present invention and a method of mounting the device will be described with reference to the drawings. FIG. 4 is a cross-sectional view of the flip-chip mounting process according to the embodiment of the present invention, which is cut by mounting pads on a circuit board.

【0026】(a)にバンプ電極5を形成したLSI4
を示す。ここで、バンプ電極5の材質は限定されない
が、LSI4を搭載する際に掛ける荷重により回路基板
1上の実装用パッド3上で変形する材質が好ましい。本
実施形態では材質としてAuを使用した。また本バンプ
電極5の形状はテール先端が尖状となるように形成する
ことが好ましい。
(A) LSI 4 having bump electrodes 5 formed thereon
Is shown. Here, the material of the bump electrode 5 is not limited, but a material that is deformed on the mounting pads 3 on the circuit board 1 by a load applied when mounting the LSI 4 is preferable. In this embodiment, Au is used as the material. Further, it is preferable that the shape of the bump electrode 5 is formed such that the tip of the tail is pointed.

【0027】(b)には未実装の回路基板1が示されて
いる。本発明にて使用する回路基板1の基材の種類は特
に限定されないが、本実施形態ではビルドアップ工法に
より製造されたプリント配線板を用いた。図1に、本発
明の一実施形態におけるソルダーレジストパターンを示
す。本ソルダーレジスト2の材料も限定されないが、本
実施形態では特に、感光性の液状レジストを使用した。
図1のようにLSI4搭載部領域には封止樹脂6の流れ
に対して抵抗となるようにソルダーレジスト2によるパ
ターンが形成されている。ソルダーレジスト2の厚みは
回路基板1の基材上及びパターン上で10〜30μmが
好ましく、本実施形態においては、基材上は30μm、
パターン上は20μmとした。
FIG. 2B shows an unmounted circuit board 1. Although the type of the base material of the circuit board 1 used in the present invention is not particularly limited, a printed wiring board manufactured by a build-up method is used in the present embodiment. FIG. 1 shows a solder resist pattern according to an embodiment of the present invention. Although the material of the solder resist 2 is not limited, a photosensitive liquid resist is used in the present embodiment.
As shown in FIG. 1, a pattern made of the solder resist 2 is formed in the LSI 4 mounting area so as to be resistant to the flow of the sealing resin 6. The thickness of the solder resist 2 is preferably 10 to 30 μm on the substrate and the pattern of the circuit board 1, and in the present embodiment, 30 μm on the substrate,
The pattern was 20 μm.

【0028】次に(c)に示されるように、回路基板1
上の搭載部中央に封止樹脂6を供給する。本発明にて使
用する供給方法は、公知のディスペンサーを用いた1点
塗布法である。また封止樹脂6としては、エポキシ系の
熱硬化型速硬化性樹脂で硬化収縮率の値が、硬化後の封
止樹脂の熱膨張率の値より、大きい樹脂を使用した。本
封止樹脂6は、200℃で30secほど(220℃で
1秒硬化:ツール温度260℃上で1秒硬化)で硬化が
完了するものである。本発明では、さらに、封止樹脂の
硬化条件が、200℃で、10秒程度、たとえば、1〜
10秒の範囲、特に5秒程度のエポキシ樹脂を封止樹脂
として用いることができる。一点塗布法により封止樹脂
6が回路基板1上に供給され、塗布された封止樹脂6は
樹脂の表面張力により半円球状態に近い形となってい
る。
Next, as shown in FIG.
The sealing resin 6 is supplied to the center of the upper mounting portion. The supply method used in the present invention is a one-point coating method using a known dispenser. As the sealing resin 6, an epoxy-based thermosetting fast-curing resin having a curing shrinkage value larger than the thermal expansion coefficient of the cured sealing resin was used. The encapsulating resin 6 completes curing at 200 ° C. for about 30 seconds (curing at 220 ° C. for 1 second: curing at a tool temperature of 260 ° C. for 1 second). In the present invention, further, the curing condition of the sealing resin is 200 ° C. for about 10 seconds, for example, 1 to 1.
An epoxy resin in a range of 10 seconds, particularly about 5 seconds can be used as the sealing resin. The sealing resin 6 is supplied onto the circuit board 1 by the one-point coating method, and the applied sealing resin 6 has a shape close to a semicircular sphere due to the surface tension of the resin.

【0029】続いて(d)に示されるように、所定の温
度に加熱されたLSI4のバンプ電極5と所定の温度に
加熱された回路基板1上の実装用パッド3との位置合わ
せを行う。LSI4と回路基板1を加熱する温度は、封
止樹脂を硬化する温度未満の温度でよく、このような温
度であれば特に限定されるものではないが、例えば硬化
温度より50℃以下の温度〜室温( 30℃) よりも上の
温度までであり、好ましくは硬化温度より80℃低い温
度〜55℃程度までである。本実施形態では共にこれを
80℃とした。
Subsequently, as shown in (d), the bump electrodes 5 of the LSI 4 heated to a predetermined temperature are aligned with the mounting pads 3 on the circuit board 1 heated to a predetermined temperature. The temperature at which the LSI 4 and the circuit board 1 are heated may be lower than the temperature at which the sealing resin is cured, and is not particularly limited as long as the temperature is such a temperature. The temperature is higher than room temperature (30 ° C.), preferably from a temperature lower by 80 ° C. than the curing temperature to about 55 ° C. In this embodiment, the temperature is set to 80 ° C.

【0030】最後に(e)に示すように、LSI4を回
路基板1上へ搭載し、LSI4を加圧・加熱する。ここ
で、加圧量は全バンプ電極5が実装用パッド3に接触し
所定量まで潰れる圧力とし、本実施形態ではバンプ電極
5の1個当たりの圧力を30gとした。この圧力により
バンプ高さが100μmから60μmまで潰される。ま
た加熱はLSI4側200℃、回路基板1側80℃で、
保持時間は30secとした。この時、封止樹脂6は回
路基板1上に形成されたソルダーレジスト2がコーナー
部が図1〜図3に示すように、のパターンにより封止樹
脂の流れ方に方向性が与えられ、LSI4のコーナー部
に導かれる。
Finally, as shown in (e), the LSI 4 is mounted on the circuit board 1, and the LSI 4 is pressurized and heated. Here, the amount of pressurization is a pressure at which all the bump electrodes 5 come into contact with the mounting pads 3 and are crushed to a predetermined amount. In the present embodiment, the pressure per bump electrode 5 is 30 g. This pressure crushes the bump height from 100 μm to 60 μm. Heating was performed at 200 ° C on the LSI 4 side and 80 ° C on the circuit board 1 side.
The holding time was 30 seconds. At this time, as shown in FIGS. 1 to 3, the direction of the flow of the sealing resin is given by the solder resist 2 formed on the circuit board 1 at the corners as shown in FIGS. To the corner.

【0031】以上の方法によれば、(f)に示すように
LSI4周辺には均等量のフィレットが形成され、信頼
性の高い実装構造を得ることができる。
According to the above method, as shown in FIG. 3 (f), a uniform amount of fillet is formed around the LSI 4, and a highly reliable mounting structure can be obtained.

【0032】上述した実施形態においては、ソルダーレ
ジスタの形状が図1に示すパターンであるときを例に挙
げて説明したが、ソルダーレジストの他の実施形態とし
て、図2、図3に示すようなパターンとすることもでき
る。図1〜図3に示すようなソルダーレジストパターン
とすることにより、LSI搭載時における樹脂の流れ方
にLSI4のコーナー部に導かれるような方向性を与え
ることができる。なお、図1(1)、図2(1)および
図3(1)において、封止樹脂の流れの方向性を矢印で
示した。
In the above-described embodiment, the case where the shape of the solder register has the pattern shown in FIG. 1 has been described as an example. However, as another embodiment of the solder resist, as shown in FIGS. It can also be a pattern. By using the solder resist pattern as shown in FIGS. 1 to 3, it is possible to give the direction of flow of the resin when mounting the LSI such that it is guided to the corners of the LSI 4. Note that in FIGS. 1 (1), 2 (1) and 3 (1), the directionality of the flow of the sealing resin is indicated by arrows.

【0033】ここで、本発明のソルダーレジストパター
ンは、実装用パッド3の外側に実装用パッド3を囲むよ
うにソルダーレジスト2が備えられるとともに、本発明
の特徴として、LSI実装時において封止樹脂の流れに
LSI4のコーナー部への方向性を与えるために、実装
用パッド3の内側に所定の配置及び形状でソルダーレジ
スト2が備えられる。
In the solder resist pattern of the present invention, the solder resist 2 is provided outside the mounting pad 3 so as to surround the mounting pad 3. The solder resist 2 is provided inside the mounting pad 3 in a predetermined arrangement and shape in order to give a flow toward the corner of the LSI 4 to the flow of the solder.

【0034】図1及び図2に示した実施形態において
は、回路基板1上の周縁部に形成されるソルダーレジス
ト2の内辺に並行に実装用パッド3が4方向に備えられ
ている。図1に示した実施形態では、これらの実装用パ
ッド3の内側に、実装用パッド3と並行となるように長
方形状のソルダーレジスト2がそれぞれの実装用パッド
3毎に設けられている。また、図2に示した実施形態に
おいては、実装用パッド3側を下底、回路基板1の中心
側を上底とし、上底より下底の方が長く上底及び下底が
実装用パッド3に平行な台形の形状をもつソルダーレジ
スト2が、それぞれの実装用パッド3毎に備えられてい
る。
In the embodiment shown in FIGS. 1 and 2, mounting pads 3 are provided in four directions in parallel with the inner side of the solder resist 2 formed on the peripheral portion of the circuit board 1. In the embodiment shown in FIG. 1, a rectangular solder resist 2 is provided inside each of the mounting pads 3 so as to be parallel to the mounting pads 3. In the embodiment shown in FIG. 2, the mounting pad 3 side is a lower bottom, the center side of the circuit board 1 is an upper bottom, and the lower bottom is longer than the upper bottom and the upper and lower bottoms are the mounting pads. A solder resist 2 having a trapezoidal shape parallel to 3 is provided for each mounting pad 3.

【0035】図3に示した実施形態においては、対向す
る2方向に実装用パッド2が備えられている。これらの
実装用パッド2の内側に、実装用パッド3側が下底、回
路基板1の中心側が上底とし、上底より下底の方が長く
上底及び下底が実装用パッド3に平行な台形の形状をも
つソルダーレジスト2が、それぞれの実装用パッド2毎
に備えられ、他の対向する2方向には、回路基板1の外
側が底辺、回路基板1の中心側が頂点となる三角形状の
ソルダーレジスト2が当該2方向毎に備えられている。
In the embodiment shown in FIG. 3, mounting pads 2 are provided in two opposing directions. Inside these mounting pads 2, the mounting pad 3 side is a lower bottom, the center side of the circuit board 1 is an upper bottom, and the lower bottom is longer than the upper bottom and the upper and lower bottoms are parallel to the mounting pad 3. A solder resist 2 having a trapezoidal shape is provided for each mounting pad 2, and a triangular shape in which the outside of the circuit board 1 is a bottom and the center side of the circuit board 1 is a vertex in two other opposing directions. A solder resist 2 is provided for each of the two directions.

【0036】上記の実施形態のようなソルダーレジスト
パターン厚では、当然樹脂は広がっている過程でこのパ
ターンを乗り越えることができるが、このパターンが存
在しない場所と比較すれば流れ易さに差が出てくる。こ
の流れ易さを利用してこの流れにLSI4のコーナー部
への方向性を与えてやれば、LSI実装時においてLS
I4辺中央部と同程度の樹脂量をLSI4コーナー部に
得ることができる。
With the solder resist pattern thickness as in the above-described embodiment, the resin can naturally get over this pattern in the process of spreading, but there is a difference in the ease of flow when compared with a place where this pattern does not exist. Come. If the direction of the corner of the LSI 4 is given to this flow by utilizing the ease of the flow, the LSI can be mounted at the time of mounting the LSI.
The same amount of resin as that at the center of the I4 side can be obtained at the corner of the LSI.

【0037】尚、上述した実施形態は本発明の好適な実
施の形態であるが、これに限定されるものでなく、本発
明の要旨である封止樹脂の流れ方に所定の方向性(半導
体装置が基板上に載置されたときに前記半導体装置の各
頂点と、略並行に載置される前記基板側の前記実装用パ
ッド列の端部まで封止樹脂が行きわたるように、略均等
に封止樹脂が流れるような方向性)を与えるような形状
のソルダーレジストをLSI搭載部に有しているもので
あれば、本発明の実施の形態となり得る。
Although the above-described embodiment is a preferred embodiment of the present invention, the present invention is not limited to this embodiment. When the device is mounted on the substrate, the sealing resin is substantially evenly distributed so as to reach each vertex of the semiconductor device and the end of the mounting pad row on the substrate side which is mounted substantially in parallel. The present invention can be implemented as long as the LSI mounting portion has a solder resist having such a shape as to give a sealing resin flowing direction.

【0038】[0038]

【発明の効果】以上の説明より明らかなように、本発明
によれば、圧接工法によるLSI実装において、特殊で
高価な樹脂供給方法を用いることなく、また実装プロセ
ス時間、樹脂供給量を増加させることなく一点塗布によ
り信頼性の高い接続を得ることができる。
As is apparent from the above description, according to the present invention, in the LSI mounting by the pressure welding method, the mounting process time and the resin supply amount can be increased without using a special and expensive resin supply method. A highly reliable connection can be obtained by one-point application without the need.

【0039】その理由は、本発明によりLSIと実装基
板との間に供給する樹脂の流れをコントロールすること
ができ、その結果1点塗布では困難であったチップ周辺
へのフィレット量の均一化が可能となるからである。
The reason is that the present invention makes it possible to control the flow of the resin supplied between the LSI and the mounting board, and as a result, it is possible to make the fillet amount around the chip uniform, which was difficult with one-point coating. It is possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態におけるソルダーレジ
ストパターンを示す図であり、(2)は、(1)のA−
A線での断面図である。
FIG. 1 is a view showing a solder resist pattern according to a first embodiment of the present invention, wherein FIG.
It is sectional drawing in the A line.

【図2】本発明の第2の実施形態におけるソルダーレジ
ストパターンを示す図であり、(2)は、(1)のB−
B線での断面図である。
FIG. 2 is a view showing a solder resist pattern according to a second embodiment of the present invention.
It is sectional drawing in the B line.

【図3】本発明の第3の実施形態におけるソルダーレジ
ストパターンを示す図であり、(2)は、(1)のC−
C線での断面図である。
FIG. 3 is a view showing a solder resist pattern according to a third embodiment of the present invention.
It is sectional drawing in the C line.

【図4】本発明の実施形態における半導体装置の実装工
程を説明するための図である。
FIG. 4 is a diagram illustrating a mounting process of the semiconductor device according to the embodiment of the present invention.

【図5】従来のソルダーレジストパターンの第1例を示
した図である。
FIG. 5 is a diagram showing a first example of a conventional solder resist pattern.

【図6】従来のソルダーレジストパターンの第2例を示
した図である。
FIG. 6 is a view showing a second example of a conventional solder resist pattern.

【図7】従来のソルダーレジストパターンの第3例を示
した図である。
FIG. 7 is a view showing a third example of a conventional solder resist pattern.

【符号の説明】[Explanation of symbols]

1 回路基板 2 ソルダーレジスト 3 実装用パッド 4 LSI 5 バンプ電極 6 封止樹脂 7 パルス加熱ツール DESCRIPTION OF SYMBOLS 1 Circuit board 2 Solder resist 3 Mounting pad 4 LSI 5 Bump electrode 6 Sealing resin 7 Pulse heating tool

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 略並行に設けられた実装用パッド列の間
にソルダーレジストを複数設け、前記ソルダーレジスト
は、封止樹脂が複数の突起電極を有する半導体装置を載
置する際に、前記実装用パッド列のコーナー部まで略均
等に広がるように設けたことを特徴とする半導体装置。
A plurality of solder resists are provided between mounting pad rows provided substantially in parallel, and the solder resist is used for mounting the semiconductor device when a semiconductor device having a plurality of projecting electrodes is mounted on a sealing resin. A semiconductor device provided so as to be substantially evenly spread to a corner portion of a pad row for use.
【請求項2】 略並行に設けられた実装用パッド列の間
にソルダーレジストを複数設け、前記複数のソルダーレ
ジストを、前記実装用パッド列のコーナー部まで前記硬
化前の封止樹脂が複数の突起電極を有する半導体装置の
載置により、略均等に流れ込むように分割して設けたこ
とを特徴とする半導体装置。
2. A plurality of solder resists are provided between mounting pad rows provided substantially in parallel, and the plurality of solder resists are divided into a plurality of sealing resin before curing to a corner portion of the mounting pad row. A semiconductor device, wherein a semiconductor device having a protruding electrode is mounted so as to be divided so as to flow substantially uniformly.
【請求項3】 略並行に設けられた実装用パッド列の間
に、前記実装用パッド列の端部から、該端部と錯角の位
置関係にあるもう1つの前記実装用パッド列の端部近傍
までを、分割してまたは溝部を形成してソルダーレジス
トを設けて、封止樹脂が複数の突起電極を有する半導体
装置の載置により前記実装用パッド列のコーナー部まで
略均等に流れ込むようにしたことを特徴とする半導体装
置。
3. An end portion of another mounting pad row which has a positional relationship between the mounting pad row provided substantially in parallel and an odd angle from the end of the mounting pad row. Up to the vicinity, divided or formed a groove portion to provide a solder resist, so that the sealing resin flows substantially evenly to the corner portion of the mounting pad row by mounting a semiconductor device having a plurality of projecting electrodes. A semiconductor device characterized by the following.
【請求項4】 略並行に設けられた実装用パッド列の間
に、ソルダーレジストを複数設け、前記ソルダーレジス
トを、実装用パッド列のコーナー部まで前記硬化前の封
止樹脂が流れ込むように、対角方向に分割したことを特
徴とする半導体装置。
4. A plurality of solder resists are provided between mounting pad rows provided substantially in parallel with each other, and the solder resist flows into the corners of the mounting pad rows so that the sealing resin before curing flows into the corners of the mounting pad rows. A semiconductor device which is divided in a diagonal direction.
【請求項5】 基板上の実装用パッドが形成された搭載
部の中心部近傍に一点塗布して封止樹脂を塗布した後
に、複数の突起電極を有する半導体装置を載置し、加熱
加圧して前記半導体装置を前記基板上に実装する半導体
装置の実装方法であって、 前記複数の突起電極を有する半導体装置を載置して、前
記半導体装置の周縁部まで前記封止樹脂が均等に流れ込
むように略並行に設けた前記実装用パッド列内に、隆起
した複数のソルダーレジストを設けてフィレットを形成
することを特徴とする半導体装置の実装方法。
5. A semiconductor device having a plurality of protruding electrodes is placed on the substrate at one point near the center of the mounting portion on which the mounting pads are formed, and a sealing resin is applied. A mounting method of mounting the semiconductor device on the substrate, wherein the semiconductor device having the plurality of protruding electrodes is placed, and the sealing resin flows uniformly to a peripheral portion of the semiconductor device. A method of mounting a semiconductor device, comprising: forming a fillet by providing a plurality of raised solder resists in the mounting pad row provided substantially in parallel as described above.
【請求項6】 前記半導体装置が前記基板上に実装され
たときに前記半導体装置の各頂点近傍まで封止樹脂が行
きわたるように、前記基板上の前記実装用パッド列の内
側に棒状の前記ソルダーレジストを設けたことを特徴と
する請求項5に記載の半導体装置の実装方法。
6. A rod-shaped inside of the mounting pad row on the substrate, such that when the semiconductor device is mounted on the substrate, the sealing resin spreads to the vicinity of each vertex of the semiconductor device. The method for mounting a semiconductor device according to claim 5, wherein a solder resist is provided.
【請求項7】 前記基板上の前記実装用パッド列の内側
に、ソルダーレジストを分割して設け、前記半導体装置
が前記基板上に載置されたときに前記半導体装置の各頂
点と、略並行に載置される前記基板側の前記実装用パッ
ド列の端部まで封止樹脂が行きわたるように、略均等に
封止樹脂が流れる前記ソルダーレジストを設けることを
特徴とする請求項5に記載の半導体装置の実装方法。
7. A solder resist is separately provided inside the mounting pad row on the substrate, and is substantially parallel to each vertex of the semiconductor device when the semiconductor device is mounted on the substrate. 6. The solder resist according to claim 5, wherein the sealing resin flows substantially evenly so that the sealing resin reaches the end of the mounting pad row on the substrate placed on the substrate. Semiconductor device mounting method.
【請求項8】 前記基板上の前記実装用パッド列の内側
に、分割してまたは溝部を形成してソルダーレジストを
設けて、前記LSIのコーナー部まで前記硬化前の封止
樹脂が前記LSIの載置により前記LSIのコーナー部
まで略均等に流れ込むようにしたことを特徴とする請求
項5に記載の半導体装置の実装方法。
8. A solder resist is provided by dividing or forming a groove on the inside of the mounting pad row on the substrate, and the sealing resin before hardening is applied to the LSI until a corner of the LSI is formed. 6. The method for mounting a semiconductor device according to claim 5, wherein the mounting causes the semiconductor device to flow substantially evenly to a corner portion of the LSI.
【請求項9】 前記複数のソルダーレジストの厚みを、
10〜30μmの範囲に設けることを特徴とする請求項
からのいずれかに記載の半導体装置の実装方法。
9. The thickness of the plurality of solder resists,
The method for mounting a semiconductor device according to claim 1, wherein the semiconductor device is provided in a range of 10 to 30 μm.
【請求項10】 前記封止樹脂は、硬化収縮率が硬化後
の熱膨張率より大きい熱硬化型速硬化性樹脂を使用する
ことを特徴とする請求項5から9のいずれか1項に記載
の半導体装置の実装方法。
10. The thermosetting resin according to claim 5, wherein the sealing resin is a thermosetting fast-curing resin having a curing shrinkage greater than a thermal expansion coefficient after curing. Semiconductor device mounting method.
JP2000384424A 1999-12-17 2000-12-18 Semiconductor device and method of mounting the device Pending JP2001237257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000384424A JP2001237257A (en) 1999-12-17 2000-12-18 Semiconductor device and method of mounting the device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP35916599 1999-12-17
JP11-359165 1999-12-17
JP2000384424A JP2001237257A (en) 1999-12-17 2000-12-18 Semiconductor device and method of mounting the device

Publications (1)

Publication Number Publication Date
JP2001237257A true JP2001237257A (en) 2001-08-31

Family

ID=26580906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000384424A Pending JP2001237257A (en) 1999-12-17 2000-12-18 Semiconductor device and method of mounting the device

Country Status (1)

Country Link
JP (1) JP2001237257A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101945531A (en) * 2009-07-07 2011-01-12 阿尔卑斯电气株式会社 Electronic circuit cell and manufacture method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101945531A (en) * 2009-07-07 2011-01-12 阿尔卑斯电气株式会社 Electronic circuit cell and manufacture method thereof

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