JP2001237159A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JP2001237159A
JP2001237159A JP2000043342A JP2000043342A JP2001237159A JP 2001237159 A JP2001237159 A JP 2001237159A JP 2000043342 A JP2000043342 A JP 2000043342A JP 2000043342 A JP2000043342 A JP 2000043342A JP 2001237159 A JP2001237159 A JP 2001237159A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
wiring metal
wafer
semiconductor device
lithography
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000043342A
Other languages
Japanese (ja)
Inventor
Yosuke Ooka
洋介 大岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2000043342A priority Critical patent/JP2001237159A/en
Publication of JP2001237159A publication Critical patent/JP2001237159A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device of high reliability, where a wafer can be subjected to a lithography process, being kept in a good state even after the wafer on which a wiring metal layer of laminated structure is formed is stored for a long term. SOLUTION: In a step 11, transistor elements are formed on a semiconductor wafer, and a laminated wiring metal film composed of a prescribed wiring metal layer and an antireflection film or a barrier layer is formed on all the surface of a wafer. Being kept in this state, the semiconductor wafer is stored in a storehouse for a long term (step 12). The semiconductor wafer is taken out of the storehouse after an optional storage time, if necessary (step 13). Thereafter, as shown in a step 14, the semiconductor wafer delivered from a storehouse undergoes a rinsing process before the semiconductor wafer delivered from a storehouse is subjected to a lithography process. Thereafter, the semiconductor wafer is subjected to a lithography process in a step 15 for the formation of a required wiring pattern on the wafer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置製造に
係り、特に積層配線構造が全面に密着形成された中途の
半導体ウェハを長期間保管する場合の信頼性維持管理に
適用される半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a semiconductor device which is applied to maintenance and management of reliability in the case where an intermediate semiconductor wafer having a laminated wiring structure formed in close contact with the entire surface is stored for a long period of time. It relates to a manufacturing method.

【0002】[0002]

【従来の技術】LSI製造工程(ウェハ工程)の中で
は、トランジスタ素子形成の後、配線金属層を全面に堆
積しておく中途の状態を維持しなければならない場合が
ある。このようなウェハは、例えば、顧客の要望に応じ
たマスク(ROMマスク)によってリソグラフィ工程が
施され、所望のROM(読み出し専用記憶装置)が実現
される。
2. Description of the Related Art In an LSI manufacturing process (wafer process), it is sometimes necessary to maintain an intermediate state in which a wiring metal layer is deposited on the entire surface after a transistor element is formed. Such a wafer is subjected to a lithography process using a mask (ROM mask) according to a customer's request, for example, and a desired ROM (read-only storage device) is realized.

【0003】配線金属層は、主にAlを主成分としたア
ルミ配線層が一般的である。アルミ配線層がトランジス
タ素子を形成するSiと接続される部分では、下地にバ
リア層が必要である。このバリア層によりAlのスパイ
ク現象やSiの析出防止ができる。また、配線金属層の
最上面は反射防止膜を形成する必要がある。この反射防
止膜によりリソグラフィ工程におけるハレーションの防
止ができる。
A wiring metal layer is generally an aluminum wiring layer mainly containing Al as a main component. At the portion where the aluminum wiring layer is connected to Si forming the transistor element, a barrier layer is required as a base. With this barrier layer, the spike phenomenon of Al and the precipitation of Si can be prevented. Further, it is necessary to form an antireflection film on the uppermost surface of the wiring metal layer. This antireflection film can prevent halation in the lithography process.

【0004】前者のバリア層は、例えばTiN/Ti積
層であり、後者の反射防止膜は、例えばTiN層であ
る。このような積層構造の配線金属層をウェハ全面に形
成しておき、長期間保管することになると、TiN層の
応力の集積が進む。
[0004] The former barrier layer is, for example, a TiN / Ti laminate, and the latter antireflection film is, for example, a TiN layer. If the wiring metal layer having such a laminated structure is formed on the entire surface of the wafer and stored for a long period of time, the accumulation of the stress of the TiN layer proceeds.

【0005】[0005]

【発明が解決しようとする課題】上記配線金属層が全面
に形成されたウェハに対し、リソグラフィ工程に入ると
きには、リソグラフィ工程に入る前段階でスクラバー処
理が行われる。ここでのスクラバー処理は、超音波水流
をウェハ全面に噴き付けるものである。これにより、リ
ソグラフィ工程前においてレジストの密着性向上及びパ
ーティクル除去の目的が達成される。
When a lithography process is performed on a wafer on which the wiring metal layer is formed on the entire surface, a scrubber process is performed before the lithography process. The scrubber treatment here is to spray an ultrasonic water flow over the entire surface of the wafer. This achieves the purpose of improving the adhesion of the resist and removing particles before the lithography step.

【0006】上記スクラバー処理は、ウェハ面にとって
少なからぬ衝撃を伴う工程である。従来では、積層構造
の配線金属層をウェハ全面に形成しておき、長期間保管
した後でも、リソグラフィ工程に入る段階になってから
スクラバー処理が行われていた。
[0006] The scrubber process is a process that involves considerable impact on the wafer surface. Conventionally, even after a wiring metal layer having a laminated structure is formed on the entire surface of a wafer and stored for a long period of time, a scrubber process has been performed after entering a lithography process.

【0007】長期間保管によるTiN層の応力の蓄積
と、スクラバー処理の衝撃が重なればウェハのダメージ
はかなり大きいものとなる。最悪、コンタクトホールや
ビアホール上のTiN層やAl層の一部が吹き飛ばされ
る事態になる。この結果、不良にならないまでも、パー
ティクルが発生するなど、歩留りが低下する問題があっ
た。
[0007] If the accumulation of stress in the TiN layer due to long-term storage and the impact of the scrubber treatment are superimposed, the damage to the wafer becomes considerably large. In the worst case, a part of the TiN layer or the Al layer on the contact hole or the via hole is blown off. As a result, there is a problem in that the yield is reduced, for example, particles are generated even if no defect occurs.

【0008】本発明は上記のような事情を考慮してなさ
れ、積層構造の配線金属層をウェハ全面に形成してお
き、長期間保管した後でも、良好な状態を維持しつつリ
ソグラフィ工程に移行できる高信頼性の半導体装置の製
造方法を提供しようとするものである。
The present invention has been made in view of the above circumstances, and a wiring metal layer having a laminated structure is formed on the entire surface of a wafer, and the lithography process is performed while maintaining a good state even after long-term storage. It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device.

【0009】[0009]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、所定の配線金属層及び反射防止膜またはバリ
ア層からなる積層配線金属膜が全面に形成された状態の
半導体ウェハを、任意の保管期間を経た後リソグラフィ
工程に移行する方法であって、前記リソグラフィ工程に
移行する前において保管期間を経た前記半導体ウェハに
対し水洗工程を経ることを特徴とする。
According to the method of manufacturing a semiconductor device of the present invention, a semiconductor wafer having a laminated wiring metal film formed of a predetermined wiring metal layer and an antireflection film or a barrier layer formed on an entire surface is optionally used. A lithography step after a storage period, wherein the semiconductor wafer after the storage period is subjected to a water washing step before the lithography step.

【0010】また、本発明の半導体装置の製造方法は、
所定の配線金属層及び反射防止膜またはバリア層からな
る積層配線金属膜が全面に形成された状態の半導体ウェ
ハを、任意の保管期間を経た後リソグラフィ工程に移行
する方法であって、前記積層配線金属膜形成後に前記半
導体ウェハに対しスクラバー処理工程を経て保管期間に
入ることを特徴とする。
Further, the method of manufacturing a semiconductor device according to the present invention comprises:
A method in which a semiconductor wafer having a laminated wiring metal film including a predetermined wiring metal layer and an anti-reflection film or a barrier layer formed on the entire surface is transferred to a lithography step after an arbitrary storage period, wherein the laminated wiring After forming the metal film, the semiconductor wafer goes through a scrubber process and enters a storage period.

【0011】また、本発明の半導体装置の製造方法は、
所定の配線金属層及び反射防止膜またはバリア層からな
る積層配線金属膜が全面に形成された状態の半導体ウェ
ハを、任意の保管期間を経た後リソグラフィ工程に移行
する方法であって、前記保管期間の前で前記積層配線金
属膜を形成した後に前記半導体ウェハに対しスクラバー
処理をする工程と、前記保管期間の後でリソグラフィ工
程に移行する前において前記半導体ウェハに対し水洗処
理を経る工程とを具備したことを特徴とする。
Further, a method of manufacturing a semiconductor device according to the present invention
A method in which a semiconductor wafer having a laminated wiring metal film formed of a predetermined wiring metal layer and an anti-reflection film or a barrier layer formed on the entire surface is transferred to a lithography step after an arbitrary storage period, wherein the storage period A step of performing a scrubber process on the semiconductor wafer after forming the laminated wiring metal film before the step, and a step of performing a water washing process on the semiconductor wafer after the storage period and before shifting to a lithography process. It is characterized by having done.

【0012】本発明の半導体装置の製造方法それぞれに
よれば、ウェハ面にとって大きな衝撃を伴うスクラバー
処理は、少なくとも積層配線金属層をウェハ全面に形成
しておき長期間保管した後においては導入しない。
According to each of the semiconductor device manufacturing methods of the present invention, the scrubber treatment involving a large impact on the wafer surface is not introduced after at least the laminated wiring metal layer is formed on the entire surface of the wafer and stored for a long time.

【0013】[0013]

【発明の実施の形態】図1は、本発明の第1実施例に係
る半導体装置の製造方法のウェハに対する要部の工程を
示す流れ図である。ステップ11で半導体ウェハへのト
ランジスタ素子形成後、所定の配線金属層及び反射防止
膜またはバリア層からなる積層配線金属膜をウェハ全面
に形成する。この状態で保管庫にて長期保管する(ステ
ップ12)。任意の保管期間後、上記半導体ウェハを必
要に応じて出庫する(ステップ13)。その後、ステッ
プ14に示すように、リソグラフィ工程に移行する前に
おいて出庫した半導体ウェハに対し水洗工程を経る。そ
の後、ステップ15においてリソグラフィ工程が行わ
れ、所望の配線パターンが形成される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flow chart showing main steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. After forming the transistor elements on the semiconductor wafer in step 11, a laminated wiring metal film including a predetermined wiring metal layer and an antireflection film or a barrier layer is formed on the entire surface of the wafer. In this state, it is stored for a long time in the storage (step 12). After an arbitrary storage period, the semiconductor wafer is unloaded as needed (step 13). Thereafter, as shown in step 14, the semiconductor wafers that have been unloaded before going to the lithography process undergo a water washing process. Thereafter, in step 15, a lithography process is performed to form a desired wiring pattern.

【0014】図2は、図1に関するリソグラフィ工程前
における半導体ウェハの一部の断面図である。半導体ウ
ェハ101上にトランジスタ素子102及び層間絶縁膜
103が形成されている。層間絶縁膜103には所定の
コンタクトホール104が形成されている。コンタクト
ホール104を含んで例えばTiN/Ti積層からなる
バリアメタル105が形成され、その上にアルミ配線層
106が形成されている。アルミ配線層106上にはT
iN層でなる反射防止膜107が全面に形成されてい
る。
FIG. 2 is a cross-sectional view of a portion of the semiconductor wafer before the lithography step in FIG. On a semiconductor wafer 101, a transistor element 102 and an interlayer insulating film 103 are formed. A predetermined contact hole 104 is formed in the interlayer insulating film 103. A barrier metal 105 made of, for example, a TiN / Ti laminate is formed including the contact hole 104, and an aluminum wiring layer 106 is formed thereon. T on the aluminum wiring layer 106
An anti-reflection film 107 made of an iN layer is formed on the entire surface.

【0015】ステップ14による水洗工程は、物理的な
作用の大きいスクラバー洗浄と異なり、例えばDip式
の純水によるリンスで処理される。従って、図2に示す
ように、コンタクト部分でも反射防止膜107のTiN
層やアルミ配線の一部が吹き飛ばされることはない。
The washing step in step 14 is different from the scrubber washing which exerts a large physical effect, and is treated by, for example, a Dip-type rinse with pure water. Therefore, as shown in FIG.
No part of the layer or aluminum wiring is blown away.

【0016】上記実施例方法によれば、TiN層の応力
の懸念があるウェハの長期間保管後に、ウェハ面にとっ
て大きな衝撃を伴うスクラバー処理は行わない。これに
より、長期間保管した後でも、良好な状態を維持しつつ
リソグラフィ工程に移行できる。しかも、リソグラフィ
工程前においてレジストの密着性向上及びパーティクル
除去の目的が達成される。
According to the method of the above embodiment, a scrubber treatment involving a large impact on the wafer surface is not performed after a long-term storage of a wafer having a stress of the TiN layer. Thereby, even after long-term storage, it is possible to shift to the lithography process while maintaining a good state. In addition, the purpose of improving the adhesion of the resist and removing the particles before the lithography step is achieved.

【0017】図3は、本発明の第2実施例に係る半導体
装置の製造方法のウェハに対する要部の工程を示す流れ
図である。ステップ21で半導体ウェハへのトランジス
タ素子形成後、所定の配線金属層及び反射防止膜または
バリア層からなる積層配線金属膜をウェハ全面に形成す
る。積層配線金属膜形成後すぐにスクラバー処理を行う
(ステップ22)。スクラバー処理はここでは超音波水
流による噴き付け洗浄である。これにより、パーティク
ル除去を達成した状態で保管庫にて長期保管する(ステ
ップ23)。そして、任意の保管期間後、上記半導体ウ
ェハを必要に応じて出庫する(ステップ24)。その
後、ステップ25においてリソグラフィ工程が行われ、
所望の配線パターンが形成される。
FIG. 3 is a flow chart showing main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. After transistor elements are formed on the semiconductor wafer in step 21, a laminated wiring metal film including a predetermined wiring metal layer and an antireflection film or a barrier layer is formed on the entire surface of the wafer. Immediately after the formation of the laminated wiring metal film, a scrubber treatment is performed (step 22). The scrubber treatment here is spray cleaning by an ultrasonic water flow. As a result, the particles are stored for a long time in the storage with the particles removed (step 23). Then, after an arbitrary storage period, the semiconductor wafer is unloaded as needed (step 24). Thereafter, a lithography process is performed in step 25,
A desired wiring pattern is formed.

【0018】上記実施例方法によれば、積層配線金属膜
(TiN層を含む積層)の応力の懸念があるウェハの長
期間保管前に、なるべく、積層配線金属膜形成後すぐに
スクラバー洗浄にてパーティクルを除去する。これによ
り、前記図2に示す構成と同様に、長期間保管した後で
も、良好な状態を維持しつつリソグラフィ工程に移行で
きる。しかも、リソグラフィ工程前においてレジストの
密着性向上及びパーティクル除去の目的が達成されてい
る。
According to the method of the above-mentioned embodiment, it is preferable to carry out scrubber cleaning as soon as possible after the formation of the laminated wiring metal film, preferably before storing the wafer for a long period of time, where there is concern about the stress of the laminated wiring metal film (lamination including the TiN layer). Remove particles. Thus, similarly to the configuration shown in FIG. 2, even after being stored for a long time, it is possible to shift to the lithography process while maintaining a good state. In addition, the purpose of improving the adhesion of the resist and removing the particles before the lithography step is achieved.

【0019】図4は、本発明の第3実施例に係る半導体
装置の製造方法のウェハに対する要部の工程を示す流れ
図である。ステップ31で半導体ウェハへのトランジス
タ素子形成後、所定の配線金属層及び反射防止膜または
バリア層からなる積層配線金属膜をウェハ全面に形成す
る。積層配線金属膜形成後すぐにスクラバー処理を行う
(ステップ32)。スクラバー処理は、ここでは超音波
水流による噴き付け洗浄である。これにより、パーティ
クル除去を達成した状態で保管庫にて長期保管する(ス
テップ33)。そして、任意の保管期間後、上記半導体
ウェハを必要に応じて出庫する(ステップ34)。その
後、ステップ35に示すように、リソグラフィ工程に移
行する前において出庫した半導体ウェハに対し再度洗浄
するため、水洗工程を経る。ステップ36においてリソ
グラフィ工程が行われ、所望の配線パターンが形成され
る。
FIG. 4 is a flow chart showing steps of a main part of a wafer in a method of manufacturing a semiconductor device according to a third embodiment of the present invention. After forming the transistor elements on the semiconductor wafer in step 31, a laminated wiring metal film including a predetermined wiring metal layer and an antireflection film or a barrier layer is formed on the entire surface of the wafer. Immediately after the formation of the laminated wiring metal film, a scrubber process is performed (step 32). The scrubber treatment here is spray cleaning by an ultrasonic water flow. As a result, the particles are stored in the storage for a long time in a state where the particles have been removed (step 33). Then, after an arbitrary storage period, the semiconductor wafer is unloaded as needed (step 34). Thereafter, as shown in step 35, a water washing step is performed in order to wash the unloaded semiconductor wafer again before shifting to the lithography step. In step 36, a lithography process is performed to form a desired wiring pattern.

【0020】上記実施例方法によれば、積層配線金属膜
(TiN層を含む積層)の応力の懸念があるウェハの長
期間保管前に、なるべく、積層配線金属膜形成後すぐに
スクラバー洗浄にてパーティクルを除去し、出庫後もリ
ソグラフィ工程前に水洗で再洗浄する。これにより、前
記図2に示す構成と同様に、長期間保管した後でも、良
好な状態を維持しつつリソグラフィ工程に移行できる。
しかも、リソグラフィ工程前においてレジストの密着性
向上及びパーティクル除去の目的が達成される。
According to the method of the above embodiment, before the wafer is stored for a long period of time, where there is a concern about the stress of the laminated wiring metal film (lamination including the TiN layer), it is preferable to carry out scrubber cleaning as soon as possible after forming the laminated wiring metal film. The particles are removed, and the wafer is washed again with water before the lithography process even after the delivery. Thus, similarly to the configuration shown in FIG. 2, even after being stored for a long time, it is possible to shift to the lithography process while maintaining a good state.
In addition, the purpose of improving the adhesion of the resist and removing the particles before the lithography step is achieved.

【0021】[0021]

【発明の効果】以上説明したように本発明によれば、各
々の半導体装置の製造方法で、ウェハ面にとって大きな
衝撃を伴うスクラバー処理は、少なくとも異種の金属層
を密着形成する積層配線金属層をウェハ全面に形成して
おき長期間保管した後においては導入されず、リソグラ
フィ工程前においてレジストの密着性向上及びパーティ
クル除去の目的が達成される。この結果、異種の金属層
を密着形成する積層配線金属層をウェハ全面に形成して
おき、長期間保管した後でも、良好な状態を維持しつつ
リソグラフィ工程に移行できる高信頼性の半導体装置の
製造方法が提供できる。
As described above, according to the present invention, in each method of manufacturing a semiconductor device, the scrubber treatment involving a large impact on the wafer surface is performed by forming a laminated wiring metal layer for forming at least different kinds of metal layers in close contact. It is not introduced after being formed on the entire surface of the wafer and stored for a long period of time, and the purpose of improving the adhesion of the resist and removing particles before the lithography process is achieved. As a result, a highly reliable semiconductor device capable of shifting to the lithography process while maintaining a good state even after being stored for a long period of time after forming a laminated wiring metal layer for closely forming a heterogeneous metal layer. A manufacturing method can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例に係る半導体装置の製造方
法のウェハに対する要部の工程を示す流れ図である。
FIG. 1 is a flowchart showing main steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

【図2】図1に関するリソグラフィ工程前における半導
体ウェハの一部の断面図である。
FIG. 2 is a cross-sectional view of a part of the semiconductor wafer before a lithography step related to FIG. 1;

【図3】本発明の第2実施例に係る半導体装置の製造方
法のウェハに対する要部の工程を示す流れ図である。
FIG. 3 is a flowchart showing main steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

【図4】本発明の第3実施例に係る半導体装置の製造方
法のウェハに対する要部の工程を示す流れ図である。
FIG. 4 is a flowchart showing main steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention;

【符号の説明】 11〜15,21〜25,31〜36…処理ステップ 101…半導体ウェハ 102…トランジスタ素子 103…層間絶縁膜 104…コンタクトホール 105…バリアメタル 106…アルミ配線層 107…反射防止膜[Description of Symbols] 11 to 15, 21 to 25, 31 to 36 Processing step 101 Semiconductor wafer 102 Transistor element 103 Interlayer insulating film 104 Contact hole 105 Barrier metal 106 Aluminum wiring layer 107 Antireflection film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 所定の配線金属層及び反射防止膜または
バリア層からなる積層配線金属膜が全面に形成された状
態の半導体ウェハを、任意の保管期間を経た後リソグラ
フィ工程に移行する方法であって、 前記リソグラフィ工程に移行する前において保管期間を
経た前記半導体ウェハに対し水洗工程を経ることを特徴
とした半導体装置の製造方法。
1. A method of transferring a semiconductor wafer having a laminated wiring metal film including a predetermined wiring metal layer and an antireflection film or a barrier layer formed on the entire surface to a lithography step after an arbitrary storage period. And subjecting the semiconductor wafer, which has been stored for a period of time before shifting to the lithography step, to a rinsing step.
【請求項2】 所定の配線金属層及び反射防止膜または
バリア層からなる積層配線金属膜が全面に形成された状
態の半導体ウェハを、任意の保管期間を経た後リソグラ
フィ工程に移行する方法であって、 前記積層配線金属膜形成後に前記半導体ウェハに対しス
クラバー処理工程を経て保管期間に入ることを特徴とし
た半導体装置の製造方法。
2. A method for transferring a semiconductor wafer having a laminated wiring metal film including a predetermined wiring metal layer and an antireflection film or a barrier layer formed on the entire surface thereof to a lithography step after an arbitrary storage period. A method of manufacturing a semiconductor device, comprising: entering a storage period through a scrubber process step on the semiconductor wafer after the formation of the laminated wiring metal film.
【請求項3】 所定の配線金属層及び反射防止膜または
バリア層からなる積層配線金属膜が全面に形成された状
態の半導体ウェハを、任意の保管期間を経た後リソグラ
フィ工程に移行する方法であって、 前記保管期間の前で前記積層配線金属膜を形成した後に
前記半導体ウェハに対しスクラバー処理をする工程と、 前記保管期間の後でリソグラフィ工程に移行する前にお
いて前記半導体ウェハに対し水洗処理を経る工程と、を
具備したことを特徴とする半導体装置の製造方法。
3. A method of transferring a semiconductor wafer, in which a laminated wiring metal film including a predetermined wiring metal layer and an antireflection film or a barrier layer is formed on the entire surface, to a lithography step after an arbitrary storage period. Performing a scrubber process on the semiconductor wafer after forming the laminated wiring metal film before the storage period, and performing a water washing process on the semiconductor wafer before shifting to a lithography process after the storage period. A method of manufacturing a semiconductor device, comprising:
JP2000043342A 2000-02-21 2000-02-21 Method of manufacturing semiconductor device Withdrawn JP2001237159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000043342A JP2001237159A (en) 2000-02-21 2000-02-21 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000043342A JP2001237159A (en) 2000-02-21 2000-02-21 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2001237159A true JP2001237159A (en) 2001-08-31

Family

ID=18566270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000043342A Withdrawn JP2001237159A (en) 2000-02-21 2000-02-21 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2001237159A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015109474A (en) * 2010-11-25 2015-06-11 三菱電機株式会社 Silicon carbide semiconductor device
US9842906B2 (en) 2010-11-25 2017-12-12 Mitsubishi Electric Corporation Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015109474A (en) * 2010-11-25 2015-06-11 三菱電機株式会社 Silicon carbide semiconductor device
US9842906B2 (en) 2010-11-25 2017-12-12 Mitsubishi Electric Corporation Semiconductor device

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