JP2001236222A - Processor equipped with out-of-order executing function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the assignment of high speed rename registers in constitution in almost the same level as that of the constitution in which only one rename register is assigned even when an instruction to request the assignment of plural rename registers is present in an instruction set. SOLUTION: This processor is provided with rename register assigning mechanisms 103 and 104 for dividing a rename register 109 into plural groups, and for assigning rename registers from each group. At the time of allocating the rename registers to an instruction to store plural executed results in the same architecture register, the rename registers are allocated from the different groups to each result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor having an out-of-order execution function using a rename register, and more particularly to a mechanism for allocating the rename register.

[0002]

2. Description of the Related Art In recent years, as a technology for increasing the speed of a processor,
In addition to superscalar technology that executes multiple instructions simultaneously,
Out-of-order execution techniques for rearranging and executing instructions in order of execution have achieved high effects.

In out-of-order execution, a register renaming technique is generally used to increase the execution efficiency. This means that the register (destination register) specified by the instruction is reallocated at the time of execution,
A technology that eliminates inter-instruction dependencies and increases efficiency. The generated result is written out to the rename register indicated by the assigned rename register number in non-instruction order before being written to an architectural register such as a general-purpose register. It is later written back to the architectural register where it should be written so as to guarantee the instruction order.

[0004] Rename register allocation is typically performed when dispatching instructions. The number of rename registers that can be assigned a rename register number even if the processor does not need to write the result to the corresponding rename register, for all the instructions that are being executed by the processor at a certain point in time (the result is not written to the architectural register). If so, the rename register number assignment mechanism is simple. That is, the rename register numbers may be sequentially assigned to the instructions to be dispatched in a cyclic manner. However, it is difficult to prepare enough rename registers for all architecture registers. Therefore, when an instruction does not need to allocate a corresponding rename register, it is necessary to provide a function that does not allocate a rename register number.

FIG. 4 shows an example of a rename register allocating mechanism having the above-mentioned function for realizing four-instruction dispatch at the same time. It indicates the rename register number at which the allocation pointer (RAP) 410 starts the allocation.
Rename register numbers that can be assigned by the adders 411 to 413 are generated in order, and the selectors 414 to 41 are assigned in response to the input assignment request signals of the respective instructions.
9, a rename register number assigned to each instruction is selected. The selectors 414 to 419 are
When the allocation request is 0 (no allocation required), the upper side (a) is selected, and when the allocation request is 1 (allocation required), the lower side (b) is selected.
Select For example, when all four instructions require the assignment of a rename register, the selectors 414 to 419 all select the b side, so that the value of the RAP 410 is assigned as it is to the rename register number of the first instruction. The values of 411 to 413 are sequentially assigned to the rename register numbers of the second to fourth instructions. Also, for example,
When the first instruction does not require the assignment of the rename register and the second instruction does, the selector 414 selects the a side, and the value of the RAP 410 is assigned to the rename register of the second instruction. After assignment, RAP 410 is updated to indicate the next assignment start number.

By the way, in order for out-of-order execution to function sufficiently, it is necessary to dispatch as many instructions as possible to the execution unit at the same time. However, as the number of instructions to be dispatched simultaneously increases, the selection range of the rename register number becomes wider. Therefore, the rename register allocation mechanism becomes complicated.

In the case where an instruction included in the processor generates a plurality of results to be written to the same architectural register, that is, an instruction requesting the assignment of a plurality of the same rename registers to store the result,
The ratio of the selection range of the rename register to the increase in the number of instructions dispatched simultaneously increases,
It becomes difficult for the rename register allocation mechanism to operate at high speed as a logic circuit.

FIG. 5 shows an example of a rename register allocating mechanism for realizing simultaneous dispatch of four instructions in a processor having an instruction requesting the allocation of two rename registers, and includes an allocation pointer (RAP) 510,
It comprises adders 511-517 and selectors 518-545. The operation is the same as the mechanism shown in FIG.
Compared to the case where only one rename register is assigned to one instruction, the structure is complicated even though the number of simultaneous dispatch instructions is the same.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to provide a processor having an out-of-order execution function using a rename register and having an instruction for generating a plurality of results to be written to the same architectural register. Is to realize a mechanism for allocating a rename register with the same complexity as a processor having only one instruction at a maximum.

[0010]

SUMMARY OF THE INVENTION The present invention comprises a rename register allocating mechanism for dividing rename registers into a plurality of groups and allocating a plurality of groups of rename registers. When assigning a rename register to an instruction for storing a plurality of execution results in the same architectural register, a plurality of groups are respectively assigned to the rename registers. As a result, even when there is an instruction requesting that a plurality of rename registers be allocated to store the execution result, a rename register allocation mechanism can be realized with the same scale as when there is only one allocation request, and the rename can be performed at high speed. Registers can be allocated.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a processor having an out-of-order execution function according to the present invention will be described below in detail with reference to the drawings. In the following embodiments, the rename registers are divided into two groups, but it goes without saying that the present invention is not limited to this.

FIG. 1 is a block diagram showing a configuration example of a processor having an out-of-order execution function using two groups of rename registers according to an embodiment of the present invention. The processor 100 includes an instruction fetch device 101, an instruction decoder 102, a rename register allocating device A103, and a rename register allocating device B1.
04, the rename register correspondence table management device 105,
It comprises an execution unit 106, a reorder buffer 107, a completion device 108, a rename register 109, and an architecture register 110. The processor 100
It is optional whether the whole is constituted by one chip.

In this embodiment, the number of entries in the architecture register 110 is 32 from R0 to R31, and the number of entries in the rename register 109 is 40 from B0 to B39.
The rename register 109 is defined as a first group GPA for B0 to B31 and a second group for B31 to B39.
It is distinguished as group GPB. There are four instructions that can be dispatched at the same time. Some of the instructions executed by the processor 100 produce two results.
The first result is identified as target A, and the second result is identified as target B. In the instruction, as the output destination (destination) of the result and the reference destination (source) of the value,
Only the same architecture register number can be used.

The processor 100 includes an instruction fetch device 10
In step 1, an instruction is read from an external memory or an instruction cache (not shown) and passed to the instruction decoder 102.

The instruction decoder 102 is a fetch device 101
It receives a maximum of four instructions, dispatches the instructions to the execution unit 106, and transmits control information indicating the architecture register number for storing the result to the reorder buffer 107 and the completion condition of the instruction, and manages the rename register correspondence table. The architecture register number (destination register number) where the instruction writes the result and the architecture register number (source register number) referencing the value are transmitted to the device 105. The instruction decoder 102 includes a target A detection unit 1021
And a target B detection unit 1022. The target A detection unit 1021 checks whether the first execution result exists in the instruction, and determines whether the first execution result exists in the rename register allocating device A10.
3 is notified of the necessity of a rename register allocation request for the instruction. Similarly, target B detection device 1022
Examines whether the second execution result is present in the instruction, and informs the rename register allocator B104 of the necessity of the rename register allocation request corresponding to the instruction.

The rename register allocating device A103 comprises:
Based on information from the target A detection unit 1021 of the instruction decoder 102, a rename register (number) is assigned to each instruction that needs to be assigned from the first group GPA of the rename register 109, and transmitted to the execution unit 106. Then, the rename register correspondence table 1051 is updated for the next instruction decoding. The rename register allocating device A103 is for allocating only the rename registers for the target A, and the maximum number of the rename registers allocated at a time is four.

FIG. 2 shows a more detailed configuration of the rename register allocating device A103. In the figure, reference numeral 1030 denotes an allocation pointer (GPAP) indicating a rename register number to start allocation, 1031 to 1033 are adders, 1034
Reference numerals 1039 to 1039 denote selectors, whose operations are basically the same as those in FIG. However, the pointer GPAP1030 is controlled to indicate any number of the first group GPA of the rename register 109. Also, this pointer 103
Even when the values indicated by the adders 1031, 1032, and 1033 are respectively added to 0, the control is performed in the rename register allocating device A 103 so as to always indicate the register number in the GPA.

The rename register allocating device B104 comprises:
Based on information from the target B detection unit 1022 of the instruction decoder 102, a rename register is assigned to each of the instructions that need to be assigned from the second group GPB of the rename register 109, and transmitted to the execution unit 106, Update the rename register correspondence table 1052 for instruction decoding. The rename register allocating device B104 is for allocating a rename register to the target B. Like the rename register allocating device A103, a maximum of four rename registers are allocated at a time.

FIG. 3 shows a more detailed configuration of the rename register allocating device B104. In the figure, reference numeral 1040 denotes an allocation pointer (GPBP) indicating a rename register number to start allocation, 1041 to 1043 denote adders, 1044
1049 are selectors, the operation of which is the same as that of FIG.
And basically the same. However, the pointer GPBP10
40 is controlled so as to indicate any number of the second group GPB of the rename register 109. Also, adders 1041 and 104 are added to the pointer 1040, respectively.
Even if the value indicated by 2,1043 is added, the value is controlled in the rename register allocating device B104 so as to always indicate the register number in GPB.

Rename register correspondence table management device 1
Reference numeral 05 denotes an architecture register number (a destination register number) in which an instruction transmitted from the instruction decoder 102 writes a result, and a rename register allocating device 10.
Rename register correspondence table 1051, which indicates the correspondence with the rename register numbers allocated in 3, 104
1052 is managed. Upon receiving the architecture register number (source register number) referred to by each instruction from the instruction decoder 102, the rename register correspondence table management device 105 refers to the rename register correspondence tables 1051 and 1052, and refers to the value referred to by the instruction to be executed. From which rename register should be read,
Alternatively, it is determined whether reading should be performed directly from the architecture register, and the result is transmitted to the execution unit 106. Tables 1051 and 1052 indicating the correspondence between the architecture register number and the rename register number are stored in the instruction decoder 102.
Register number of the architecture register in which the instruction transmitted from is stored the result
And the rename register number assigned by the rename register assignment device B 104 and the rename register number whose completion unit 108 has written back the result to the architecture register.

The execution unit 106 includes the instruction decoder 10
1. According to the information from the rename register allocating device A 103, the rename register allocating device B 104, and the rename register correspondence table managing device 105, the rename register 109 or the architecture register 11
Using 0, the instructions are executed in order from the instruction that has become executable, the result is written to the rename register 109, and the completion of the execution is notified to the completion unit 108.

The result written to the rename register 109 is sent to the reader buffer 107 by the completion unit 108.
Is written into the corresponding architectural register 110 so as to guarantee the order of instructions, and the execution of the instruction is completed. Further, the completion device 108 notifies the rename register correspondence table management device 105 of the name register number that has written the result in the architecture register 110.

As described above, in the description of the embodiment, one type of architectural register, the corresponding rename register, and the maximum number of rename registers assigned to one instruction are two.
However, even if these restrictions are changed, it can be easily understood by those skilled in the art, and thus the description thereof is omitted here.

[0024]

As described above, according to the present invention,
By dividing the rename registers into a plurality of groups and allocating the rename registers from each of the divided groups, even if there is an instruction requesting the assignment of a plurality of rename registers, at most one instruction can A mechanism for allocating rename registers can be realized with a structure similar to that in the case where only one rename register is allocated, and it becomes possible to allocate rename registers at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a processor according to an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a rename register allocating apparatus A of FIG. 1;

FIG. 3 is a detailed configuration diagram of a rename register allocating device B of FIG. 1;

FIG. 4 is a diagram illustrating a basic configuration example of a rename register allocating device.

FIG. 5 is a diagram showing a configuration example of a rename register allocating device according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 101 instruction fetch device 102 instruction decoder 1021 target A detection unit 1022 target B detection unit 103 rename register allocation device A 104 rename register allocation device B 105 rename register correspondence table management device 1051, 1052 rename register correspondence table 106 execution unit 107 reorder buffer 108 Completion device 109 Rename register 110 Architecture register

Claims (2)

[Claims] 1. A processor having an out-of-order execution function using a rename register, comprising: a rename register allocating mechanism for dividing a plurality of rename registers into a plurality of groups and allocating a rename register from each group. A processor characterized by the above-mentioned. 2. The processor according to claim 1, wherein the rename register allocating mechanism allocates a plurality of groups of rename registers to each result of an instruction for storing a plurality of execution results in the same architecture register. And processor.