JP2001231071A - Cell search device for asynchronous broadband direct sequence code division multiple access receiver, and method for acquiring code specific to each cell in the receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cell search device for an asynchronous broadband direct sequence code division multiple access receiver and a method for acquiring code specific to each cell in the receiver. SOLUTION: The cell search device for a receiver that searches for a cell from an asynchronous broadband direct sequence code division multiple access signal, includes a code group recognition section 260 that recognizes a code group by estimating a frequency error between a synchronous channel and a main synchronous code generated internally and a channel passed through the synchronous channel, compensating the error, and obtaining the correlation between the compensated synchronous channel and a sub synchronous code able to be generated and includes a scrambling code electronic camera section 270 that obtains the correlation between scrambling codes belonging to the code group shown by the sub synchronous code and a data channel to search a scrambling code specific to each cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an asynchronous wideband direct sequence code division multiple access (DC / CDMA) system.
The present invention relates to a cell search apparatus of a receiver and a method of acquiring a code specific to each cell in an asynchronous wideband direct sequence code division multiple access receiver.

[0002]

2. Description of the Related Art Asynchronous broadband DS / CDMA (Dir)
ect Sequence / CodeDivision
Multiple Access) system is IM
T-2000 (International Mobi)
le Telecommunications-200
0; International Mobile Telecommunications-2000), and is expected to be an important part of next-generation mobile telecommunications. This DS
The / CDMA system includes a synchronous system and an asynchronous system. The major difference between these two systems is that the synchronous system uses an external timing source, such as a wide area system, to synchronize time between cells, whereas the asynchronous system In this case, synchronization between cells is not performed.

In such a DS / CDMA system, each cell is divided by a spreading code. In the synchronous system, since synchronization performed between cells can be controlled, a code is assigned to each cell except for the phase of the spreading code. That is, only one unique spreading code is used. On the other hand, in the asynchronous system, since there is no available time information, different spreading codes are assigned to each cell.

In the cell search process in the DS / CDMA system, when starting communication between a mobile station (MS) and a base station (BS), an optimum cell is searched for from the MS and assigned to the cell. This is to acquire the synchronization of the spreading code and the code. In the asynchronous system, a relatively long time is required because the work performed in the process of searching for a cell is generally complicated as compared with the synchronous system.

[0005] The reason is that in the case of the synchronous system, since the spreading codes assigned to all cells are the same, it is only necessary to find out the phase of the code. On the other hand, in the asynchronous system, It is necessary to find not only the phase of the spreading code but also the spreading code sequence itself, which complicates the operation performed in the cell search process. For this reason, in the asynchronous CDMA system, the process of searching for a cell is very complicated, and thus it is an important process for determining the characteristics of the asynchronous CDMA system.

[0006] A spreading code for dividing each cell by a wideband CDMA system is called a "scrambling code". This scrambling code has a total of 5
There are twelve. If it is necessary to search all 512 in cell search, it takes a very long time and a lot of trouble. In order to solve such problems, the concepts of "code group" and "synchronization channel (SCH)" are applied in a wideband CDMA system.

The code group is obtained by dividing the scrambling code into a number of groups.
Each cell has its own code group,
As a result, it is possible to reduce the number of scrambling codes that the MS has to search for when searching for a cell. In a wideband CDMA system there are 64 code groups, with each group being assigned eight scrambling codes. Therefore, if a code group is detected once during a cell search, the number of scrambling codes to be searched can be reduced to eight. The code group assigned to each cell is determined by the SCH.

The SCH is a channel physically allocated in a downlink direction from a base station (BS) to a mobile station (MS) used for cell search, and is a main common control channel (p-CCPCH). ) Is time-multiplexed for each slot and transmitted. Such an SCH is composed of a main synchronization code (PSC) and a sub-synchronization code (SSC), and the PSC and SSC are transmitted simultaneously for each slot.

FIGS. 1 (a), 1 (b) and 1 (c) show a hierarchical structure of a synchronization channel. FIG. 1 (a)
Indicates one superframe composed of 72 frames. The progress time of this one superframe is 72
0 ms. FIG. 1B shows one frame composed of 15 slots. The progress time of this one frame is 10 ms. FIG. 1C shows a p-CCPCH composed of nine symbols, a PSC (C _p ) and an SSC (C _s ⁱ ) each composed of one symbol.
Is shown. The maintenance time of this one slot is 0.667 ms, and the one symbol is composed of 256 chips.

Each of the PSC and the SSC is a code sequence having a length of 256 chips, and there is one unique PSC common to all cells and 16 SSCs changing for each slot. Further, there is an orthogonal relationship between PSC and SSC.

[0011] The cell search is performed using the SCH. That is, first, a slot boundary is searched through slot synchronization, and a code group is recognized based on a correlation between an SSC and a received signal. Next, after the code group is recognized in this manner, the scrambling code allocated to each cell is searched for.

Therefore, when recognizing the code group, it is necessary to accurately find the SSC transmitted through the SCH of each slot. In an ideal usage environment,
1 for the received SCH signal of the 15 slots
6 and the SSCs of No. 6 are found, and the SSC that shows the maximum value is searched for. However, in an actual use situation, various factors cause performance degradation.
The main causes of this performance degradation include noise, channel changes in the mobile unit, and frequency errors due to frequency mismatch between the transmitter at the transmitting end and the receiver at the receiving end.

[0013] Among the main causes of these performance degradations, frequency errors are unavoidable phenomena caused by the physical characteristics of devices in the communication system, and greatly degrade the performance of the communication system. In particular, broadband DS / CD
Among various important problems in the MA system, one cell search is performed by determining a correlation between a received signal and various codes, and if the frequency error exists, the received signal is searched. This adversely affects the characteristics of the correlation with the SSC, and as a result, there is a problem that the probability of cell search is reduced and the cell search time is increased.

In order to minimize the performance degradation caused by such causes, first the results of the correlation between the received signal and the SSC over various frames are combined. The coupling method includes a coherent coupling and a non-coherent coupling.
Each of these coupling schemes has advantages and disadvantages.The coherent coupling has an advantage that it is relatively resistant to noise, but on the other hand, if the channel changes drastically and there is a frequency error, the performance is degraded. The disadvantage is that it becomes more intense. Conversely, non-coherent combining has the advantage of being relatively robust to channel changes and frequency errors, but is noisy and can severely degrade when the signal-to-noise ratio (SNR) degrades. It has the disadvantage of occurring.

[0015] Additive white Gaussian noise (Additive white Gau noise) such that the channel is in an ideal state and no frequency error occurs.
In a sian noise (AWGN) channel, the performance of coherent combining is about 3 dB better than the performance of non-coherent combining. Therefore, it is considered desirable to perform coherent combining by removing the influence of the frequency error and the channel in the received signal.

[0016]

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a method for estimating a frequency error and a channel, respectively, to compensate an estimated value for a received signal, A cell search device of an asynchronous wideband DS / CDMA receiver for searching for a cell by combining the results of the correlation between the frequency error and channel compensated signal and the SSC by coherent combining, and each of the receivers in the receiver. An object of the present invention is to provide a cell-specific code acquisition method.

[0017]

According to the present invention, there is provided a cell search apparatus for an asynchronous wideband direct sequence code division multiple access receiver according to claim 1 of the present invention. In a cell search apparatus of a receiver for searching for a cell from an asynchronous wideband direct sequence code division multiple access signal that includes and receives a synchronization channel and a data channel composed of a sub-synchronization code indicating a code group unique to each cell. Estimating and compensating for a frequency error between the synchronization channel and an internally generated main synchronization code, estimating and compensating for the channel through which the synchronization channel has passed, and A code group recognizing unit for recognizing the code group by obtaining a correlation with a synchronization code; Characterized in that it comprises a scrambling code recognition unit to locate each cell specific scrambling code seeking correlation between the plurality of scrambling codes and the data channels belonging to the code group.

According to another aspect of the present invention, there is provided a cell search apparatus for an asynchronous wideband direct sequence code division multiple access receiver according to claim 2 of the present invention. A main synchronization code generator, and a frequency error compensator for estimating a frequency error between the synchronization channel and a main synchronization code generated from the main synchronization code generator to compensate for an error estimated for the synchronization channel. A channel compensator for estimating channel characteristics from the frequency error compensated synchronization channel and compensating the channel characteristics estimated for the frequency error compensated synchronization channel; a channel compensated synchronization channel; Code group recognition unit that recognizes the code group by combining the result of the correlation with the secondary synchronization code To comprising a vessel.

According to another aspect of the present invention, there is provided a cell search apparatus for an asynchronous wideband direct sequence code division multiple access receiver according to claim 3 of the present invention. A switch coupled to receive the synchronization channel on one side, and a phase difference between the synchronization channel coupled to the other side of the switch and the main synchronization code generated from the main synchronization code generator. A frequency error estimator for converting the phase difference into a frequency error, a numerically controlled oscillator for generating a complex cosine wave corresponding to the frequency error, and the synchronization channel connected to the other side of the switch and entering through the switch. And a multiplier for multiplying the complex cosine wave.

Further, in order to solve the above problems,
According to a fourth aspect of the present invention, there is provided the cell search apparatus for an asynchronous wideband direct sequence code division multiple access receiver according to the third aspect, wherein the frequency error estimator comprises: a synchronous channel equally divided at predetermined intervals; A plurality of partial correlators for obtaining respective correlations with a main synchronization code generated from a synchronization code generator; and a division method for dividing two output values separated by a predetermined chip time from outputs of the partial correlators. A phase calculator for obtaining a phase from an output of the divider, and a multiplier for dividing an output of the phase calculator by the time and converting the output to a frequency. .

According to a fifth aspect of the present invention, there is provided a cell search apparatus for an asynchronous wideband direct sequence code division multiple access receiver according to the fifth aspect of the present invention. And an averager for adding the output of the divider for a predetermined number of times and averaging the number of times.

And, in order to solve the above-mentioned problem,
The cell search apparatus for an asynchronous wideband direct sequence code division multiple access receiver according to claim 6 of the present invention is the cell search apparatus according to claim 2, wherein the code group recognizer comprises: A plurality of correlators for determining a correlation between the code, a coherent combiner that adds all the outputs of the correlators to the square, and a sub-synchronous code when the output of the coherent combiner is equal to or more than a predetermined value is selected. And a selecting means for performing the setting.

According to another aspect of the present invention, there is provided an asynchronous wideband direct sequence code division multiple access receiver according to the present invention. A method for obtaining a scrambling code included in a code group from an asynchronous wideband direct sequence code division multiple access signal received including a synchronization channel and a data channel including a sub-synchronization code indicating a unique code group. (A) estimating and compensating for a frequency error between the synchronization channel and a main synchronization code generated by a main synchronization code generator; and (b) estimating and compensating a channel passed by the synchronization channel. And (c) determining the correlation between the compensated synchronization channel and the possible sub-synchronization codes. (D) recognizing a sub-synchronization code included in the synchronization channel; and (d) determining a correlation between a plurality of scrambling codes belonging to a code group indicated by the sub-synchronization code and the data channel. Searching for a unique scrambling code.

According to another aspect of the present invention, there is provided a method for acquiring a code unique to each cell in an asynchronous wideband direct sequence code division multiple access receiver according to claim 8 of the present invention. The step (a) includes (a)
1) equally dividing the synchronization channel at predetermined intervals for each slot, and obtaining respective correlations between the equally divided synchronization channel and the main synchronization code generated from the main synchronization code generator; (A2) dividing two output values separated by a predetermined chip time among output values of the correlation result of the step, (a3) obtaining a phase from the result of the division in the step, (a4) Ii) dividing the obtained phase by the time to convert it into a frequency, and (a5) compensating for the synchronization channel more by the frequency.

Further, in order to solve the above-mentioned problem, a method for acquiring a code specific to each cell in an asynchronous wideband direct sequence code division multiple access receiver according to claim 9 of the present invention is as described in claim 8. In the step a1), the equal interval of the synchronization channel is 16 times the chip length.

In order to solve the above problem, a method for acquiring a code unique to each cell in an asynchronous wideband direct sequence code division multiple access receiver according to claim 10 of the present invention is as described in claim 8. The time of step a2) is one half of the length of the synchronization channel chip.

[0027]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited to only this embodiment, and can be appropriately modified as long as it is based on the technical idea of the present invention. FIG. 2 shows a broadband DS / C according to the present invention.
It is a block diagram of a DMA receiver. As shown in FIG.
The broadband DS / CDMA receiver according to the present invention includes an antenna 200, a radio frequency (RF) receiver 210, a down converter 220, a low-pass filter (LPF) 230, an analog-to-digital converter (ADC) 240, and a slot synchronization unit. 250, a code group recognition unit 260, a scrambling code recognition unit 270, and a demodulation unit 280.

The slot synchronizing section 250 includes a correlator 25
1, a PSC generator 252, a PSC synchronization detector 253, a verifier 254, and a PSC synchronization adjuster 255. In addition, the code group recognition unit 260 includes a frequency error compensator 261, a channel compensator 262, and a code group recognizer 263. The scrambling code recognition unit 270 is a
1. Scrambling code generator 272, correlator 27
3 and a scrambling code recognizer 274.

Broadband DS / CDMA with the above configuration
The operation of the receiver is as follows. First, RF receiver 2
10 receives the RF signal entering through antenna 200 and converts it to an intermediate frequency (IF) signal. The down converter 220, the LPF 230, and the ADC 240
Convert the signal to a baseband discontinuous signal.

The slot synchronizer 250 includes an ADC 240
The slot is synchronized by searching for a slot boundary from the SCH output from. That is, PSC
The point in time when the peak appears in the output of the matched filter with respect to is the point in time when the slots are synchronized. The correlator 251 is
PSC output from PSC generator 252 and ADC 24
0 to determine the correlation between the SCH and the output SCH.
The C synchronization detector 253 detects a slot synchronization signal from the output of the correlator 251.

The PSC synchronization adjuster 255 adjusts the synchronization signal of the slot output from the PSC synchronization detector 253 so as to match the synchronization signal of the received signal, and outputs the result from the PSC generator 252. The verifier 254 verifies whether or not the PSC synchronization detector 253 can acquire the slot synchronization signal, and outputs the result from the correlator 251.

The code group recognizing section 260 has a function of ADC2.
A frequency error and a channel are compensated for the SCH output from 40, and a code group is recognized. And
This code group is determined by the SSC. One frame is composed of 15 slots. Then, one SS out of 16 SSCs for each slot
C is transmitted simultaneously with PSC. That is, 15 SSCs are transmitted in one frame. A code group is determined by 15 consecutive SSCs transmitted in one frame.

Further, the code group recognizing section 260 receives the slot synchronization information found by the slot synchronization section 250 and the 16 SSCs and the S S output from the ADC 240.
By determining the correlation with the CH, the transmitted SSC can be detected, and as a result, the code group can be recognized and the frame synchronization can be obtained.

The frequency error compensator 261 estimates a frequency error between the PSC generated from the PSC generator 252 and the SCH output from the ADC 240, and compares the estimated frequency error with the SC output from the ADC 240.
Compensate for H. SC output from ADC 240
H includes the frequency error ω due to the mismatch of the oscillation frequency between the transmitting end and the receiving end.

The channel compensator 262 estimates the characteristics of the complex channel from the output signal of the frequency error compensator 261. Then, the characteristic of the complex channel estimated in this way is compensated for the output signal of the frequency error compensator 261. The code group recognizer 263 is the channel compensator 2
The correlation between the 62 output signals and the 16 SSCs is determined, and the results are coherently combined on a frame-by-frame basis to detect the SSC and obtain a frame synchronization signal.

The scrambling code recognition unit 270
The eight scrambling codes belonging to the code group determined by the code group
The correlation with the data output from the C240 is obtained to find the scrambling code assigned to each cell. The code synchronization adjuster 271 adjusts the synchronization of the scrambling code using the frame synchronization signal obtained by the code group recognizer 263.

The scrambling code generator 272 includes:
Based on the synchronization signal adjusted by the code synchronization adjuster 271, eight scrambling codes belonging to the code group recognized by the code group recognizer 263 are generated. The correlator 273 includes the data output from the ADC 240 and the scrambling code generator 272.
The correlation between each of the eight scrambling codes generated from. The scrambling code recognizer 274 recognizes the scrambling code based on the result of the correlator 273. The demodulation unit 280 performs normal rake processing and demodulation to output data.

FIG. 3 is a detailed block diagram of the code group recognition section 260 shown in FIG. The code group recognition unit includes a frequency error compensator 261, a channel compensator 262, and a code group recognition 263, as shown in FIG. The frequency error compensator 261 includes a switch 301, a frequency error estimator 302, a numerically controlled oscillator (NCO) 303, and a multiplier 304. The channel compensator 262 includes a channel estimator 311,
It comprises a complex conjugate unit 312 and a multiplier 313. The code group recognizer 263 includes a correlator 321, a coherent combiner 322, a code group recognizer and a frame synchronizer 323.

The operation according to the above configuration is as follows. The frequency error compensator 261 estimates and compensates for a frequency error with respect to the SCH output from the ADC 240. The frequency error estimator 301 receives the SCH and P output from the ADC 240 input through the switch 301.
An estimated value ω ′ is output for the frequency error ω between the SC generator 252 and the PSC generated. NCO30
3 generates a complex cosine wave corresponding to this ω ′. The multiplier 304 compensates for a frequency error by multiplying the complex cosine wave output from the NCO 303 by the SCH output from the ADC 240. The estimation of the frequency error will be described in more detail with reference to FIG.

The channel compensator 262 shown in FIG.
The channel characteristics included in the SCH output from the 240 are estimated, and the estimated characteristics are compensated for the SCH output from the ADC 240. The channel estimator 311
The channel characteristics are estimated by a normal method, and parameters necessary for the channel estimation are updated for each slot using the correlation between the signal whose frequency error has been compensated by the multiplier 304 and the PSC.

The complex conjugate unit 312 shown in FIG. 3 calculates a complex conjugate for the estimated channel value. Multiplier 313
Is the signal output from the multiplier 304 and the complex conjugate 31
By compensating the channel by multiplying the SCH by the output of No. 2 to remove the frequency error and the influence of the channel on the SCH output from the ADC 240.

The code group recognizer 263 shown in FIG.
It recognizes a code group included in the SCH output from the ADC 240 and acquires a frame synchronization signal. The correlator 321 shown in FIG. 3 calculates the correlation between the signal output from the multiplier 313 and the 16 SSCs.
At this time, the correlator 321 performs a 16-point high-speed Hadamard transform. The coherent combiner 322 performs coherent combining of the results output from the correlator 321 in frame units. Here, it is desirable to perform coherent combining since the frequency error and the influence of the channel have already been eliminated.

The code group recognition and frame synchronizer 323 shown in FIG. 3 is used when the value output from the coherent combiner 322 is larger than a predetermined threshold value or when the respective output values are compared to be the maximum value. Finally, the 15 SSCs transmitted in one frame are detected. Further, a code group is recognized from the detected SSC value to obtain a frame synchronization signal.

FIG. 4 shows the configuration of the coherent coupler 3 shown in FIG.
22 is a detailed block diagram of No. 22. FIG. This coherent combiner includes a plurality of adders 401 and 40 as shown in FIG.
, 403 and a multiplier 410. If the output values of the correlator 321 are Z ₁ , Z ₂ ,..., Z _L , the adders 401, 402,..., 403 add all the correlation values. The multiplier 410 squares a value obtained by adding all the correlation values, and outputs a coherent combination value Z as shown in the following equation (1).

[0045]

(Equation 1)

FIG. 5 shows the frequency error estimator 3 shown in FIG.
FIG. 2 is a block diagram for explaining No. 02 in more detail. As shown in FIG. 5, the frequency error estimator includes a plurality of partial correlators 500, 510, and 520, and a plurality of dividers 501 and 51.
1, 521, an averager 530, a phase calculator 540 and a multiplier 550.

The operation of the frequency error estimator is as follows. The partial correlators 500, 510, and 520 are ADCs
In the SCH output from 240, the SCH having a length of 256 chips in each slot is divided into M equal parts, and the PS shown in FIG.
The partial correlation between the complex conjugate of the PSC generated from the C generator 252 and the M-divided SCH is determined. In other words, instead of determining the correlation between the SCH and the PSC for the entire 256 chips, the PSC is divided by M intervals, which is a number having a chip length of 16 times, and the correlation of the partial interval for each is divided. Ask for a relationship. Note that M is any one of 2, 4, 8, and 16. And the partial correlators 500, 510, 520
Conveniently, it consists of a matched filter or an active correlator. The outputs from the partial correlators 500, 510, and 520 are performed using phase values.

This will be described in more detail as follows. In the estimation of the frequency error included in the cell search apparatus of the asynchronous wideband direct sequence code division multiple access receiver according to the present invention, the PSC and the SSC have an orthogonal relationship in units of 16 chips as shown in the following equation (2). This is performed using the characteristic of the correlation of having.

[0049]

(Equation 2)

In the above equation (2), n indicates the index of the SSC and is a value of 1, 2,... I is 0
The above is a positive number, and J is one or more positive numbers satisfying (I + J) ≦ 16. That is, the present invention relates to PSC and SSC
The orthogonality can be maintained even if the correlation between partial sections is obtained only between 16-times multiple chips instead of obtaining the correlation over the entire section between 256 chips which is one cycle. It has.

Here, it is assumed that a chip-based complex signal received in the SCH section of one slot is r (n). Now, assuming that there is no flat fading environment, that is, there is no multipath, this r (n) is represented by the following equation (3).

[0052]

(Equation 3)

In the above equation (3), x (n) is the following equation (4A), (4B), (4) as the transmitted complex SCH signal.
C).

[0054]

(Equation 4)

In the above formula (3), h (n) is SCH
This is the complex channel through which the signal has passed in the interval, and N (n) is the complex Gaussian noise. Here, the frequency error f _e
When there is, r (n) changes as represented by the following equation (5).

[0056]

(Equation 5)

In the above equation (5), T _c is a chip section, and φ is an arbitrary phase having a uniform distribution in the [0, 2π] section. The signal received in the SCH section is divided by M blocks, which is the number of chip lengths of 16N. Note that this N
Takes one of the values 1, 2, 4, and 8,
M takes a value of M = 16 / N corresponding to N. SC
The reason why the signal received in the H section is divided by the chip length of 16N is to take advantage of the property that the PSC and the SSC have an orthogonal relationship in units of a minimum of 16 chips.

In the embodiment of the present invention, the frequency error
Two assumptions were made for estimation. That is, the first
The assumption is that the channel is not changed in the SCH section. No.
The second assumption is that one block out of several M blocks
The phase due to the frequency error in one section is φ₀,
φ₁, ... φ_M-1And each is constant, φ_{M / 2 + m}−
φ _m= 2πf_e(128T_c)
You.

The first assumption is appropriate in view of the actual use situation, and the second assumption is that the phases of signals belonging to one block are all the same and the phase difference between blocks separated by 128 chips is different. Means the same as the phase change due to the frequency error.

Here, the SCH corresponding to several M blocks
The signals are r ₀ (n), r ₁ (n),.
_{If M-1} (n), by the second assumption, r
_m (n) (m = 0, 1,..., M-1) is represented by the following equation (6).

[0061]

(Equation 6)

In the above formula (6), n = 0, 1,..., 16N
−1, and m = 0, 1,..., M−1. Also, h
Represents the magnitude of the complex channel.

In the method described above, the ADC 240 (see FIG. 2)
By modeling the SCH output from, the SCH signal received in one interval can be regarded as a signal in which noise is excessive after a complex constant is multiplied to the transmission signal, and thus the PSC and the SSC are Can be used. That is, when the correlation between the signal received for each of the M blocks and the PSC is obtained, the resulting Y _m (m = 0, 1,..., M
-1) is represented by the following equation (7).

[0064]

(Equation 7)

[0065] In the above formula (7), k is a positive number, the N _m is a component caused by noise after obtaining the correlation between the PSC and SSC. Here, from the number M of Y _m to M /
It is possible to determine the phase change between 2 128 chips, when obtaining the Y _m for the block number M, as follows. That is, the phase change is calculated by the dividers 501 and 51.
1, 521, an averager 530 and a phase calculator 540 (see FIG. 5).

That is, the dividers 501 and 51 shown in FIG.
1, 521 is a division Y _M in a combination of Y _{M / 2 + m} and Y _m , which are two values separated by a length of 128 chips among the results output from the respective partial correlators 500, 510, and 520. _{/ 2} executes _{+ m} / Y _m. The averaging unit 530 is the divider 5
01, 511 and 521 are averaged. The phase calculator 540 obtains a phase for the result output from the averager 530. At this time, the dividers 501 and 51
If the phase for each output value of 1, 521 is obtained, it is also possible to obtain the phase change Δφ by averaging the phases thus obtained. When these results are expressed by equations, the following equations (8A) and (8B) are obtained.

[0067]

(Equation 8)

The multiplier 550 calculates 1 / [2
π (ΔT)] to output an estimated value of the frequency error. In the embodiment of the present invention, ΔT is 128T _c
It is. The frequency error estimated value f 'is expressed by the following equation (9).

[0069]

(Equation 9)

[0070]

According to the cell searching apparatus and the cell-specific code acquisition method of the asynchronous wideband direct sequence code division multiple access receiver according to the present invention configured as described above, the frequency error is estimated. By compensating for it, it becomes possible to improve the performance of cell search,
Ultimately, the cell search time can be shortened.

Further, when the cell search apparatus of the asynchronous wideband direct sequence code division multiple access receiver and the method of acquiring a code specific to each cell according to the present invention are applied, cell search is performed by adding only a simple operation. Therefore, the burden on additional hardware can be reduced.

Further, the method of estimating and compensating for a frequency error included in the present invention can be applied to automatic frequency control and NCO control in a software defined radio system.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are diagrams hierarchically showing a structure of a synchronization channel. FIG.

FIG. 2 is a block diagram of a wideband DS / CDMA receiver according to the present invention.

FIG. 3 is a detailed block diagram of a code group recognition unit shown in FIG. 2;

FIG. 4 is a detailed block diagram of the coherent combiner shown in FIG. 3;

FIG. 5 is a block diagram illustrating the frequency error estimator shown in FIG. 3 in more detail.

[Explanation of symbols]

 Reference Signs List 200 antenna 210 radio frequency receiver 220 down converter 230 low-pass filter 240 analog-to-digital converter 250 slot synchronization unit 260 code group recognition unit 270 scrambling code recognition unit 280 demodulation unit

Claims (10)

[Claims] 1. An asynchronous wideband direct sequence code division multiple access signal received including a synchronization channel and a data channel comprising a main synchronization code common to all cells, a sub-synchronization code indicating a code group unique to each cell, and In a cell search apparatus of a receiver that searches for a cell, a frequency error between the synchronization channel and a main synchronization code generated internally is estimated and compensated, and a channel passed by the synchronization channel is estimated and compensated. A code group recognizing unit for recognizing the code group by determining a correlation between the compensated synchronization channel and a possible sub-synchronization code; and a plurality of scrambling codes belonging to the code group indicated by the sub-synchronization code. And the data channel to find a scrambling code unique to each cell. Cell search apparatus of a direct sequence code division multiple access receiver asynchronous wideband, characterized in that it comprises a scrambling code recognition unit issuing. 2. The code group recognition unit estimates a frequency error between a main synchronization code generator, a main synchronization code generated from the main synchronization code generator and the main synchronization code, and calculates a frequency error between the main synchronization code and the main synchronization code. A frequency error compensator for compensating for the estimated error, a channel compensator for estimating channel characteristics from the frequency error compensated synchronization channel, and compensating for the estimated channel characteristics for the frequency error compensated synchronization channel. 2. The code group recognizer according to claim 1, further comprising a code group recognizer for recognizing the code group by combining a correlation result between the channel compensated synchronization channel and the plurality of sub-synchronization codes. Cell search device for asynchronous wideband direct sequence code division multiple access receiver. 3. The frequency error compensator includes: a switch connected to receive the synchronization channel on one side; and a switch connected to the other side of the switch and generated from the synchronization channel and the main synchronization code generator. A frequency error estimator that calculates a phase difference between the main synchronization code and the phase difference, converts the phase difference into a frequency error, a numerically controlled oscillator that generates a complex cosine wave corresponding to the frequency error, and the other side of the switch. 3. The asynchronous wideband direct sequence code division multiple access receiver according to claim 2, further comprising a multiplier for multiplying the complex cosine wave by the synchronous channel input through the switch. Cell search device. 4. The frequency error estimator includes: a plurality of partial correlators for obtaining respective correlations between a synchronization channel equally divided at predetermined intervals and a main synchronization code generated from the main synchronization code generator. A divider that divides two output values separated by a predetermined chip time among outputs of the partial correlator, a phase calculator that obtains a phase from an output of the divider, and an output of the phase calculator. 4. The cell search apparatus for an asynchronous wideband direct sequence code division multiple access receiver according to claim 3, further comprising a multiplier that divides by time to convert to frequency. 5. The asynchronous circuit according to claim 4, wherein the frequency error estimator further comprises an averager for adding the output of the divider a predetermined number of times and averaging the output by the number of times. Cell searcher for a wideband direct sequence code division multiple access receiver. 6. The code group recognizer, further comprising: a plurality of correlators for calculating a correlation between an output of the channel compensator and the plurality of sub-synchronization codes; The asynchronous broadband as claimed in claim 2, comprising: a coherent combiner; and selecting means for selecting a sub-synchronization code when an output of the coherent combiner is equal to or greater than a predetermined value. Cell search device for direct sequence code division multiple access receiver. 7. An asynchronous wideband direct sequence code division multiple access signal received including a synchronization channel and a data channel comprising a main synchronization code common to all cells, a sub-synchronization code indicating a code group specific to each cell, and And (c) estimating and compensating for a frequency error between the synchronization channel and a main synchronization code generated by a main synchronization code generator. (B) estimating and compensating the channel through which the synchronization channel has passed, and (c) determining a correlation between the compensated synchronization channel and a possible sub-synchronization code to be included in the synchronization channel. (D) a plurality of scramblings belonging to a code group indicated by the sub-synchronization code. Determining a correlation between a code and said data channel to find a scrambling code specific to each cell. A code specific to each cell in an asynchronous wideband direct sequence code division multiple access receiver. Acquisition method. 8. The step (a) comprises: (a1) equally dividing the synchronization channel for each slot at a predetermined interval, and dividing the equally divided synchronization channel into a main synchronization code generated by the main synchronization code generator. (A2) dividing two output values separated by a predetermined chip time from among output values resulting from the correlation of the step, (a3) the step of: (A4) dividing the obtained phase by the time and converting it into a frequency; and (a5) compensating the synchronization channel by the frequency more by the frequency. 8. The method of claim 7, wherein the code is unique to each cell in the asynchronous wideband direct sequence code division multiple access receiver. 9. The method of claim 8, wherein in the step (a1), the equal interval of the synchronization channel is a chip length of a multiple of sixteen.
A method for acquiring a code specific to each cell in an asynchronous wideband direct sequence code division multiple access receiver. 10. The asynchronous wideband direct sequence code division multiple access receiver according to claim 8, wherein the time of the step (a2) is １ ／ of the length of the synchronization channel chip. Code acquisition method specific to each cell.