JP2001230252A - SEMICONDUCTOR DEVICE HAVING Cu-BASED EMBEDDED WIRING AND PULSE PLATING METHOD OF Cu-BASED EMBEDDED WIRING - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform Cu-based embedded wiring which is superior in adhesive ness and embedding at low cost, in a semiconductor device having Cu-based embedded wiring and a pulse plating method of Cu-based embedded wiring. SOLUTION: A Cu alloy layer is provided between a barrier metal and an alloy composed of either Cu or an alloy whose main component is Cu.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a Cu-based buried interconnect and a pulse plating method for the Cu-based buried interconnect, and more particularly to a damascene method.
Ne) A semiconductor device having a Cu-based buried wiring characterized by a technique for forming a Cu-based plating layer having excellent adhesion when forming a fine Cu-based buried wiring by using the method, and a Cu-based buried wiring. The present invention relates to a pulse plating method for embedded wiring.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor devices, or
With the increase in speed, there has been a demand for lowering the resistance of the wiring layer in order to reduce the signal delay. Cu wiring, which is about twice as large as
It is used as a highly integrated and miniaturized LSI wiring material.

However, in general, when a fine wiring layer is formed, it is necessary to perform dry etching. In the case of Cu, however, conventional RIE (reactive ion etching) is used because the vapor pressure of a halide of Cu is low. The method has a problem that a sufficient etching rate cannot be obtained at a low temperature, a problem that anisotropic etching is difficult, and a problem that corrosion occurs due to halide residues.

[0004] Therefore, Cu which is difficult to perform such fine processing is used.
As one of effective methods for forming wiring, a method called a damascene method using a self-alignment technique has been developed. This damascene method means that a Cu film is deposited and buried in a groove along a wiring pattern provided in an interlayer insulating film and a via hole, and an unnecessary portion on an upper portion is chemically mechanically polished (CMP: Chemical Mechanical).
This is a method of forming a buried conductive layer by removing by a polishing method.

In this case, as a method of depositing a Cu film in a groove or a via hole, a CVD (chemical vapor deposition) method having excellent step coverage and a sputtering method having poor step coverage are used. And the subsequent reflow, electrolytic plating method or electroless plating method are being studied.

In the case where a Cu embedded wiring layer is formed by a damascene method, Cu easily diffuses in SiO ₂ constituting an interlayer insulating film, forms a deep level in a silicon semiconductor, and forms a minority carrier. Since the life is shortened, it is necessary to interpose a barrier metal layer such as a TiN layer between the SiO ₂ layer and the Cu layer in order to prevent the diffusion of Cu.

[0007] Of the above-mentioned methods, electrolytic plating is used to obtain C
In the case of embedding a u film, a Cu plating layer cannot be directly electrolytic-plated on a barrier metal such as TiN, so that a plating base layer made of a thin Cu film in advance, ie, C
u seed layer is formed on the surface of the barrier metal, and Cu
An electric current is passed through the Cu seed layer in the plating solution to form a Cu plating layer on the Cu seed layer.

If the step coverage is poor, such a Cu seed layer has a via hole (Via) or a trench (T).
(Rench), the Cu embedded wiring process is greatly affected by the Cu seed layer, for example, the embedding by the Cu plating layer becomes incomplete.

For this reason, the Cu seed layer needs to be a thin film that does not change the shape of the via hole or the groove. However, the thin film is formed with good coverage by a sputtering method having excellent adhesion to the barrier metal layer. It is difficult to form a film.

On the other hand, when a CVD method having excellent coverage is used, it is possible to form a thin film. However, a Cu thin film formed by the CVD method is in close contact with a barrier metal layer such as TiN. There is a problem that the force is weak, and in some cases, adverse effects such as a gap between the barrier metal layer and the Cu buried layer are formed.

Therefore, when the Cu buried layer is formed by the electrolytic plating method, it is important to improve the adhesion between the Cu seed layer and the barrier metal layer. Therefore, in order to improve the adhesion between such a Cu seed layer and a barrier metal layer, an attempt was made to form a Cu seed layer using a so-called cementation method, and this was described with reference to FIG. I do.

Referring to FIG. 7A, first, a seed layer 32 made of Zn with good adhesion to the TiN barrier metal layer 31 is formed on the TiN barrier metal layer 31.
Is formed by a CVD method having excellent coverage to obtain a sample.

Next, as shown in FIG. 7 (b), a cyan (CN) bath or ammonia (NH ₃ ) which can form a complex of Cu and Zn contained in the substitution tank 33 is used.
The sample is immersed in a Cu replacement liquid 34 consisting of a bath.

Next, a cementation reaction of Zn + Cu ²⁺ → Zn ²⁺ + Cu occurs in the Cu replacement liquid 34, and the seed layer 32 made of Zn is replaced with the Cu seed layer 35.

Next, the sample on which the Cu seed layer 35 has been formed is pulled up from the Cu replacement solution 34 and immersed in a Cu plating solution 37 containing copper sulfate contained in a plating tank 36, and a power source 38 is provided. The anode 39 side is made positive (+) and the TiN barrier metal layer 31 side is made negative (-) through the, and a direct current is caused to flow in the forward direction.
A Cu plating layer 40 is formed on the u seed layer 35.

As described above, when the cementation method is used, since the seed layer 32 made of Zn having excellent adhesion to the TiN barrier metal layer 31 is formed first, the inside of the via hole or the groove is plated with Cu. When embedding with a layer, it becomes possible to form a Cu plating layer without generating a gap between the layer and the barrier metal layer.

The seed layer 32 made of Zn as described above is used.
This example is described with reference to FIG. Referring to FIG. 8A, first, a seed layer 32 made of Zn having good adhesion to the TiN barrier metal layer 31 is formed on the TiN barrier metal layer 31.
Is formed by a CVD method having excellent coverage to obtain a sample.

Next, this sample is immersed in a Cu plating solution 37 containing copper sulfate contained in a plating tank 36, and the anode 39 side is made positive (+) through a power source 38, and TiN The Cu plating layer 40 is formed directly on the seed layer 32 by passing a direct current in the forward direction with the barrier metal layer 31 side being negative (-).

Also in this case, since the seed layer 32 made of Zn having excellent adhesion to the TiN barrier metal layer 31 is formed, when filling the via hole or the trench with the Cu plating layer, the gap between the TiN barrier metal layer 31 and the barrier metal layer is reduced. Thus, it is possible to form a Cu plating layer without generating a gap.

[0020]

However, when the cementation method is used, the replacement solution for replacing Zn with Cu is limited to a cyan bath or an ammonia bath. Cannot be performed, it is necessary to prepare a Cu plating solution separately from the replacement solution when forming the Cu plating layer, and there is a problem that the cost increases.

When electrolytic plating is performed on the Zn seed layer 32 by a DC electric field, the adhesion between the Zn seed layer 32 and the Cu plating layer 40 is not always sufficient. is there.

Accordingly, an object of the present invention is to form a Cu-based buried wiring having excellent adhesion and burying properties at low cost.

[0023]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. In addition, FIG.
It is a figure showing a basic process of a pulse plating method of the present invention which omitted a semiconductor substrate, a slot, a hole, etc. See FIG. 1. (1) The present invention relates to a semiconductor device having a Cu-based buried interconnect, wherein a barrier metal 1 and a Cu-based plating layer 8 made of either Cu or an alloy containing Cu as a main component are provided. It is characterized by having a Cu alloy layer having a different composition from the Cu-based plating layer 8.

As described above, between the barrier metal 1 and the Cu-based plating layer 8, the Cu-based plating layer 8 has a composition different from that of the Cu-based plating layer 8.
By providing the alloy layer, the adhesion between the barrier metal 1 and the Cu-based plating layer 8 and the embedding property can be improved. The alloy containing Cu as a main component is, for example,
The Cu alloy layer having a composition different from that of the Cu-based plating layer 8 is, for example, a Cu-based plating layer 8.
Is different from the composition ratio of Cu-Zn alloy or Cu-F
e alloy or the like.

(2) The present invention also provides a step of providing at least one of a groove and a hole in an insulating film in a pulse plating method of a Cu-based buried wiring, and forming a barrier metal on a surface of the insulating film and an exposed surface of the groove or the hole. 1, a step of forming a first seed layer 2 made of a metal other than Cu on the barrier metal 1, and Cu or an alloy containing Cu as a main component by using an electric field pulse having a reverse direction and a forward direction. And a step of forming the plating layer 8 made of any one of the above-mentioned Cu-based conductors by electrolytic plating.

As described above, the first seed layer 2 made of a metal other than Cu, that is, the seed layer 2 made of the metal M having better adhesion to the barrier metal 1 than Cu is provided on the barrier metal 1. By using an electric field pulse composed of a reverse direction and a forward direction, at least a part of the seed layer 2 is melted to form the second seed layer 7 made of a Cu alloy. The adhesion is improved as compared with the case where the plating layer 8 made of a Cu-based conductor is plated by a DC electric field.

The direction of the electric field generated by the power source 3 is reversed by applying a pulse current in the reverse direction so that the anode 6 side becomes negative, so that the first seed layer 2 is melted by the reaction of M → M ²⁺ + 2e, ,
By applying a forward pulse current so that the direction of the electric field by the power supply 3 is positive on the anode 6 side, M ²⁺ + 2e →
The reaction of M and Cu ²⁺ + 2e → Cu occurs on the negative electrode side to form a second seed layer 7 made of an M—Cu alloy. Finally, a forward direct current electric field causes Cu ²⁺ + 2e → The Cu-based plating layer 8 is formed by the reaction of Cu. In addition,
If the plating solution 5 stored in the plating tank 4 is a Cu plating solution, the Cu-based plating layer 8 becomes a pure Cu plating layer,
In the case where other metal elements are contained, a Cu-based alloy plating layer containing Cu as a main component is formed.

(3) The present invention also provides a step of providing at least one of a groove and a hole in an insulating film in a pulse plating method for a Cu-based buried wiring; Forming an insoluble auxiliary electrode in a plating bath of a Cu-based conductor made of either Cu or an alloy containing Cu on the barrier metal 1; forming Cu on the auxiliary electrode Forming a first seed layer 2 made of a metal other than the above, and forming an electroplated plating layer 8 made of a Cu-based conductor by using electric field pulses having a reverse direction and a forward direction. And

As described above, by disposing an insoluble auxiliary electrode between the barrier metal 1 and the first seed layer 2 in a Cu-based conductor plating bath, the entire first seed layer 2 is dissolved. Also in this case, since it becomes possible to perform electrolytic plating, strictness is not required for the operation of the pulse electric field, and the control is facilitated. In this case, Pt, Ag, or Au is suitable for the auxiliary electrode because it is desirable that the auxiliary electrode has good conductivity in addition to being insoluble in the plating bath.

(4) In the present invention, in the above (2) or (3), in the electroplating step, at least a part of the first seed layer 2 is dissolved by a pulse electric field applied in the reverse direction first. Then, after the second seed layer 7 is formed by a forward pulse electric field, a plating layer 8 made of a Cu-based conductor is formed by electroplating by a forward pulse electric field.

As described above, by dissolving at least a part of the first seed layer 2 by the initially applied reverse pulse electric field, the element forming the first seed layer 2 and the Cu-based conductor are dissolved. The second seed layer 7 made of an alloy can be formed, whereby the adhesion between the seed layer and the plating layer 8 made of a Cu-based conductor can be improved.

(5) According to the present invention, in the above (4), the amount of backward integrated current and the amount of forward integrated current of the pulse electric field applied in the step of forming the second seed layer 7 are made equal, or The present invention is characterized in that the backward integrated current amount flowing in one cycle is made equal to the forward integrated current amount and the backward integrated current amount is sequentially reduced.

As described above, the amount of backward integrated current and the amount of forward integrated current of the pulse electric field applied in the step of forming the second seed layer 7 are made equal, or the amount of backward integrated current flowing in one cycle is By making the forward integrated current amount equal and sequentially reducing the backward integrated current amount, the second
The in-plane distribution of the composition of the seed layer can be made uniform, and the plating layer 8 can be formed with a smooth film thickness distribution with little unevenness on the surface.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a plating process according to a first embodiment of the present invention will be described with reference to FIGS. 2 to 4. First, referring to FIG. A pulse waveform diagram of an applied current according to the first embodiment will be described. In FIG. 2, a Zn seed layer having a thickness of 100 nm was formed on a SiO ₂ wafer via a TiN barrier metal layer, and then a substrate cut into an area of 2 cm × 2 cm was used as a sample and placed in a plating tank. An experiment was conducted by accommodating 200 cc of a copper sulfate-based ordinary Cu plating solution.

First, in the seed layer dissolving step, for example, 100 m
After flowing a reverse current of A / cm ² for 20 ms to dissolve a part of the seed layer, a forward current of 10 mA / cm ² is applied for 20 ms, for example, for 10 to 30 cycles, for example, 10
A Zn—Cu alloy seed layer is formed by periodic flow, and finally a forward direct current is passed to form a Cu plating layer.

Next, the composition of the Zn—Cu alloy seed layer will be described with reference to FIG. FIG. 3A is a diagram showing a case where the pulse potential applied in the deposition step is equal to or higher than the Zn deposition potential even at a low potential.
By dissolving a part of 3 and then applying a pulse electric field equal to or higher than the Zn deposition potential, the Cu seed layer 17 is deposited because Zn is lower than Cu. Note that reference numeral 16
Is a melting part of the Zn seed layer 13.

FIG. 3B shows a case where the pulse potential applied in the deposition step is higher than the Zn deposition potential at a high potential and lower than the Zn deposition potential at a low potential. Yes,
A part of the Zn seed layer 13 is dissolved by the first reverse electric field, and when a pulse electric field higher than the Zn deposition potential is applied, the Cu seed layer 18 is deposited as in the case of FIG. When a pulse electric field equal to or lower than the Zn deposition potential is applied, the Zn-Cu alloy seed layer 19 is deposited. When a pulse electric field equal to or higher than the Zn deposition potential is applied, the Cu seed layer 20 is changed. Precipitates.

FIG. 3 (c) is a diagram showing a case where the pulse potential applied in the deposition step is equal to or lower than the Zn deposition potential even at a high potential. Layer 1
3 is melted, and then a Zn-Cu alloy seed layer 21 is deposited by applying a pulsed electric field of a Zn deposition potential or less.

Therefore, the composition of the Zn—Cu alloy seed layer can be arbitrarily set according to the forward potential of the applied pulse electric field. In the case of the first embodiment, the Zn—Cu alloy seed layer The potential is set so that the entirety of 14 becomes a Zn-Cu alloy.

When an element (M) which is more noble than Cu is used as the metal constituting the seed layer, the result opposite to that of FIG. 3 is obtained, and when the potential is low, the M-Cu alloy is used. If a seed layer is formed, while the potential is high, an M seed layer will be formed again, and the plating solution will remove C
The u plating layer cannot be formed.

Next, referring to FIG. 4, a first embodiment of the present invention in which the plating step shown in FIG. 2 is applied to the formation of a Cu embedded wiring layer.
The plating step of the embodiment will be described. 4A. First, SiO ₂ deposited on a silicon substrate (not shown)
A trench having a depth of 0.75 μm and a width of 0.6 μm is formed in the interlayer insulating film 11 made of
After a TiN barrier metal layer 12 having a thickness of, for example, 50 nm is formed by a method, a Zn seed layer 13 having a thickness of, for example, 100 nm is formed by a CVD method. Therefore, the width of the opening which is the unfilled portion of the trench after film formation is 0.3 μm (= 0.6 μm−2 × 0.05 μm−2).
× 0.1 μm).

Next, as shown in FIG. 4B, the silicon substrate was immersed in an ordinary copper sulfate-based Cu plating solution contained in a plating tank, the anode side was set to a negative value, and a reverse current of 100 mA / cm ² was applied. Is flowed for 20 msec, and a part of the Zn seed layer 13 is dissolved by a reaction of Zn → Zn ²⁺ + 2e.

Next, with the anode side being positive, a forward current of 10 mA / cm ² was passed for 20 msec, and Zn ²⁺ + 2e → Zn and
A Zn—Cu alloy seed layer 14 is formed by a reaction of Cu ²⁺ + 2e → Cu.

Subsequently, a forward direct current is applied to form a Cu plating layer 15 on the Zn—Cu alloy seed layer 14 by a reaction of Cu ²⁺ + 2e → Cu, and the trench is buried. .

Finally, although not shown, a chemical mechanical polishing method based on alumina powder was used as a slurry.
200-300 g / cm ² , preferably 250 g / cm ²
With a polishing pressure of 50 to 100 rotations / minute (rpm)
m), preferably at 50 rev / min, polished for 1-2 minutes, C
u plating layer 15, Zn—Cu alloy seed layer 14, Zn seed layer 13, and unnecessary portions of TiN barrier metal layer 12, that is, Cu plating layer 15 deposited above the height of the trench provided in interlayer insulating film 11. Then, the TiN barrier metal layer 12 is removed to form a buried Cu embedded wiring layer.

As described above, in the first embodiment of the present invention, first, Zn is used, which has good adhesion to the TiN barrier metal layer 12 which is different from Cu to be plated, and is lower than Cu. After the Zn seed layer 13 is formed, a part of the Zn seed layer 13 is removed by a reverse electric field to remove Zn.
Since the Cu alloy seed layer 14 is formed, the adhesion is improved as compared with the case where the Cu plating layer 15 is formed directly on the Zn seed layer 13.

When a Zn—Cu alloy seed layer 14 is formed, a forward pulse current is used.
Compared with the case of using a direct current, the Zn—Cu alloy seed layer 1
In-plane distribution of the composition No. 4 can be made uniform.

Next, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6. First, referring to FIG. 5, the application of the second embodiment of the present invention will be described. A pulse waveform diagram of a current will be described. In FIG. 5, SiO ₂
On the wafer, a thickness of 100 is formed via a TiN barrier metal layer.
After forming a Pt auxiliary electrode having a thickness of 100 nm and a Zn seed layer having a thickness of 100 nm, a substrate cut into an area of 2 cm × 2 cm was used as a sample, and a normal copper sulfate-based C was placed in a plating bath.
The experiment was conducted by accommodating 200 cc of the u plating solution.

Referring to FIG. 5, first, in the seed layer dissolving step, for example, 200 m
After flowing a reverse current of A / cm ² for 100 ms to dissolve all of the Zn seed layer, a forward current of 10 mA / cm ² is applied for 2 seconds, and then a reverse current is passed so that the current value gradually decreases. At the same time, the application time was adjusted so that the integrated current amount was the same as the integrated current amount of the reverse current pulse.
A forward current of 0 mA / cm ² is applied,
A Zn—Cu alloy seed layer is formed by repeating 30 cycles, for example, 10 cycles.
Form a plating layer.

As described above, in the second embodiment of the present invention, since the Pt auxiliary electrode is formed, it is possible to form the Zn—Cu alloy seed layer even if the entire Zn seed layer is dissolved. Become. In the case of the first embodiment, when the Zn seed layer is completely dissolved, the Zn layer, the Zn—Cu alloy layer, or the Cu layer is applied even when a forward pulse electric field is applied. Could not be produced.

Next, referring to FIG. 6, a second embodiment of the present invention in which the plating step shown in FIG. 5 is applied to the formation of a Cu embedded wiring layer.
The plating step of the embodiment will be described. Referring to FIG. 6A, first, SiO ₂ deposited on a silicon substrate (not shown)
A trench having a width of 0.6 μm is formed in an interlayer insulating film 11 made of, and a TiN barrier metal layer 12 having a thickness of, for example, 50 nm is formed in the trench by a CVD method. However, a Pt auxiliary electrode 22 having a thickness of, for example, 100 nm is formed, and then a Zn seed layer 13 having a thickness of, for example, 100 nm is formed using a CVD method. Therefore, the width of the opening which is the unfilled portion of the trench after film formation is 0.1 μm (= 0.6 μm−2 × 0.05).
μm−2 × 0.1 μm−2 × 0.1 μm).

Next, as shown in FIG. 6 (b), the SiO ₂ wafer 11 is immersed in a copper sulfate-based ordinary Cu plating solution contained in a plating bath, the anode side is made negative, and the reverse current of 100 mA / cm ² is applied. A directional current is passed for 100 ms, and the entire Zn seed layer 13 is dissolved by the reaction of Zn → Zn ²⁺ + 2e.

Next, with the anode side being positive, a forward current of 10 mA / cm ² was passed for 2 seconds, and Zn ²⁺ + 2e → Zn and Cu ²⁺
+ 2e → Zn—Cu alloy seed layer 1 by reaction of Cu
4, and then, as shown in FIG. 5, a reverse current is caused to flow again so that the current value gradually decreases, and an application time is set so that the integrated current amount becomes the same as the integrated current amount of the reverse current pulse. Is adjusted, a forward current of 10 mA / cm ² is applied, and this cycle is repeated for 10 to 30 cycles, for example, 10 cycles, to form the Zn—Cu alloy seed layer 14.

Subsequently, a forward direct current is applied to form a Cu plating layer 15 on the Zn—Cu alloy seed layer 14 by a reaction of Cu ²⁺ + 2e → Cu, and the trench is buried. .

Finally, although not shown, the first
As in the embodiment, alumina powder is used as a slurry.
200-300 g /
cm ^Two, Preferably 250 g / cm^TwoSpin at the polishing pressure of
Several 50-100 rotations / minute (rpm), preferably 50 rotations
/ Minute, polishing for 1 to 2 minutes, Cu plating layer 15, Zn-
Cu alloy seed layer 14, Zn seed layer 13, Pt auxiliary electrode
Unnecessary portions of the pole 22 and the TiN barrier metal layer 12,
That is, SiO_TwoMore than the height of the trench provided in the wafer 11
Plated layer 15 to TiN barrier metal layer deposited on
12 is removed to form a buried Cu buried wiring layer.

As described above, in the second embodiment of the present invention, since the Zn seed layer 13 is formed via the Pt auxiliary electrode 22, the Zn seed layer 13 is dissolved in the step of dissolving the Zn seed layer 13. 13-
Since the formation of the Cu seed layer 14 becomes possible, the setting of the reverse electric field and the current amount becomes easy.

In the second embodiment of the present invention, positive and negative pulse currents are applied alternately and in such a manner that the current value gradually decreases. And the dissolving process is repeated after forming the seed layer, and the film thickness distribution with less irregularities is more uniform than in the first embodiment. The Zn—Cu alloy seed layer 14 can be formed.

The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations and conditions described in each embodiment, and various changes can be made. For example, the amount of current applied and the duration of application in each of the above embodiments are arbitrary, and may be set according to the thickness of the Zn seed layer and the thickness of the generated Zn—Cu alloy seed layer.

In the first embodiment, the reverse electric field to be applied is only the first pulse.
The reverse electric field which gradually decreases as shown in FIG. 5 may be periodically applied. On the other hand, also in the second embodiment using the Pt auxiliary electrode, the pulse shown in FIG. An electric field may be applied.

In each of the above embodiments, C
Although described as the step of forming the u-buried wiring layer, it is not limited to only the step of forming the Cu-buried wiring layer.
The present invention is also applied to the case of forming in another step.

Further, in each of the above embodiments, the buried wiring layer is formed by the Cu plating layer. However, the embedding wiring layer is not limited to the pure Cu plating layer. Any Cu-based alloy may be used, for example,
A Cu-Zn alloy may be used.

In each of the above embodiments, the Zn seed layer is used as the first seed layer.
The present invention is not limited to the seed layer, and may be a material having better adhesion to the TiN barrier metal layer than Cu and a metal lower than Cu, for example, Fe.

In each of the above embodiments, TiN is used as the barrier metal. However, the present invention is not limited to TiN. For example, TaN or WN may be used.

In the second embodiment, Pt is used as the auxiliary electrode. However, the present invention is not limited to Pt. At least the first seed layer (M) can be formed by plating. Any metal can be used.
If the seed layer and Cu are both metals that can be formed by plating, an M-Cu alloy seed layer can be formed. Such a metal that replaces Pt is Ag or A
u is preferred.

[0065]

According to the present invention, the metal constituting the first seed layer is replaced with Cu by the electric field pulse method. Therefore, the seed layer is formed using the same plating solution and Cu is removed.
Since the system plating layer can be formed, the device configuration is simplified, and a Cu-based buried wiring having excellent adhesion can be formed. In addition, the material of the seed layer and the waveform of the applied pulse electric field can be reduced. The selection and control can improve the electrical conductivity, mechanical strength, heat resistance, and the like of the Cu-based buried wiring, and as a result, the reliability of a semiconductor integrated circuit device having a highly integrated and miniaturized wiring layer It greatly contributes to the improvement of the cost or cost reduction.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is a pulse waveform diagram of an applied current according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a composition of an alloy seed layer according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a plating step according to the first embodiment of the present invention.

FIG. 5 is a pulse waveform diagram of an applied current according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a plating step according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a step of forming a seed layer using cementation.

FIG. 8 is an explanatory diagram of a DC electrolytic plating step.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 barrier metal 2 seed layer 3 power supply 4 plating tank 5 plating solution 6 anode 7 seed layer 8 Cu-based plating layer 11 interlayer insulating film 12 TiN barrier metal layer 13 Zn seed layer 14 Zn-Cu alloy seed layer 15 Cu plating layer 16 melting Part 17 Cu seed layer 18 Cu seed layer 19 Zn-Cu alloy seed layer 20 Cu seed layer 21 Zn-Cu alloy seed layer 22 Pt auxiliary electrode 31 TiN barrier metal layer 32 seed layer 33 substitution tank 34 Cu substitution liquid 35 Cu seed layer 36 Plating tank 37 Cu plating solution 38 Power supply 39 Anode 40 Cu plating layer

Claims (5)

[Claims] 1. A Cu alloy layer having a composition different from that of the Cu-based plating layer between a barrier metal and a Cu-based plating layer made of either Cu or an alloy containing Cu as a main component. Semiconductor device having a Cu-based embedded wiring. 2. A step of providing at least one of a groove and a hole in the insulating film, a step of forming a barrier metal on the surface of the insulating film and an exposed surface of the groove or the hole, and a step of forming a metal other than Cu on the barrier metal. Forming a seed layer by using an electric field pulse composed of a reverse direction and a forward direction.
Or Cu made of any of alloys containing Cu as a main component
A pulse plating method for a Cu-based embedded wiring, comprising a step of forming a plating layer made of a system conductor by electroplating. A step of forming at least one of a groove and a hole in the insulating film; a step of forming a barrier metal on the surface of the insulating film and an exposed surface of the groove or the hole; Forming an insoluble auxiliary electrode in a plating bath of a Cu-based conductor made of any of the following alloys; forming a first seed layer made of a metal other than Cu on the auxiliary electrode; A method of forming a plating layer made of a Cu-based conductor by electroplating using an electric field pulse having a forward direction and a forward direction. 4. In the electroplating step, at least a part of the first seed layer is dissolved by a pulsed electric field applied in a reverse direction first, and then a second seed layer is formed by a pulsed electric field in a forward direction. 4. The method according to claim 2, wherein a plating layer made of a Cu-based conductor is formed by electroplating using a forward pulsed electric field. 5. The method according to claim 1, wherein the backward integrated current amount and the forward integrated current amount of the pulse electric field applied in the step of forming the second seed layer are equal, or the backward integrated current amount flowing in one cycle is equal to the forward integrated current amount. 5. The method according to claim 4, wherein the integrated current amount is made equal and the reverse integrated current amount is sequentially reduced.