JP2001229685A - Semiconductor memory and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory and its driving method in which data are never destroyed by read-out, and neither a selection transistor for read-out nor element separation for write-in/erasing is required. SOLUTION: In a first transistor of which has a gate electrode provided with a ferroelectric film, the gate is connected to a word line, the drain is connected to a bit line, the source is connected to a source line, and the drain and the bit line or the source and the source line are connected through a diode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-destructively readable semiconductor memory device which is a field-effect transistor using a ferroelectric thin film as a gate and a method of driving the same.

[0002]

2. Description of the Related Art A field effect transistor (hereinafter referred to as a ferroelectric FET) having a ferroelectric film on a gate is known.
If the ferroelectric film can be polarized upward or downward, and the threshold voltage of the ferroelectric FET can be set to one of two different values corresponding to the two polarization states, this state Is retained, that is, stored as long as the polarization of the ferroelectric film is retained.

When a word line is connected to the gate electrode, a bit line is connected to the drain, and a source line is connected to the source of the ferroelectric FET, a memory cell is formed as an element at each intersection of the matrix array.

FIG. 4 shows a matrix array of a semiconductor memory device having a plurality of memory cells.

In FIG. 4, M11, M12, M21,
And M22 are ferroelectric FETs constituting the memory cells C11, C12, C21 and C22 at the respective intersections of the matrix array, and W1 is the W11 of M11 and M12.
2 is a word line connected to the gates of M21 and M22, S1 is M11 and M12, S2 is M21 and M2
The source line connected to the second source, B1, is M11 and M11.
21 is a bit line connected to the drains of M12 and M22, respectively.

[0006] The logic state of a memory cell is identified by whether the ferroelectric FET of the selected memory cell is on or off. Whether the ferroelectric FET is on or off depends on whether or not the channel 7 below the gate 10 of the ferroelectric FET is conducting.
When a certain voltage is applied to the gate electrode 10 of T, the ferroelectric FET is turned on in one state and turned off in the other state according to the two polarization states of the ferroelectric film. A gate voltage exists between two different threshold voltages. Therefore, when this gate voltage is applied to the gate electrode, for example, the logic of the ferroelectric FET in the on state is promised to be "1" and the logic of the ferroelectric FET in the off state is promised to be "0".

Under this condition, for example, to know the logic held in memory cell C11 in FIG.
1 to a low voltage, and then the source line S1
After raising the voltage to the read voltage, the word line W1 is moved to the middle between the two threshold voltages. if,
If the state of the ferroelectric substance of the gate of M11 is a state of a low threshold voltage, that is, "1", M11 is in an on state,
A current flows from S1 to B1, B1 is charged, and the voltage of B1 increases. On the other hand, if the state of the ferroelectric material of the gate of M11 is a state of a high threshold voltage, that is, “0”, M11 is in an off state and B1 is not charged and B1 is not charged.
The voltage of 1 remains low. Therefore, bit line B1
The logic state held by the desired memory cell can be determined from the level of the voltage.

[0008]

However, when a voltage is applied to the word line for each read, even if the value is between the two threshold voltages of the polarization of the ferroelectric film described above,
A voltage is gradually applied to the ferroelectric film of the gate in the “0” state in a direction approaching the “1” state.
As a result, the state of the ferroelectric film of all the gates in the “0” state connected to the word line to which the read voltage has been applied approaches the “1” state for each read, and gradually changes between “0” and “1”. There has been a problem of disturbing which makes it difficult to determine.

To avoid this problem, a ferroelectric FET
Is set to either the enhancement type or the depletion type depending on the polarization state of the ferroelectric film, and each of them is made to correspond to two logical values, thereby enabling reading without applying a voltage to the word line. However, since the dielectric ferroelectric FET is always "1" even when the gate voltage is zero, that is, normally on, if the logic held in the non-selected memory cell is "1",
A current path from the bit line to the source line is formed via the unselected memory cells, and there is a problem that the potential of the bit line changes depending on the state of the unselected memory cells. Therefore, as disclosed in, for example, JP-A-8-139286, it is necessary to add a transistor for connecting only the transistor of the selected memory cell to the memory cell.

In order to write data only in the transistor of an arbitrary selected memory cell, for example, as disclosed in JP-A-5-206411 or JP-A-5-205487, It is also necessary to add a transistor for selection.

Here, a first transistor having a ferroelectric film at its gate is connected to a selected memory cell and a word line and a bit line to a selection transistor TB, respectively.
FIG. 5 shows a memory cell including a TP.

In FIG. 5, M is a first transistor provided with a ferroelectric film at a gate serving as a memory cell at each intersection of a matrix array, and the gate of which is provided with a program for data writing via a second transistor TP. Connected to line WP. The gate of the second transistor TP is connected to a selection line BP arranged in parallel with the bit line B. TB is the drain of the first transistor and bit line B
And a gate thereof is connected to the word line W. The source line S is connected to the source of the first transistor M.

In order to read the logic state of a memory cell with the above configuration, whether the transistor of the selected memory cell is of the enhancement type or the division type, that is, whether the transistor of the selected memory cell is on or off when the potential of WP is zero, May be identified. Here, the selection of the memory cell is performed by setting the word line W to a high voltage and activating the third transistor TB.

On the other hand, in order to erase the data of the selected memory cell, that is, write "0", the potential of the substrate of the selected first transistor is changed by the polarization of the ferroelectric film with respect to that of the program line WP. Needs to be increased to a voltage at which the voltage reverses. For that purpose, the substrate of the first transistor must be separated from the first transistor of the memory cell not selected by the well 30. Therefore, when the wells of the first transistors are formed so as to be common along the word line direction, the word line WP is set to a low voltage, and the selection line BP of each memory cell along the word line is set to a high voltage for gate selection. Transistor TP
Is turned on, the gate of the first transistor M is set to a low voltage, and then the well 30 is set to a high voltage to a potential at which the polarization of the ferroelectric film of the gate of the transistor M is inverted. As a result, memory cells having a common well in the word line direction are collectively erased and "0" is written in each memory cell.

In order to selectively write data to an arbitrary memory cell from which data has been erased, all the lines are set to a low voltage, and then the selection line BP of the selected memory cell is set to a high voltage, and the gate selection transistor TP is turned on. After turning on, the program line W connected to the selected memory cell through this
By setting P to a high voltage, “1” is written to the gate of the first transistor M.

As described above, in the configuration as shown in FIG. 4, in the read operation, the disturbance of the word line causes
There has been a problem that it is difficult to determine the readout of the held data. According to the configuration as shown in FIG. 5, the problem of disturb can be avoided. However, the memory cell requires three transistors, and the substrate of the first transistor of each memory cell has at least an adjacent word line or bit line. If the memory cell is not electrically isolated by the substrate and well of the first transistor of the memory cell, selective writing cannot be performed, and the size of the memory cell is several times as large as that of a one-transistor / one-capacitor type memory cell. There was a disadvantage that it became larger.

According to the present invention, there is provided a semiconductor memory device in which a matrix array is constituted by memory cells comprising a small number of elements, in which no data destruction or disturbance is caused in reading, erasing, or chipping of data in a memory cell. The present invention provides a method for driving the same.

[0018]

According to a first aspect of the present invention, there is provided a first transistor having a ferroelectric film on a gate, wherein the gate of the first transistor is a word line, and the drain is a drain. In the bit line, the source is connected to the source line, and a diode is provided between the drain and the bit line or between the source and the source line. With this configuration, when judging the conduction state of the memory cell selected for reading by the diode, the unselected memory cell receives or receives charges from the bit line or the source line connected to the unselected memory cell. Since the outflow is prevented, a selection transistor for connecting the memory cell to be read and the bit line can be eliminated.

According to a second aspect of the present invention, in the first transistor having a gate provided with a ferroelectric film, the gate of the first transistor is connected to a word line via a second transistor, and the drain is connected to a bit line. And the source is connected to a source line via a diode arranged in a forward direction from the source to the drain, and the gate of the second transistor is connected to a program line to form a memory cell in a matrix. It was done. With this configuration, charge is prevented from flowing out of the bit line connected to the memory cell selected for reading by the diode to the source line via the non-selected memory cell. Can be omitted.

According to a third aspect of the present invention, the first transistor is either an enhancement type or a division type depending on the polarization state of the ferroelectric film, and each of the first transistors has one of two logical values. It corresponds to crab. With this configuration, data can be read without applying a voltage to the gate of the first transistor.

According to a fourth aspect of the present invention, in the method of driving a semiconductor memory device, the gate of the first transistor having a ferroelectric film on the gate is connected to the word line via the second transistor.
The drain is connected to the bit line, the source is connected to the source line via a diode arranged in the forward direction from the source to the drain, and the gate of the second transistor is formed by connecting the memory cells connected to the program line in a matrix. In reading the selected memory cell in the semiconductor memory device having the structure described above, the bit line connected to the selected memory cell is discharged to a low potential in advance, and then the source line connected to the memory cell is set to the high potential. Thus, the potential of the bit line according to the logic state of the first transistor of the selected memory cell is obtained. With this configuration, it is possible to read only the selected memory cell.

According to a fifth aspect of the present invention, in the method of driving a semiconductor memory device, the gate of the first transistor provided with a ferroelectric film in the gate is connected to the word line via the second transistor.
The drain is connected to the bit line, the source is connected to the source line via a diode arranged in the forward direction from the source to the drain, and the gate of the second transistor is formed by connecting the memory cells connected to the program line in a matrix. In erasing a selected memory cell in the semiconductor memory device configured as described above, the bit line and the source line connected to the selected memory cell are set to a low potential, the program line is set to a high potential, and the gate of the first transistor is set. And the word line are electrically connected via the second transistor, and then the potential of the word line and the potential of the bit line connected to the selected memory cell are changed to the ferroelectricity of the gate of the first transistor. A high voltage higher than the polarization of the body film is inverted, and then a word line connected to the selected memory cell It is characterized in that an erased state the first transistor by a potential to a low voltage.

With this configuration, the first transistor of the selected memory cell can be in the erased state, so that it is not necessary to electrically separate the substrate of the first transistor from other memory cells.

According to a sixth aspect of the present invention, in the method of driving a semiconductor memory device, the gate of the first transistor having a ferroelectric film in the gate is connected to the word line via the second transistor. , The drain is connected to the bit line, the source is connected to the source line via a diode arranged in the forward direction from the source to the drain, and the gate of the second transistor is a matrix of memory cells connected to the program line. In writing to a selected memory cell in a semiconductor memory device configured in such a manner, after erasing the selected memory cell, the bit line and the source line connected to the memory cell are set to a low potential, and the program line is set to a high potential. As a potential, the gate of the first transistor and the word line are electrically connected via the second transistor. After that, the potential of the word line connected to the memory cell is set to a voltage higher than the voltage at which the polarization of the ferroelectric film of the gate of the first transistor is inverted. It is characterized by being in a state.

With this configuration, the first transistor of any selected memory cell can be changed from the erased state to the written state.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows an embodiment of a memory cell forming a matrix array in a semiconductor memory device according to the present invention. In FIG. 1, in this memory cell, a word line W is connected to a gate of a field-effect first transistor M having a ferroelectric film at a gate via a second transistor TP. The bit line B is connected to the drain, the source line S is connected to the source of the first transistor M via the diode D, and the program line BP is connected to the gate of the second transistor TP. .

In the semiconductor memory device according to the present embodiment, it is assumed that the transistor M is either an enhancement type or a division type depending on the polarization state of the ferroelectric film of the gate. Here, the data held in the first transistor M is “0” if M is an enhancement type, and “1” if M is a depletion type.

In the configuration of FIG. 1, the first transistor M
First, to read the data held by the word lines W,
All of the source line S, the program line BP, and the bit line B are kept at a low potential such as a ground potential, and then a read voltage, for example, a power supply voltage of a memory device is applied to the source line S. At this time, if the first transistor M holds “0”, no current flows from the source line S to the bit line B because the first transistor M is non-conductive, and the potential of the bit line B is low. Remains. However, if the first transistor M holds “1”, a current flows from the source line S to the bit line B because the first transistor M is conductive, and the potential of the bit line B rises. Thus, whether or not the potential of the bit line rises is detected by the sense amplifier (not shown) connected to the bit line, and the data held in the memory cell is “0” or “1”. Is determined.

FIG. 2 shows the memory cells according to the present embodiment arranged in a 2 × 2 matrix. In FIG. 2, M11, M12, M21, and M22 are memory cells C11, C12,
A field-effect type first transistor having ferroelectric films constituting C21 and C22, respectively, where W1 is M1
1 and M12, W2 is a word line connected to the gates of M21 and M22, respectively, and S1 is S11 of M11 and M12.
2 is a source line connected to the sources of M21 and M22, B
1 is a bit line connected to the drains of M11 and M21, and B2 is a bit line connected to the drains of M12 and M22. Also, TP
11 and TP12 are second transistors connected between the gates of M11 and M12 and the word line W1, respectively, and TP21 and TP22 are second transistors connected between the gates of M21 and M22 and the word line W2, respectively. And BP2 are program lines connected to the gates of TP11 and TP21 and TP12 and TP22, respectively. D11, D12
Are between M11 and M12 and the source line S1, respectively.
D21 and D22 are diodes connected between M21 and M22 and the source line S2, respectively.

A method of driving a semiconductor memory device in which a plurality of memory cells are arranged in a matrix will be described. In the reading, erasing, and writing of each memory cell, the driving method of each element is as described above. In the simple 2 × 2 matrix array shown in FIG. 2, depending on the combination of data held in each cell, The operation of the semiconductor memory device of the present invention will be described below.

In FIG. 2, it is assumed that the data held by memory cell C11 is "1". This memory cell C11
, First, the word lines W1, W2,
All the source lines S1 and S2, the program lines BP1 and BP2, and the bit lines B1 and B2 are kept at a low potential such as a ground potential, and then a read voltage is applied to the source line S1, for example, a power supply voltage of a memory device. Is applied. At this time, since the first transistor M11 holds data "1", a current flows from the source line S1 to the bit line B1, and the potential of the bit line B starts to rise. At this time, if the unselected memory cell C21 holds data "1", the first transistor M21 is conductive, but the diode D21 is connected to the bit line B.
1 prevents the current from flowing to the source line S2, the data in the memory cell C21 is not read, and the bit line B
As for No. 1, the potential is surely increased by charging the selected memory cell C11 from the source line S1. By detecting the increased voltage of the bit line B1 with a sense amplifier (not shown) connected to the bit line B1, it is possible to reliably determine that the data held in the selected memory cell C11 is "1".

Therefore, according to the present invention, the unselected memory cell C21 is not read, and the selected memory cell C21 is not read.
Only 11 can be read reliably.

Next, the case where data held in the first transistor M is erased ("0" is written) will be described with reference to FIG.

First, the bit line B connected to the memory cell
After the source line S is set at a low potential and the program line BP is set at a high potential, the gate of the first transistor and the word line are electrically connected via the second transistor TP, and then the word connected to the memory cell is turned on. The potential of the line W and the potential of the bit line B are simultaneously set to the erase voltage. here,
If M holds "1", the potential of the channel 20 becomes the same as that of the bit line B because the channel 20 of this transistor is conductive. Thereafter, when the potential of the word line connected to the first transistor M is set to a low voltage, a potential difference between the channel 20 and the gate electrode 21 of M becomes more than necessary for inversion of the polarization of the ferroelectric film. The data "1" is rewritten to the data "0" by the inversion of the gate, and the data erasure is completed. On the other hand, if M holds “0”, the channel 20 is conductive, and there is almost no potential difference between the channel 20 and the gate electrode 21. Also, even if there is a potential difference,
Since the gradient is in the direction of making the polarization “0”, the data of the memory cell keeps “0”, that is, remains erased.

Next, in erasing data when the memory cells are arranged in a 2 × 2 matrix, as shown in FIG. 2, for example, the program line BP1 is set to a write voltage or higher, and then the word line W1 is set. And W2 and the bit line B1 are simultaneously set to the erase voltage. Thereafter, when the word lines W1 and W2 are lowered to the ground potential, "0" is written to the memory cells C11 and C21 at once.

Therefore, according to the present invention, it is possible to eliminate the need for an isolation structure for erasing data by increasing the substrate potential only by a desired selected portion, which has been conventionally required.

Next, a case where data is written to the first transistor M from which data has been erased will be described with reference to FIG.

First, the bit line B and the source line S connected to the selected memory cell are set to a low potential, the program line BP is set to a high potential, and the gate of the first transistor M and the word line W are set to the second transistor TP. , And the potential of the word line connected to the memory cell is set to the write voltage, thereby making the gate electrode 21
By causing a potential difference more than necessary due to the polarization inversion of the ferroelectric film between the channel and the channel 20, the data of the selected memory cell can be rewritten from "0" to "1".

Next, in erasing data when the memory cells are arranged in a 2 × 2 matrix, as shown in FIG. 2, the bit line B and the source line S are set to a low potential, and the program line BP is set to a high potential. After the gate of the first transistor M and the word line W are electrically connected via the second transistor TP as the potential, the potential of the word line connected to this memory cell is set to the writing voltage, whereby the gate electrode 21 is turned on. By causing a potential difference more than necessary due to the polarization inversion of the ferroelectric film between the channel and the channel 20, the data of the selected memory cell can be rewritten from "0" to "1".

Further, the first and second embodiments are described.
Thus, it is also possible to adopt a configuration in which the substrates of the memory cells are separated, and a configuration in which the arrangement direction of the bit lines and the source lines is parallel or orthogonal to the word line direction, respectively.

In the first embodiment, as shown in FIG.
In the first transistor having a ferroelectric film at the gate, the gate of the first transistor is connected to the word line via the second transistor, the drain is connected to the bit line, and the source is connected from the source to the drain in a forward direction. FIG. 3 shows a configuration in which each diode is connected to a source line via a diode disposed in the same direction. However, as shown in FIG. The same effect as described in the present embodiment can be obtained even in the case where the control is performed directly without using the two transistors.

[0043]

As described above, in the structure of the memory cell of the present invention, the source is connected via the non-selected memory cell to the bit line connected to the memory cell selected for reading by the diode arranged in the memory cell. Since charge can be prevented from flowing out to the line, a selection transistor for connecting the memory cell to be read and the bit line is not required. Further, since the voltage of the bit line is blocked by this diode, if the transistor holding data is in the state of "1", the potential of the channel of the transistor and the bit line are set to the same potential. By creating a potential difference between the bit line and the word line, "1" can be rewritten to "0". This operation can be performed collectively for memory cells connected to the same bit line. As a result, there is no need for an isolation structure for erasing data by raising the substrate potential by a desired selected portion.

Further, since a field-effect transistor having a gate provided with a ferroelectric film for holding data of a memory cell is either an enhancement type or a division type, a voltage is not applied to the gate. Data can be read. Therefore, the gate polarization state does not change due to the application of the read voltage.

As described above, according to the present invention, there is no data destruction (disturb) due to reading, no selection transistor for reading is required, and element isolation for writing and erasing is not required. And a semiconductor memory device capable of reading, erasing, and writing, and a driving method thereof can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a diagram showing a circuit configuration of a semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a diagram showing a circuit configuration of a semiconductor memory device according to one embodiment of the present invention;

FIG. 4 is a diagram showing a circuit configuration of a conventional semiconductor memory device;

FIG. 5 is a diagram showing a circuit configuration of a conventional semiconductor memory device;

[Explanation of symbols]

 20 channel 21 gate electrode 30 well

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Nobuyuki Moriwaki 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. (72) Inventor Hiroshige Hirano 1-1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics In-house F term (reference) 5B025 AA07 AB03 AC01 AD03 AD04 AD08 AE08 5F001 AA17 AD52 AE02 AE03 5F083 FR05 GA09

Claims (6)

[Claims] When connecting a gate of a transistor having a ferroelectric film to a word line, a drain to a bit line, and a source to a source line, a transistor is connected between a drain and a bit line or between a source and a source line. Storage device with a diode connected to it. 2. A first transistor having a ferroelectric film as a gate, a gate disposed in a word line, a drain disposed in a bit line, and a source disposed in a forward direction from a source to a drain via a second transistor. A semiconductor memory device in which a plurality of memory cells each connected to a source line via a connected diode and a gate of the second transistor connected to a program line are arranged in a matrix. 3. The first transistor is either an enhancement type or a division type depending on the polarization state of the ferroelectric film, and each of the first transistors corresponds to one of two logical values. The semiconductor memory device according to claim 2. 4. A first transistor having a ferroelectric film as a gate, a gate disposed in a word line, a drain disposed in a bit line, and a source disposed in a forward direction from a source to a drain via a second transistor. Of the selected memory cell in a semiconductor memory device in which a plurality of memory cells configured by connecting the gates of the second transistors to the program lines via a diode are connected in a matrix. In reading, a bit line connected to the selected memory cell is discharged to a low potential in advance, and then a source line connected to the memory cell is set to a high potential, so that the first memory cell of the selected memory cell is discharged. A method for driving a semiconductor memory device that obtains a potential of a bit line according to a logic state of a transistor. 5. A first transistor having a ferroelectric film as a gate, a gate disposed in a word line, a drain disposed in a bit line, and a source disposed in a forward direction from a source to a drain via a second transistor. Of the selected memory cell in a semiconductor memory device in which a plurality of memory cells configured by connecting the gates of the second transistors to the program lines via a diode are connected in a matrix. In erasing, the bit line and the source line connected to the selected memory cell are set at a low potential, the program line is set at a high potential, and the gate of the first transistor and the word line are electrically connected via the second transistor. And the potential of the word line and the potential of the bit line connected to the selected memory cell are changed to the first transistor. The voltage of the ferroelectric film at the gate of the transistor is set to a high voltage at which the polarization is inverted, and then the potential of the word line connected to the selected memory cell is set to a low voltage, thereby setting the first transistor in the erased state. And a method for driving a semiconductor memory device. 6. A first transistor having a gate provided with a ferroelectric film, a gate disposed via a second transistor on a word line, a drain disposed on a bit line, and a source disposed in a forward direction from a source to a drain. Of the selected memory cell in a semiconductor memory device in which a plurality of memory cells configured by connecting the gates of the second transistors to the program lines via a diode are connected in a matrix. In writing, after erasing the selected memory cell, the bit line and the source line connected to the memory cell are set to a low potential, the program line is set to a high potential, and the gate and the word line of the first transistor are connected to the second line. After being electrically connected through the second transistor, the potential of the word line connected to the memory cell is changed to the first potential. A method for driving a semiconductor memory device in which the first transistor is changed from an erased state to a written state by setting a voltage higher than the voltage at which the polarization of the ferroelectric film of the gate of the transistor is inverted.