JP2001223680A - Stuffing control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simple stuffing control circuit that its circuit scale can be reduced. SOLUTION: The stuffing control circuit consists of a packet insert control means, having a write control circuit 1, a transmission parameter setting circuit 4, a test packet flag generating circuit 5, and a read control circuit 3, of a FIFO 2 and of a null packet insert circuit 6. The read control circuit 3 reads digital data 29 from the FIFO 2, according to a frame pattern 28 generated by the test packet flag generating circuit 5 and allows a null packet insertion circuit 6 to insert valid null packets, so that the number of valid packets reaches a number specified in compliance with a prescribed transmission standard.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a stuffing control circuit, and more particularly to a stuffing control circuit used to convert packetized digital data from a data rate of an output device to a data rate specified by a predetermined transmission standard. .

[0002]

2. Description of the Related Art Generally, the transmission speed of digital data between digital data processing devices is lower than the data transfer speed in a digital data processing device that receives and processes the digital data. A speed conversion circuit for performing speed conversion of the received digital data is provided. By the way, in the transmission of digital data, a packet obtained by dividing the digital data by a predetermined number of bytes, a frame composed of a plurality of packets, and a superframe composed of a plurality of frames (hereinafter referred to as SFP) are used as a unit. In these cases, not only do the received packets match the data rate in the digital data processor,
The packets need to be arranged in a predetermined format.
For this reason, the transmission speed (data rate) of a packet is defined according to each transmission parameter.

[0003] This speed conversion will be described with reference to FIG. FIG. 5 shows a timing chart when speed conversion is performed by receiving an SFP composed of n packets. When the received data is transmitted to a first-in first-out memory (hereinafter, referred to as FIFO), The speed conversion is performed by writing the data at the data rate and reading the written data in the order in which the data was written at the data rate in the receiving apparatus. In the drawing, write data 1 indicates a case where the data rate of a packet written to the FIFO is specified, and read data 1 indicates a packet arrangement in the SFP whose speed has been converted in this case. The write data 2 is a FIFO
Shows the case where the data rate of the packet written in the SFP is lower than the prescribed one, and the read data 2 shows the packet arrangement in the SFP whose speed has been converted in this case.

In FIG. 5, when the number of valid packets in one received SFP is n, if the data rate at the time of reception is a prescribed one, as shown in write data 1, the FIFO Since the writing is completed within the readable period of one SFP, as shown in the read data 1, the SFP after the speed conversion contains n valid packets. However, when the data rate is lower than the prescribed one, the writing to the FIFO does not end within the readable period of one SFP as shown in the write data 2, so that as shown in the read data 2, Only n-1 valid packets can be accommodated in the SFP after the speed conversion.

[0005] Therefore, if the data rate from the transmitting device is lower than the prescribed one, the number of packets received is insufficient to form a predetermined format, and the receiving device can reduce the number of packets. It needs to be supplemented (stuffed). Conventionally, this stuffing is performed by providing a memory for adjusting a data rate when performing processing based on a predetermined format.

[0006]

However, the conventional stuffing method has a problem that the circuit scale becomes large, for example, a memory for storing data of at least one SFP is required. SUMMARY OF THE INVENTION An object of the present invention is to provide a simple stuffing control circuit capable of reducing the circuit scale.

[0007]

SUMMARY OF THE INVENTION A stuffing control circuit according to the present invention is provided with an effective null packet so that digital data having a frame structure composed of a plurality of packets includes the number of effective packets specified by a predetermined transmission standard. Is a circuit that inserts
Digital data can be written and read simultaneously at different speeds, and a memory that reads in the order in which the digital data is written and a valid null packet are generated, and a valid null packet is added to the digital data read from the memory. Packet insertion means for inserting, and packet insertion control means for controlling the packet insertion means while reading digital data from the memory to insert valid null packets so that the number of valid packets becomes the number specified by the transmission standard. , Digital data is written to the memory at the transmission rate of the digital data, and is read from the memory at the transmission rate specified by the transmission standard.

[0008] In this case, one configuration example of the packet insertion control means is to input a clock signal corresponding to a transmission rate specified by a transmission standard to a memory, and to convert digital data written in the memory based on a predetermined frame pattern. It is configured to read and convert the transmission rate of the input digital data to the transmission rate specified by the transmission standard. One configuration example of the packet insertion control means includes a write control circuit that controls writing to a memory based on input digital data, counts the number of packets written to the memory, and generates write count data,
A transmission parameter setting circuit that outputs a transmission parameter specified by a transmission standard; a test packet flag generation circuit that generates a frame pattern from the transmission parameter; and a memory read and valid null packet based on the frame pattern and the number of write times data. And a read control circuit for controlling the insertion of the data.

One configuration example of the test packet flag generation circuit is configured to generate a frame pattern in which valid packets are arranged at an arbitrary position. In one configuration example of the read control circuit, at least one difference between the number of packets written to the memory and the number of packets read from the memory is defined at a position where a valid packet is to be arranged based on the frame pattern. Data is read from the memory when the number is less than the number of valid packets, and when the difference is 0, a valid null packet is inserted. One configuration example of the packet insertion means generates an invalid null packet and a valid null packet for supplementing a packet that is insufficient due to the speed conversion, and inserts the invalid null packet and the valid null packet into the digital data read from the memory. It is configured to be.

Another example of the structure of the packet insertion control means is to count the number of digital data packets written in the memory and determine the number of valid packets deficient with respect to the number of valid packets specified by transmission parameters of a predetermined transmission standard. An input rate monitoring circuit for detecting and controlling the packet inserting means to insert a valid null packet so that the number of valid packets becomes the number specified by the transmission standard, and outputting a transmission parameter of the transmission standard to the input rate monitoring circuit. And a transmission parameter setting circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. First, a stuffing control circuit according to a first embodiment of the present invention will be described. The stuffing control circuit of this embodiment performs stuffing by writing to a FIFO at a transmission rate, and reading at a specified data rate after speed conversion. FIG.
Shows a first embodiment of a stuffing control circuit according to the present invention.
It includes a FIFO 2, a read control circuit 3, a transmission parameter setting circuit 4, a test packet flag generation circuit 5, and a null packet insertion circuit 6.

In this case, when the packet data (TS) 20 is input, the write control circuit 1 transmits a clock signal (TSCLK) 21 synchronized with the transmission speed of the packet data (TS) 20 and a write control signal 22. Generate and F
It outputs the packet data (TS) 20 to the FIFO 2 at a speed synchronized with the transmission speed. Also, F
The number of packets written to the IFO 2 is output to the read control circuit 3 as write number data 23. This FIF
O2 has a write control port, a write clock input port, a read control port, and a read clock input port, and can simultaneously perform writing and reading at different speeds. Transmission parameter setting circuit 4
Outputs the transmission parameter setting data 24 necessary for generating the frame pattern to the test packet flag generation circuit 5.

The test packet flag generation circuit 5 generates a frame pattern 28 for each SFP with packet flags of the number of packets specified by each parameter of the setting data 24 output from the transmission parameter setting circuit 4, Output to 3. The read control circuit 3 performs read control on the FIFO 2 based on the frame pattern 28 output from the test packet flag generation circuit 5, the write count data 23 output from the write control circuit 1, and the read count data generated by itself. A signal 25 and a clock signal (SYSTEM CLK) 26 synchronized with the system clock are output, and information for null packet insertion is generated to generate a null packet insertion circuit 6.
To output a null packet insertion signal 27.

The FIFO 2 has a clock signal (TSCLK) 2
1 and the write control signal 22, the packet data (TS) 20 is written at a speed synchronized with the transmission speed, and the read control signal 25 and the clock signal (SYSTEM CLK) 26 read the written data in the written order. It is. As a result, the packet data 29 whose speed has been converted to the system clock rate is output. The null packet insertion circuit 6 generates a valid null packet and an invalid null packet, and inserts a valid null packet into the packet data 29 output from the FIFO 2 based on the null packet insertion signal 27 output from the read control circuit 3. It performs stuffing and insertion of invalid null packets due to speed conversion.

In the stuffing control circuit of this embodiment, the insertion of a valid null packet and an invalid null packet accompanying stuffing and speed conversion can be performed by one null packet insertion circuit, so that the entire circuit configuration is simplified. The stuffing control circuit can simultaneously write and read the packet data (TS) 20 and insert a valid null packet during the reading. Therefore, the packet data (TS) 20 for one SFP is used for the stuffing. FIFO2 because there is no need to store
This has the effect of requiring only a small storage capacity and reducing the circuit scale.

Next, the stuffing control circuit of this embodiment is provided with an orthogonal frequency division multiplex (hereinafter referred to as OFDM: Orthogonal Frequeney Division Multip
An example applied to a modulator will be described. DVB-
The T standard is a transmission protocol for digital video terrestrial broadcasting standardized by the European Telecommunications Standards Institute (ETSI), and multiplexes video, audio, and data.
MPEG2 (Moving), a standard for storage and transmission methods
It is used to transmit TS (Transport Stream) which is a transmission data format of Picture Experts Group Phase 2). OFDM is a digital modulation method for modulating transmission digital data with a large number (several hundreds to thousands) of carrier waves orthogonal to each other, and is resistant to multipath fading and can increase the efficiency of frequency use.

As shown in FIG. 2, the OFDM modulator includes a stuffing control circuit 41, an error correction encoding circuit 42, a reference symbol insertion circuit 43, and an inverse fast discrete Fourier transform circuit 44 (hereinafter referred to as an IFFT circuit). Write)
A quadrature modulation circuit 45, and are arranged in this order from the input side. In this case, a TS output from a higher-level device (not shown) is input to a stuffing control circuit 41, which converts the speed into the system clock rate of the OFDM modulator, and inserts a valid null packet and an invalid null packet accompanying the speed conversion. After the insertion, it is input to the error correction coding circuit 42 and subjected to error correction coding.

The error-corrected coded signal is input to a reference symbol insertion circuit 43, into which a null symbol and a reference symbol required for demodulation are inserted.
The signal is input to a circuit 44 and subjected to inverse fast discrete Fourier transform processing, and a guard period for removing the effect of multipath is added. And this IFFT circuit 4
4 is input to a quadrature modulation circuit 45, converted into an analog signal, and then quadrature-modulated.
It is output as an M-modulated signal. That is, when the data rate of the TS output from the higher-level device is lower than the prescribed data rate, the stuffing control circuit 41
It is used to convert to a data rate specified by an OFDM modulator.

Next, the operation of the stuffing control circuit 41 in the OFDM modulator will be described in detail with reference to FIGS. First, writing to the FIFO 2 will be described. In this case, the TS 20 output from the higher-level device (not shown) is connected to the write control circuit 1 and the FIFO.
2 is input. TS input to write control circuit 1
At 20, a synchronization byte is detected, and a clock signal (TSCLK) 21 and a write control signal 22 synchronized with the transmission speed of the TS 20 are generated. Generated clock signal (TSCL
K) 21 and the write control signal 22 are output from the write control circuit 1 to the FIFO 2, and the input TS 20 is sequentially transmitted from the beginning of the packet to the FIFO at a speed synchronized with the transmission speed.
Written to O2. Further, the write control circuit 1
The number of packets for each SFP written in the IFO 2 is counted, and is output to the read control circuit 3 as write number data 23.

Next, reading from the FIFO 2 will be described. First, in the test packet flag generation circuit 5,
One SFP is set by setting data 24 such as a mode, a modulation method, and a coding rate sent from the transmission parameter setting circuit 4.
Frame pattern 2 with packet flags for the number of packets specified by each parameter of the setting data 24 for each
8 is generated and output to the read control circuit 3. In this case, the frame pattern 28 has a high level (H) when there is a packet flag and a low level (L) when there is no packet flag. This frame pattern 28 is composed of 1 SFP
It is only necessary to provide the packet flags of the number specified in, and the arrangement of the packet flags can be set freely. For example, by appropriately distributing the valid packets in one SFP,
Subsequent processing can be simplified.

Next, based on the frame pattern 28 input from the test packet flag generation circuit 5, the read control circuit 3 controls reading from the FIFO 2 and control of null packet insertion in the null packet insertion circuit 6. In this case, the read control circuit 3 sets the frame pattern 28
In the section without the packet flag, the null packet insertion circuit 6 inserts an invalid null packet. In the section of the frame pattern 28 where the packet flag is present, the write count data 23 input from the write control circuit 1 is stored.
The difference between the number of times of writing and the number of times of reading from the FIFO 2 generated by the read control circuit 3 is determined. If the difference is equal to or more than 1 and equal to or less than the specified number, the FIFO 2 reads one packet and converts the speed to the system clock rate. The TS 29 is output, and when it is 0, the null packet insertion circuit 6 inserts a valid null packet.

Next, insertion of a null packet when stuffing is performed will be described with reference to the timing chart of FIG. In this case, one SFP is composed of 11 packets, of which six valid packets are required, and valid packets 1 to
6 is written to FIFO2. Also, the frame patterns are the third, fifth, seventh, eighth, and tenth.
It is assumed that the packet flags are arranged at the 11th and 11th positions.

First, the first and second frame patterns have no packet flag, so the null packet insertion circuit 6
Performs invalid null packet insertion. Next, in the third frame pattern, since there is a packet flag, a difference between the number of times of writing and the number of times of reading is obtained. In this case, the writing of the valid packet 1 has been completed, and the valid packet 2
Is being written, the writing count is 1. on the other hand,
The read count is 0 because the read has not yet been performed.
It is. Therefore, the difference is 1 and not 0, so the FIF
The valid packet 1 is read from O2. Similarly,
An invalid null packet is inserted in the fourth and sixth frame patterns, and valid packets 2 and 3 are read in the fourth and seventh frames.

Next, in the eighth frame pattern, since there is a packet flag, a difference between the number of times of writing and the number of times of reading is obtained. In this case, since the writing of the valid packets 1 to 3 has been completed and the valid packet 4 is being written, the number of writing is 3. On the other hand,
This is 3 because the reading of the valid packets 1 to 3 has been completed. Therefore, since the difference becomes 0, the null packet insertion circuit 6 inserts a valid null packet.

Next, at the ninth frame pattern, since there is no packet flag, the null packet insertion circuit 6 inserts an invalid null packet. Next, in the tenth frame pattern, since there is a packet flag, a difference between the number of times of writing and the number of times of reading is obtained. In this case, the writing of the valid packets 1 to 4 has been completed, and the valid packet 5
Is being written, the writing count is 4. on the other hand,
The number of times of reading is 3 since the reading of the valid packets 1 to 3 has been completed. Therefore, the difference becomes 1 and is not 0, so that the valid packet 4 is read from the FIFO 2.

Since the eleventh frame pattern also has a packet flag, the difference between the number of times of writing and the number of times of reading is obtained. In this case, since the writing of the valid packets 1 to 5 has been completed and the valid packet 6 is being written, the number of times of writing is 5. On the other hand, the read count is 4 because the reading of the valid packets 1 to 4 has been completed.
Therefore, the difference becomes 1 and is not 0, so that the valid packet 5 is read from the FIFO 2. Thus, FIG.
As shown in the post-stuffing data, a valid null packet is placed after the valid packet 3 to obtain six SFPs in which the number of valid packets is defined.

As described above, since this OFDM modulator is provided with the stuffing control circuit 41 on the input side, even if the data rate output from the higher-level device is lower than the prescribed data rate, the OFDM modulator can be stored in one SFP. The number of valid packets included can be made equal to the specified number. In this case, the stuffing control circuit 41 can perform the speed conversion of the transmission speed and the insertion of the invalid null packet accompanying the speed conversion simultaneously with the stuffing, so that the circuit scale can be reduced. The stuffing control circuit 41 can simultaneously write and read the packet data (TS) 20 and insert a valid null packet during the reading. Therefore, the packet data (TS) for one SFP for stuffing is provided. Since there is no need to store 20, the storage capacity of the FIFO 2 can be small, and the circuit scale can be reduced.

Next, a second embodiment of the stuffing control circuit of the present invention will be described. The stuffing control circuit of this embodiment performs stuffing by writing to a FIFO at a transmission rate and reading out the data at a data rate before speed conversion specified by a predetermined transmission standard. FIG. 4 shows a second embodiment of the stuffing control circuit according to the present invention.
A stuffing control circuit including an effective null packet insertion circuit 8, a transmission parameter setting circuit 9, and an input rate monitoring circuit 10, and a speed conversion circuit including a second FIFO 11 and an invalid null packet insertion circuit 12 are provided.

In this case, the first FIFO 7 and the second FIFO 7
The FO 11 has a write clock input port and a read clock input port, and can simultaneously perform writing and reading at different speeds. First FIF
In O7, the clock signal (input TSCLK) 31 of the packet data (TS) 30 is input to the write clock input port, and the packet data (TS) 30 is written at the clock rate of the clock signal (input TSCLK) 31.

A clock signal (internal TSCLK) 32 having a prescribed clock rate before the speed conversion and synchronized with the system clock is input to the read clock input port, and the written data is transmitted to the clock signal (internal TSCLK).
TSCLK), and are input to the effective null packet insertion circuit 8 in the order of writing at the clock rate of 32.
In this case, the clock signal (internal TSCLK) 32 corresponds to the data rate before the speed conversion specified in accordance with each transmission parameter, and the clock signal (input TSCLK) 3
1 is slower than this specified data rate.

The transmission parameter setting circuit 9 outputs the specified transmission parameter setting data 34 to the input rate monitoring circuit 10. The input rate monitoring circuit 10 includes a packet data (TS) 30, setting data 34 output from the transmission parameter setting circuit 9, and a clock signal (internal TSCL).
K) 32, and outputs a valid null packet insertion signal 37 to the valid null packet insertion circuit 8. The input rate monitoring circuit 10 receives input packet data (T
S) Count the number of 30 packets and monitor the input rate,
1 SFP counted by clock signal (internal TSCLK) 32
Within this, it is determined whether or not the data rate is such that the number of valid packets per SFP defined by each parameter of the setting data 34 can be stored.

When the number of stored valid packets is insufficient,
Information for inserting a valid null packet is generated and output to the valid null packet insertion circuit 8 as a valid null packet insertion signal 37. The valid null packet insertion circuit 8 generates a valid null packet, inserts a valid null packet into the data read from the first FIFO 7 based on the input valid null packet insertion signal 37, and generates a second FIFO.
11 is output.

In the second FIFO 11, a clock signal (internal TSCLK) 32 is input to a write clock input port, and data output from the effective null packet insertion circuit 8 is written at a clock rate of the clock signal (internal TSCLK) 32. It is. A clock signal (SYSTEM CLK) 36 is input to the read clock input port, and the written data is read out in the order in which the data was written at the clock rate of the clock signal (SYSTEM CLK) 36 and speed-converted to the system clock rate. You. The invalid null packet insertion circuit 12 generates an invalid null packet, and generates a second F
An invalid null packet is inserted and output at a position where there is no valid packet in the data read from the IFO 11.

The stuffing control circuit of this embodiment can simultaneously execute writing and reading of the packet data (TS) 30 and insert a valid null packet during reading. Therefore, the stuffing control circuit normally monitors the input rate. Does not require a storage capacity for storing data for one SFP for counting the number of input packets in one SFP required for the data transfer, so that the storage capacity of the memory used for the stuffing can be small and the circuit size can be reduced. is there. Also, this stuffing control circuit has a first
Compared to the embodiment, the FIF constituting the speed conversion circuit
Since an extra O and a null packet insertion circuit are required, the overall circuit scale cannot be reduced as in the first embodiment. However, it is only necessary to dispose it before the speed conversion circuit, and the speed conversion circuit does not need to be changed. Therefore, there is an effect that application to an existing circuit is easy and development can be accelerated. Also, the stuffing control circuit 4 of the OFDM modulator shown in FIG.
As 1, the stuffing control circuit of this embodiment can be used.

[0035]

As described above, the stuffing control circuit according to the present invention is capable of simultaneously executing writing and reading of digital data at different speeds, and has a memory which is read out in the order in which the digital data is written. Packet insertion means for generating a null packet and inserting a valid null packet into the digital data read from the memory; and for reading the digital data from the memory so that the number of valid packets becomes a number specified by a predetermined transmission standard. And a packet insertion control means for controlling the packet insertion means to insert a valid null packet into the digital data having a frame structure composed of a plurality of packets. It is possible to insert a valid null packet to include a valid packet. , There is an effect that conventionally the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of an OFDM modulator using the stuffing control circuit of the present invention.

FIG. 3 is a timing chart illustrating null packet insertion.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a timing chart illustrating speed conversion.

[Explanation of symbols]

1. Write control circuit, 2, 7, 11 FIFO, 3.
Read control circuit, 4, 9 ... transmission parameter setting circuit,
5 Test packet flag generation circuit, 6 Null packet insertion circuit, 8 Valid null packet insertion circuit, 10 Input rate monitoring circuit, 12 Invalid null packet insertion circuit, 2
0, 29, 30 ... packet data (TS), 21 ... clock signal (TSCLK), 22 ... write control signal, 23 ...
Write count data, 24, 34 ... setting data, 25 ...
Read control signal, 26, 36 ... clock signal (SYSTEM
CLK), 27 ... null packet insertion signal, 28 ... frame pattern, 31 ... clock signal (input TSCLK), 32 ...
Clock signal (internal TSCLK), 37: valid null packet insertion signal, 41: stuffing control circuit, 42: error correction encoding circuit, 43: reference symbol insertion circuit, 44 ...
IFFT circuit, 45 ... quadrature modulation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H04L 13/08 H04L 11/20 102A F-term (Reference) 5K022 DD12 DD22 5K028 AA07 BB06 KK01 KK32 5K030 GA19 JA01 LA06 LB12 LD07 MA13 MB12 MC06 5K034 AA10 CC03 DD02 EE03 HH12 HH23 HH58 PP07 5K047 AA16 CC02 CC08 DD01 DD02 GG47 GG49 HH54 JJ04 KK00 LL01 MM26

Claims (7)

[Claims] 1. A stuffing control circuit for inserting a valid null packet into a digital data having a frame structure composed of a plurality of packets so as to include a valid number of valid packets specified by a predetermined transmission standard, A memory that can simultaneously execute writing and reading of data at different speeds, and that reads out the digital data in the order in which it was written; Packet inserting means for inserting a null packet, and controlling the packet inserting means while reading the digital data from the memory, so that the effective null packets are transmitted so that the number of effective packets becomes the number specified by the transmission standard. And a packet insertion control means for inserting the packet. Stuffing control circuit data is written to the memory at a transmission rate of the digital data, characterized in that it is configured to be read out from the memory at a defined transmission speed by the transmission standard. 2. The packet insertion control means inputs a clock signal corresponding to a transmission rate defined by the transmission standard to the memory, and converts the digital data written in the memory based on a predetermined frame pattern. 2. The apparatus according to claim 1, wherein the transmission rate of the read digital data is converted into a transmission rate specified by the transmission standard.
A stuffing control circuit as described. 3. A write control for controlling writing to the memory based on the input digital data and counting the number of packets written to the memory to generate write count data. A circuit, a transmission parameter setting circuit that outputs a transmission parameter specified by the transmission standard, a test packet flag generation circuit that generates a frame pattern from the transmission parameter, and, based on the frame pattern and the number-of-writes data, 3. The stuffing control circuit according to claim 2, further comprising a read control circuit for controlling reading of said memory and insertion of said valid null packet. 4. The stuffing control circuit according to claim 3, wherein the test packet flag generation circuit is configured to generate a frame pattern in which valid packets are arranged at an arbitrary position. 5. The read control circuit according to claim 1, wherein the difference between the number of packets written to the memory and the number of packets read from the memory is determined at a position where the valid packet is to be arranged based on the frame pattern. 5. The stuffing according to claim 3, wherein data is read from the memory when the number of valid packets is equal to or greater than 1 and equal to or less than the prescribed number of valid packets, and a valid null packet is inserted when the difference is 0. Control circuit. 6. The packet insertion means according to claim 1, wherein said digital data is converted into an invalid null packet and a valid null packet for replenishing a packet lacking as the digital data is converted into a transmission rate specified by said transmission standard. 6. The stuffing control according to claim 2, wherein the invalid null packet and the valid null packet are inserted into the digital data generated and read from the memory. circuit. 7. The packet insertion control means counts the number of packets of the digital data written in the memory, detects a shortage of valid packets with respect to the number of valid packets specified by transmission parameters of the transmission standard, An input rate monitoring circuit that controls the packet insertion unit to insert the valid null packet so that the number of valid packets becomes the number specified by the transmission standard, and that the transmission rate of the transmission standard is transmitted to the input rate monitoring circuit. 2. The stuffing control circuit according to claim 1, further comprising a transmission parameter setting circuit for outputting.