JP2001223328A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of simply and effectively connecting between laminated insulating boards, easily inspecting its connecting state, and easily repairing when a failure occurs at a portion. SOLUTION: The semiconductor device comprises a plurality of insulating boards 10 for mounting electronic components 12 and sequentially laminated. The components 12 are flip-chip mounted on one surface of the board 10. Conductive wirings 11 are provided to project from a peripheral edge of the board 10. The wirings 11 are bent to the other surface side of the board 10. The bent wiring 11 and the wiring 11 on the board 1 lower by one layer than the board 10 are connected in continuity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of insulating substrates on which electronic components are mounted are sequentially laminated, and more particularly, to a semiconductor device in which electronic components are flip-chip mounted on one surface of an insulating substrate. It is suitable to be applied to.

[0002]

2. Description of the Related Art In recent years, electronic equipment has been becoming lighter, thinner and smaller, and high-performance integration and high-speed signal processing have been advanced. Along with this, the shape of the semiconductor device is changed from a shape in which lead terminals, which are conductive wiring, are drawn out from the side surface of a package such as a QFP (Quad Flat Package) in a gull wing shape, for example, a BGA (Ball Grid Arra).
By forming electrodes using gold bumps or the like on the lower surface side of the package as shown in y), etc., the area occupied by the semiconductor device when mounting such a semiconductor device on a motherboard is significantly reduced. It is shifting to a shape that can be transformed.

[0003] As a semiconductor device further downsized than the BGA, for example, a semiconductor chip as an electronic component is mounted on a rigid substrate or the like as an insulating substrate made of ceramics by a method such as a flip chip mounting method. CSP (Chip Size Package) is attracting attention.

[0004]

However, according to the above-described conventional semiconductor device, it is difficult to reduce the area occupied by one such semiconductor device on the mother substrate by reducing the size of the package. Although it is possible, the number of mounting semiconductor devices mounted on the motherboard has been increasing along with the recent addition of new functions to electronic equipment. Was.

In such a semiconductor device, not only the mother substrate becomes large, but also the length of the lead terminals from the main semiconductor device to other semiconductor devices becomes extremely long. This results in distortion, an increase in power consumption, and the like, resulting in inconvenience that it is difficult to obtain predetermined electrical performance. Particularly, in the case of a media device having a high-speed and large-capacity circuit system, reducing the lead terminal length has been an important issue.

Further, even if the mother board is reduced in size, the number of semiconductor devices that can be mounted on a mounting area for one semiconductor device on the mother board is one. There is also a risk of limiting the number of semiconductor devices to be obtained.

As one method for solving such a problem,
Conventionally, for example, JP-A-10-223683, JP-A-63-6115
No. 0 and Japanese Patent Application Laid-Open No. 7-106509, etc., provide wiring, solder balls, inner leads, via holes, through holes, and the like on an insulating film or an insulating sheet on which a semiconductor chip is mounted. Insulating films and insulating sheets are sequentially laminated, and wiring, solder balls, inner leads,
There have been proposals for conductive connection via via holes and through holes.

However, in this case, it is difficult to visually confirm the connection state between the insulating films and the insulating sheets, and it is necessary to seal a part or the whole of the laminated insulating films and the insulating sheets with a resin. For this reason, it is difficult to repair even if some defects occur, and there is still an insufficient problem.

Further, as disclosed in Japanese Patent No. 3033315, etc., an electronic component such as an IC is subjected to inner lead bonding on an insulating substrate made of polyimide or the like, and a peripheral portion of the insulating substrate thus laminated is laminated. A multilayer multi-chip semiconductor device has been proposed in which an outer lead of an upper layer and an outer lead of one layer below the outer lead are sequentially electrically connected to each other by an outer lead which is a conductive wiring extending to the semiconductor device.

However, in this case, in order to ensure the strength of the joint between the inner lead of the insulating substrate and the electrode of the electronic component, the insulating substrate must have a predetermined size.
In addition, when stacking, it is necessary to provide a spacer having a predetermined thickness on the outer lead portion in order to avoid contact between the upper electronic component and the inner lead one layer below. There were still insufficient problems in thinning.

Therefore, a first object of the present invention is to prevent a conductive wiring from being bent when connecting a conductive wiring on each insulating substrate to an electrode of an electronic component in a semiconductor device. , Miniaturize the insulating substrate to the minimum necessary,
An object of the present invention is to make a package sufficiently small for practical use.

In addition, the connection state between the laminated insulating substrates is visually checked and easily inspected, and the number of parts of the semiconductor device is reduced to simplify the configuration.
An object of the present invention is to provide a simple and reliable conductive connection between laminated insulating substrates.

A second problem is to stably laminate a plurality of insulating substrates on which electronic components are mounted, and a third problem is to prevent the laminated insulating substrates from collapsing before conducting connection. It is to prevent.

A fourth problem is to prevent a plurality of conductive wirings from being separated, and a fifth problem is that when a plurality of insulating substrates on which electronic components are mounted are stacked, these insulating substrates are stacked. In order to simplify the positioning of the device.

A sixth object is to be able to withstand stress concentration generated between conductive wirings at corners of each insulating substrate due to internal strain caused by heat at the time of conductive connection.

A seventh problem is to form alignment marks for positioning without increasing the number of parts, and an eighth problem is to easily form alignment marks for positioning.

A ninth problem is that the conductive wiring is bent so as to be curved at the periphery of the insulating substrate, so that damage and disconnection of the conductive wiring caused by the stress when the conductive wiring is bent can be prevented. Is to prevent it.

[0018]

According to a first aspect of the present invention, there is provided a semiconductor device in which a plurality of insulating substrates on which electronic components are mounted are sequentially laminated to achieve the first object. On one surface of each insulating substrate, electronic components are flip-chip mounted, and conductive wiring is provided so as to protrude from the periphery of each insulating substrate, and the conductive wiring is connected to the other surface of each insulating substrate. And the conductive wiring is electrically connected to the conductive wiring on the insulating substrate one layer below the insulating substrate.

According to a second aspect of the present invention, in order to achieve the above-mentioned second object, a plurality of insulating substrates to be stacked are sequentially mounted on adjacent lower electronic components. I do.

According to a third aspect of the present invention, in order to achieve the third object, an adjacent insulating substrate and an electronic component are provided with an adhesive therebetween.

According to a fourth aspect of the present invention, in order to achieve the fourth object, a plurality of conductive wirings are arranged and arranged on each insulating substrate, and a tip of the conductive wiring protruding from a peripheral edge of each insulating substrate. The portion is provided with a dispersion preventing member for bundling these conductive wires.

According to a fifth aspect of the present invention, in order to achieve the fifth object described above, each of the insulating substrates has, at four corners thereof, positioning projections for laminating these insulating substrates. Features.

According to a sixth aspect of the present invention, in order to achieve the sixth object, the conductive wiring at the corner of the plurality of conductive wirings is wider than the other conductive wirings. It is characterized by that.

According to a seventh aspect of the present invention, in order to achieve the seventh object, an alignment mark for positioning is formed on a wide conductive wiring.

According to an eighth aspect of the present invention, in order to achieve the eighth object, the alignment mark is formed by a round hole.

According to a ninth aspect of the present invention, in order to achieve the ninth object, the bent portion of the conductive wiring is curved.

[0027]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1 and 2 are an external perspective view and a longitudinal sectional view of a semiconductor device according to the present invention. In the illustrated semiconductor device, for example, an adhesive such that an insulating substrate 10 on which a semiconductor chip 12 such as an IC or an LSI, which is an electronic component, is mounted is superimposed on the lower semiconductor chip 12 in order. And laminated. Also,
On the other surface side of the lowermost insulating substrate 10 of the semiconductor device, electrodes 10A for electrically connecting the semiconductor device to a mother substrate or the like are arranged in a predetermined arrangement.

The insulating substrate 10 is made of glass epoxy, polyimide, or the like. A conductive wiring 11 is disposed on one surface of the insulating substrate 10 in a predetermined pattern. One end 11A of the conductive wiring 11 has an electrode 12A of the semiconductor chip 12. Are mounted by a flip chip mounting method or a TAB method to form modules MO1 to MO4, respectively.

The other end 11B of the conductive wiring 11
Extends at the peripheral edge of the insulating substrate 10, for example, protruding downward from the other surface side of the insulating substrate 10, is bent with a curve, and the tip is one layer higher than the insulating substrate 10. Corresponding conductive wiring 11 on lower insulating substrate 10
And are sequentially joined via solder 16 or the like.

In this embodiment, the tip of the other end 11B of the conductive wiring 11 in each layer is made of, for example, the same material as the insulating substrate 10 to prevent the conductive wiring 11 from scattering. A member 13 is provided, and each of the conductive wires 11 is fixed so as to have a certain pitch accuracy.

In order to form such a laminated structure, the module MO1 in which the semiconductor chip 12 is mounted on the insulating substrate 10,
MO2, MO3, MO4 are sequentially formed on the upper insulating substrate 10;
After laminating the semiconductor chip 12 one layer below via an adhesive, the conductive wires 11 of each layer are sequentially joined in the vertical direction to complete the electrical connection between the layers. At this time, in the semiconductor chips 12 of the modules MO1 to MO3, the electrodes of the semiconductor chips 12 and the conductive wires 11
Is sealed with a sealing resin FJ made of an insulating material or the like.

By stacking the modules MO1 to MO4, the tips of the conductive wirings 11 sequentially bent from the uppermost insulating substrate 10 are placed one layer below the insulating substrate 10
It comes into contact with the upper surface of the upper conductive wiring 11. Then, the contacting conductive wires are joined by soldering, a conductive paste material, welding, or the like.

As described above, in this semiconductor device, the respective semiconductor chips 12 are electrically connected to each other sequentially through the conductive wirings 11 of the respective insulating substrates 10, and are connected to the mother substrate through the lowermost electrodes 10 A. It is configured to be electrically connected to the electrode.

Incidentally, when the semiconductor chip 12 to be mounted is different, the wiring pattern of the conductive wiring 11 formed on the insulating substrate 10 of each layer is not necessarily the same wiring pattern, and the electrodes of the non-common semiconductor chip are not necessarily the same. The wiring configuration is different for processing.

The insulating substrate 10 and the semiconductor chip 1
The thickness 2 is a thickness of several tens [μm] to several hundreds [μm]. The semiconductor chip 12 is formed by a mechanical polishing method such as gliding or polishing, or a chemical polishing method such as a method of dissolving the back surface on which no elements are formed in a wafer state or a chip state with an etching solution mainly composed of an HF solution, or the like. Is polished to a desired thickness by a CMP method or the like using the above method in combination.

Further, in this semiconductor device, as shown in FIG. 3, the conductive wirings 11 located at least at the ends (closest to the corners) of the plurality of conductive wirings 11 arranged on the insulating substrate 10 are arranged. The width may be formed to be wider than the width of another conductive wiring 11 located inside the conductive wiring 11.

Thus, when stress concentration occurs in the conductive wiring 11 due to a difference in expansion between the semiconductor chip 12 and the insulating substrate 10, they can be prevented from being broken, and high reliability can be obtained. Can be obtained. Further, the width of the conductive wiring 11 varies depending on the dimensions of the insulating substrate 10 and environmental conditions, but it is desirable that the width of the wider one is 1.2 times or more larger than the width of the narrower one.

FIG. 3 shows a configuration in which protrusions 15 are provided at at least four corners of the insulating substrate 10. In this manner, the protrusion 15 is formed integrally with the insulating substrate 10 so as to protrude beyond its outer dimensions.

With such a configuration, the position of the conductive wiring 11 is located inside the projection 15.
In addition, it is possible to prevent the conductive wiring 11 bent from the peripheral edge of the insulating substrate 10 from coming into contact with an external component or damaging the conductive wiring during operation. The protrusions 15 can not only protect the conductive wiring mechanically and electrically, but also can be used for alignment between the insulating substrates 10 when the insulating substrates 10 are laminated. If the tip of 15 is the outer shape for alignment,
Positioning can be facilitated.

In addition, if the outer dimensions of the projection 15 and the outer dimensions of the lowermost insulating substrate 10 having the electrodes 10A for connection to the electrodes of the mother board are made substantially the same, the protrusions 15 can be laminated. Not only is the positioning of the substrate easy, but also in the case where a protective resin is formed in the bent conductive wiring region, that is, in the side region of the insulating substrate, the protrusions of the lowermost insulating substrate 10 and the other insulating substrate 10 If the external dimensions of the 15 are substantially the same, not only can the protective resin be easily formed, but also the thickness of the protective resin can be made uniform.

Further, in this semiconductor device, the connection of the conductive wiring 11 between the laminated insulating substrates 10 is performed, for example, by disposing a solder material on the conductive wiring 11 and reflowing the solder material. Since the bent conductive wiring 11 is in contact with the conductive wiring 11 on the insulating substrate 10 located thereunder, the solder can be easily connected by melting the solder.

Further, for example, the solder may be melted in a solder bath provided with a heater, and the stacked modules MO1 to MO4 may be immersed and connected in the melted solder.

As described above, in the step of immersing the semiconductor device in the molten solder in the solder bath, when the semiconductor device is lifted from the molten solder, at least one corner of the hexagonal semiconductor device is melted. When the angle θ formed with the solder surface is in the range of 30 ° to 60 °, a short circuit between adjacent conductive wirings 11 connecting the insulating substrates 10 can be prevented.

Further, on the other side of the lowermost insulating substrate 10, an external connection electrode 10A for connecting to the mother substrate is provided.
Are formed. In the example of FIGS. 1 and 2, a solder ball is formed as the electrode 10A, and a so-called CSP
(Chip Size Package) and the structure of BGA (Ball Grid Array). The lowermost insulating substrate 10 and the conductive wiring 11 formed thereon are manufactured by the same method as the upper insulating substrate 10.

Further, as a method of bending the conductive wiring 11 at the periphery of the insulating substrate 10, for example, by bending the conductive wiring 11 so as to bend, the conductive wiring 11 may have a conductive property such as a crack caused by a stress caused by bending the conductive wiring 11. The damage and disconnection of the conductive wiring 11 can be prevented.

[0047]

As described above, according to the present invention,
In a semiconductor device formed by sequentially laminating a plurality of insulating substrates on which electronic components are mounted, since the electronic components are flip-chip mounted on one surface of the insulating substrate, a connection between one end of the conductive wiring and an electrode of the electronic component is formed. In this case, the conductive wiring can be prevented from being bent and deformed by the insulating substrate, and the conductive substrate can be prevented from being deformed, so that the insulating substrate can be miniaturized to the minimum necessary. A semiconductor device capable of reducing the size of a package for practical use can be realized.

Further, by connecting the conductive wirings between the respective insulating substrates at the peripheral portions of the insulating substrates, the connecting portions of the semiconductor device can be visually checked from the outside.
Inspection of the connection portion can be made extremely easy, and thus, conductive connection between the insulating substrates can be easily and reliably performed.

Further, since the connection is made on the side surface of the laminated insulating substrate, even if a defect occurs in a part of the laminated insulating substrate, repair can be easily performed. In addition, since the conductive wiring for connection is formed to protrude from the side surface of the insulating substrate, the solder dip or
The connections can be made collectively using a simple process such as solder reflow, and thus a low-cost module can be realized.

According to the second aspect of the present invention, the sense of stability when stacking a plurality of insulating substrates is enhanced by stacking the insulating substrate of one lower layer on the electronic component of the lower layer of each insulating substrate. be able to.

According to the third aspect of the present invention, the adhesive is interposed between the insulating substrate and the electronic component which are adjacent in the laminating direction, so that the plurality of laminated insulating substrates can be connected before the conductive connection. Collapse can be prevented beforehand.

According to the fourth aspect of the present invention, a plurality of conductive wirings are arranged on the insulating substrate, and the end of the other end of the conductive wiring on the uppermost or lowermost insulating substrate is provided with an anti-separation member. Is provided, it is possible to prevent the conductive wirings from being separated and to fix the conductive wirings so as to have a constant pitch accuracy.

According to the fifth aspect of the present invention, since the protrusions are provided at the corners of the insulating substrate, the positioning at the time of laminating the upper and lower insulating substrates is further facilitated by using the protrusions. And high alignment accuracy can be obtained. In addition, it becomes a reference for the outer shape at the time of resin molding of the mounting body, so that accurate resin molding can be performed.

Further, since the projections are provided so as to protrude from the conductive wiring between the laminated insulating substrates, external force is applied to the conductive wiring to prevent the conductive wiring from being deformed or damaged. can do.

According to the invention of claim 6, since the conductive wiring at the corner of the array of the plurality of conductive wirings on the insulating substrate is wider than the other conductive wirings, the electronic component and the insulating substrate Due to the difference between the expansion and the expansion, it is possible to prevent the conductive wiring from being broken when stress is applied thereto, and to improve reliability in connection.

According to the seventh aspect of the present invention, the alignment mark can be provided on the wide conductive wiring at the corner of the conductive wiring without increasing the number of parts, and a plurality of insulating substrates are laminated. In this case, positioning between the upper and lower insulating substrates can be further simplified.

According to the eighth aspect of the present invention, by forming the alignment mark with a round hole, the alignment mark can be easily formed collectively in another process.

According to the ninth aspect of the present invention, since the bent portion of the conductive wiring at the peripheral portion of the insulating substrate is curved, the conductivity caused by the stress when the conductive wiring is bent is obtained. Wiring damage and disconnection can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a semiconductor device according to the present invention.

FIG. 2 is a longitudinal sectional view of the semiconductor device.

FIG. 3 is a plan view showing an insulating substrate in which protrusions are formed at four corners of the insulating substrate and corners of conductive wiring are formed to be wide;

[Explanation of symbols]

 MO1 module MO2 module MO3 module MO4 module FJ sealing resin layer 10 insulating substrate 10A electrode 11 conductive wiring 11A one end 11B other end 11C alignment mark 12 semiconductor chip (electronic component) 13 anti-separation member 14 adhesive 15 protrusion 20 jig

Claims (9)

[Claims] 1. A semiconductor device in which a plurality of insulating substrates on which electronic components are mounted are sequentially laminated, wherein each of the electronic components is flip-chip mounted on one surface of each of the insulating substrates, and each of the insulating substrates is Conductive wiring is provided so as to protrude from the periphery of the insulating substrate, and the conductive wiring is bent to the other surface side of each of the insulating substrates, and the bent conductive wiring and the insulating substrate one layer below the insulating substrate are provided. A semiconductor device having a conductive connection with an upper conductive wiring. 2. The semiconductor device according to claim 1, wherein the plurality of insulating substrates to be stacked are sequentially mounted on adjacent lower electronic components. 3. The semiconductor device according to claim 2, wherein the adjacent insulating substrate and the electronic component have an adhesive therebetween. 4. An anti-separation member for arranging a plurality of the conductive wirings on each of the insulating substrates, and bundling the conductive wirings at a leading end of the conductive wirings protruding from a peripheral edge of each of the insulating substrates. The semiconductor device according to claim 1 provided. 5. The semiconductor device according to claim 1, wherein each of the insulating substrates has, at four corners thereof, positioning protrusions for laminating the insulating substrates. 6. The semiconductor device according to claim 1, wherein the conductive wiring at the end of the plurality of conductive wirings is wider than the other conductive wirings. 7. The semiconductor device according to claim 6, wherein an alignment mark for positioning is formed on said wide conductive wiring. 8. The alignment mark comprises a round hole,
The semiconductor device according to claim 7. 9. The semiconductor device according to claim 1, wherein said bent portion of said conductive wiring is curved.