JP2001223222A - Low-loss transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low-loss transistor, which is low in on-voltage and short in switching time. SOLUTION: A bipolar transistor is provided with a substrate, a collector layer consisting of a first conductivity type Si film, a base layer consisting of a second conductivity type SiGe film, an emitter layer consisting of a first conductivity type Si film, a base electrode formed by a method where one part of the emitter layer is made to cut away or the conductivity type of one part of the emitter layer is made to invert and a metal terminal is bonded to the part, an emitter electrode formed by bonding the metal terminal to the emitter layer, and a collector electrode formed by bonding the metal terminal to either of the substrate and the collector layer and in the bipolar transistor. When the total extension of the contact interface of the part arranging closely the emitter electrode to the base electrode per unit area is assumed to be X (mm/cm2) and the doping concentration (atoms/cm3) of the emitter layer is assumed to be Y, the relations of X>=500 and the relation of Y>=9.0×1018-3.2×1015X are both satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-loss transistor capable of operating at high speed, and more particularly to a high-power low-loss transistor having a short switching time.

[0002]

2. Description of the Related Art Conventionally, a bipolar transistor, a MOSFET (Metal Oxide Semiconductor field effect transistor) or an IGBT (Insulated Gate Bipolar Transistor) made of silicon has been used as a switching element for controlling on / off of current.
r) has been used. These transistors are used in a common emitter circuit as shown in FIG. This is an example of a bipolar transistor, but a MOSFET or IGBT
But it is almost the same circuit. In this circuit, the emitter electrode 4 and the collector electrode 6 of the transistor 14 are connected to the load 16
Is connected to the power supply 17 via the.

In order to turn on the bipolar transistor 14 in this circuit, a base current is caused to flow in a forward direction when the base and the emitter are regarded as diodes, so that the impedance between the emitter and collector of the transistor 14 becomes low, and the load is reduced. A current flows through the transistor 16, and at this time, the transistor 14 is turned on. By setting the base current to zero, the impedance between the emitter and the collector of the transistor 14 becomes high, the current flowing into the load 16 is cut off, and the transistor 14 is turned off at this time.

Normally, in order to control the power applied to the load 16, the base current is repeatedly turned on and off, and the switching between on and off is performed in as short a time as possible. In this case, the base current has a square wave shape, and the power transmitted from the power supply 17 to the load 16 can be changed by changing the ON / OFF time ratio. This method is called a pulse width modulation method (PWM method). In this PWM method, the voltage between the emitter and the collector of the transistor 14 is almost infinitely close to zero during the ON operation, and the collector current is cut off during the OFF operation.
The heat generation power in No. 4 can be kept low. That is, while suppressing the power loss in the transistor 14, the load 16
Power is supplied efficiently to the

[0005] The power loss of a transistor in such a switch circuit is determined by the ON voltage of the transistor and the switch time. Here, "ON voltage" means a voltage drop generated between the emitter and the collector when the transistor is turned on. Since the product of the on-voltage and the current flowing there results in power loss when the transistor is turned on, the on-voltage should be as low as possible. On the other hand, with respect to the switching time, a state in which a voltage is increased between the collector and the emitter while a current flows through the transistor during switching occurs transiently, which causes the transistor to generate heat. That is, the longer the switch time, the greater the power loss. The power loss causes heat generation of the transistor, which requires a radiator, which causes an increase in the size of the device and an increase in cost. For this reason, O
In order to reduce the power loss at the time of N, it is necessary to reduce the ON voltage as much as possible and to shorten the switching time as much as possible.

[0006]

A conventional bipolar transistor as a switching element does not have such a low on-voltage and does not have a sufficiently short switching time. For example, in a bipolar transistor, a main current of 10 A or more can be passed, and the ON voltage at the rated current is at least about 0.5 V. Here, the rated current is defined as the main current value when the current density of the chip becomes 80 A per 1 cm ² . In most cases, a switch time of 1 microsecond (μs) or more is required.

[0007] In the case of a MOSFET, the rated current is 1.0 V
And switching time is several hundred nanoseconds (ns)
Most of them take some time.

Further, in the IGBT, the ON voltage is 1.2 V or more at the rated current, and the switch time is 1 to 10 μs or more.

From the above, in order to further reduce the power loss with respect to the conventional transistor, the on-state voltage at the time of the rated current is 1.0 V or less, and the switching time is 1 V or less.
It can be said that it is necessary to be less than 00 ns.

The present invention has been made to solve the above-described problems, and has as its object to provide a low-loss transistor having a low on-voltage and a short switching time.

[0011]

SUMMARY OF THE INVENTION The present inventors have previously described SiGe in Japanese Patent Application No. 11-204055.
We proposed a bipolar transistor using. In this specification, the base layer is made of p-type SiGe containing 5 atomic% of Ge and has a thickness of 0.4 μm and an emitter having a thickness of 0.4 μm.
6 μm n-type Si, n-type collector with thickness of 20 μm
(Hereinafter, referred to as a prior application transistor). The doping concentration of the base, collector and emitter of this prior application transistor is 2 ×
10 ¹⁷ atom / cm ³ and 5 × 10 ¹⁴ atom / cm ³ , 5 × 10 ¹⁸
atom / cm ³ . As a result, the withstand voltage of the prior application transistor was in the range of 150 V to 225 V. In addition, the switching time of the transistor of the prior application is 100 ns or less, and the switching time is superior to that of the conventional device. However, the on-voltage of the prior application transistor is relatively high at 10 V or more at the rated current, and it is necessary to further reduce the on-voltage to reduce switch loss. The present inventors have conducted intensive studies on reducing the ON voltage and the switching time, and as a result, have completed the present invention described below.

A low-loss transistor according to the present invention comprises a substrate, a collector layer made of a first conductivity type Si film laminated on the substrate, and a second conductivity type Si film laminated on the collector layer. A base layer made of a SiGe film, an emitter layer made of a Si film of the first conductivity type formed on the base layer, and a part of the emitter layer
Alternatively, a base electrode formed by inverting a part of the conductivity type of the emitter layer and joining a metal terminal to the missing or inverted portion, and a metal electrode is formed by joining a metal terminal to the emitter layer. In a transistor including an emitter electrode and a collector electrode formed by bonding a metal terminal to either the substrate or the collector layer, a portion where the emitter electrode and the base electrode per unit area are arranged close to each other Is defined as X (mm / cm ² ), and the doping concentration (atom / cm ³ ) of the emitter layer is defined as Y (contact / length).
Where both of the following expressions (1) and (2) are satisfied.

X ≧ 500 (1) Y ≧ 9.0 × 10 ¹⁸ −3.2 × 10 ¹⁵ X (2) FIG. 6 shows the contact length (mm / cm ² ) on the horizontal axis and emitter doping on the vertical axis. FIG. 9 is a graph showing the results of examining the influence of the contact length and the emitter doping concentration on the on-state voltage by taking the concentration (atom / cm ³ ). As a result of intensive studies conducted by the present inventors, the conditions under which the ON voltage is 1.0 V or less are as follows.
It has been found that a region to the right of the characteristic line A (a region satisfying the above equation (1)) and a region above the characteristic line B (a region satisfying the above equation (2)) overlap each other.

According to the low-loss transistor of the present invention, a performance with an on-state voltage of 1.0 V or less and a switch time of 100 nanoseconds or less is achieved.

In this case, the Ge content of the base layer made of the SiGe film of the second conductivity type is 2.5 to 15% in atomic density.
(Atomic%). As shown in FIG.
When the Ge content in the base layer is less than 2.5% in atomic density, the switching time is as slow as 400 to 500 ns, but when the Ge content is 2.5% or more in atomic density, the switching time is less than 100 ns. Be faster. In particular, when the Ge content is 4% or more in atomic density, the switching time is stabilized to 100 nanoseconds or less. However, when the Ge content in the base layer is 1
If it exceeds 5%, a leakage current is generated between the collector and the base, and the transistor does not operate at all and the amplification function is lost. Therefore, the upper limit of the Ge content is set to 15 atomic%.

In order to improve the on-voltage, it is important to increase the doping concentration of the emitter to increase the contact length.

The reason why the base layer is made of SiGe will be described. By converting the base layer to SiGe, strain is generated in the base layer and the collector layer, and the life time of the minority carriers in the base layer is shortened by the influence. This results in a reduction in the charge stored in the base layer, which results in a shorter switching time.

The doping concentration of the impurity element in the emitter layer is increased.
The chemical vapor deposition method is used as a method for the above. Chemical vapor deposition
In the multiplication method, heating is performed in a vacuum vessel filled with semiconductor material gas.
A substrate with a thin film deposited on it
Is the law. For example, based on a Si film doped with n-type impurities
To deposit on the plate surface, use disilane as a process gas.
(Si_TwoH₆) Or silane (SiH_Four) And phosphine
(PH_Three) Is used. On the other hand, p-type impurities
To deposit a doped SiGe film on the substrate surface,
Disilane (Si_TwoH₆) Or silane (S
iH_Four) And diborane (B_TwoH₆) And Germanic (GeH)_Four)When
Is used. At this time, the substrate temperature is set to, for example, 650.
Set to ℃ or higher. The P doping concentration of the n-type Si film is
Run (Si _TwoH₆) Or silane (SiH_FourFor)
Sphine (PH_Three), But 1 × 1
0¹⁹/ Cm^ThreeTo achieve the above P doping concentration, the mixing ratio
(PH_ThreePartial pressure / Si_TwoH₆Partial pressure or SiH_Four10)
It can be obtained by setting it to 0 ppm or more. Emi
When forming an n-type Si film corresponding to the
In addition to vapor deposition, use diffusion or ion implantation.
Can be

In order to increase the contact length, the emitter electrode 4
The base electrode 5 and the base electrode 5 may be arranged in a comb-like shape as shown in FIGS. 2 and 3 (vertical sectional view of FIG. 2). When the emitter electrode 4 and the base electrode 5 are arranged in a comb shape in this manner, it is effective to form the comb teeth as thin as possible to form a large number. As shown in FIG. 4, the emitter electrodes 4 and the base electrodes 5 having substantially the same width may be alternately arranged in a plane. In addition to the comb-teeth shape for extending the contact length, for example, a spiral emitter electrode 4 and a base electrode 5 may be arranged in a plane on a circular substrate as shown in FIG.

The effect of extending the contact length will be described with reference to FIG.

When the transistor is turned on, the collector current flowing between the emitter and the collector tends to concentrate near the vicinity of the emitter electrode 4 and the base electrode 5, and a region 20 where the collector current flows at a high density appears as shown in FIG. I do.
For this reason, a region where current does not easily flow is generated near the center of the width of the emitter electrode 4 and near the center of the width of the base electrode 5. When the width of the emitter electrode 4 and the width of the base electrode 5 are reduced to increase the contact length between the emitter electrode 4 and the base electrode 5, that is, the contact length per unit area is increased. Can be increased, which contributes to a decrease in ON voltage.

On the other hand, increasing the doping concentration of the emitter layer 3 has the effect of dispersing the collector current that tends to concentrate in the region 20 where the emitter electrode 4 and the base electrode 5 are close to each other. Dispersion of the collector current facilitates the flow of the collector current to the central region of the width of the emitter electrode 4,
Since the area through which the current flows increases, the on-state voltage is reduced.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

Example 1 As Example 1, a high power bipolar transistor 14 shown in FIGS. 2 and 3 was manufactured. A method for manufacturing the transistor 14 of Embodiment 1 will be described with reference to FIGS.

First, a P-doped n-type Si layer 1 having a thickness of 20 μm and a p-type B-doped S are formed on an n-type 0.001 Ω · cm silicon substrate 1A by chemical vapor deposition.
An iGe layer 2 having a thickness of 0.4 μm and an n-type P-doped Si layer 3 were sequentially laminated thereon to obtain a laminated structure (FIG. 1).
(A), (b)). In order to deposit the Si layer 1 doped with the n-type impurity on the substrate surface, disilane (Si ₂ H ₆ ) or a mixed gas of silane (SiH ₄ ) and phosphine (PH ₃ ) is used as a process gas.

On the other hand, in order to deposit the SiGe layer 2 doped with a p-type impurity on the Si layer 1, disilane (Si ₂ H ₆ ) or silane (SiH ₄ ) and diborane (B ₂ H ₆ ) are used as process gases. And a mixed gas of germane (GeH ₄ ). At this time, the substrate temperature was set to, for example, 650 ° C. or higher. The Ge content of the p-type SiGe layer serving as the base layer 2 was set to about 5 atomic%.

The P doping concentration of the n-type Si layer 3 is determined by the mixing ratio of phosphine (PH ₃ ) to disilane (Si ₂ H ₆ ) or silane (SiH ₄ ), but 1 × 10 ¹⁹
To achieve a P-doping concentration of / cm ³ or more, the mixing ratio (P
H ₃ partial pressure / Si ₂ H ₆ partial pressure or SiH ₄ partial pressure) to 100p
pm or more. In this embodiment, the doping amount of each of the layers 1, 2 and 3 is 5 × 10 ¹⁴ atom / cm.
³ , 5 × 10 ¹⁷ atom / cm ³ , 5 × 10 ¹⁸ atom / cm ³ 〜1 ×
It is 10 ¹⁹ atom / cm ³ .

Subsequently, parts other than the transistor are removed by using a chemical etching method, and a part of the emitter is removed by using chemical etching. Thereafter, a metal film is formed on the emitter layer and the base layer exposed on the surface by using an evaporation method, and the emitter electrode 4 and the base electrode 5 are respectively formed.
And Further, a metal film was deposited on the back surface of the substrate 1A to form a collector electrode 6.

Thus, the transistor 14 of the first embodiment shown in FIGS. 2 and 3 was obtained. The transistor 14 according to the first embodiment has a size of 5 × 5 mm square, and its electrode pattern has a comb shape as shown in FIG. While adjusting the width of the emitter electrode 4 and the comb width of the base electrode 5,
By changing the number of combs, the peripheral length of the contact interface between the adjacent electrodes 4 and 5 was variously changed in the range of 40 to 560 mm. The perimeter in this range corresponds to a range of 160 to 2240 mm / cm ² when converted to a contact length per unit area.

FIG. 6 shows the results of evaluation of the on-voltage of each of the transistors manufactured here, with the rated current of 20 A. In FIG. 6, the horizontal axis indicates the contact length (mm / cm ² ), and the vertical axis indicates the doping concentration (atom / cm ³ ) of the emitter layer. FIG. 4 is a characteristic diagram showing a result.
From the figure, when the contact length is X (mm / cm ² ) and the doping concentration (atom / cm ³ ) of the emitter layer is Y, the inequality (1); X ≧ 500 mm / cm ² is satisfied and the inequality is satisfied. (2): When Y ≧ 9.0 × 10 ¹⁸ −3.2 × 10 ¹⁵ X, the on-state voltage was found to be 1.0 V or less.

Embodiment 2 As Embodiment 2, a high power bipolar transistor 14A shown in FIG. 4 was manufactured. An outline of a method for manufacturing the transistor 14A of the second embodiment will be described.

An n-type silicon substrate 1 of 0.001 Ω · cm
N-type S doped with P by chemical vapor deposition on
iGe layer 1 is 20 μm, p-type B-doped SiGe layer 2
0.4 μm, and an n-type P-doped Si layer 3
Were sequentially laminated to obtain a laminated structure. Doping amount of each layer 1, 2 and 3, respectively ^{5 × 10 14 atom / cm 3} , 5 × 10 1 7 a
tom / cm ³ , 5 × 10 ¹⁸ atom / cm ³ .

The SiGe layer 2 doped with a p-type impurity is
In order to deposit on the i-layer 1, a process gas
Run (Si_TwoH₆) Or silane (SiH_Four) And diborane
(B_TwoH ₆) And Germanic (GeH)_FourUsing a gas mixture with
You. At this time, the substrate temperature was set to, for example, 650 ° C. or higher. What
Regarding the Ge content of the SiGe layer 2 (base layer),
Various changes in the atomic density range from 0% to 15%
A star was made.

As a result, a transistor 14A of Example 2 shown in FIG. 4 was obtained. Transistor 14 of Embodiment 2
In A, emitter electrodes 4 and base electrodes 5 having substantially the same width are alternately arranged in a plane. The width of the electrodes 4 and 5 is, for example, 200 μm of the same size.

As shown in FIG. 5, a circular transistor 14B in which a spiral emitter electrode 4 and a base electrode 5 are planarly arranged on a circular substrate 1A as shown in FIG.
It may be.

FIG. 7 shows the Ge concentration (atomic%) in the base layer on the horizontal axis and the switch time (ns) on the vertical axis.
FIG. 9 is a characteristic diagram showing the results of investigation on the correlation between bipolar transistors having base layers with various Ge concentrations. The contact length was set to satisfy the condition of the above inequality. As is clear from the characteristic line C in the figure,
When there is no Ge in the base layer (Ge = 0%), the switch time is 500 ns. When the Ge concentration in the base layer is about 2.5 to 2.8% in atomic density, the switch time is 400 ns. When the Ge concentration in the inside becomes 4% or more in atomic density, the switching time is reduced to 100 ns or less. In addition, when the switch time was measured for the element manufactured by the above method, it was found that the switch time could be suppressed to 100 ns or less in both cases of ON and OFF.

As a result, it has been found that the switching time is about 500 ns when the Ge concentration in the base layer is 2.5 atomic% or less, whereas the switching time is reduced to 100 ns or less in a region longer than that. . On the other hand, when the Ge concentration in the base layer became 15 atomic%, a leakage current occurred between the emitter and the base and between the collector and the base, and the transistor did not operate. Regarding the on-state voltage, there was no dependency on the Ge concentration in the operated transistor.

[0038]

According to the present invention, the width of the emitter electrode and the width of the base electrode are reduced to increase the total extension of the contact interface between the emitter electrode and the base electrode, that is, to reduce the contact length per unit area. By increasing the area, the area where the collector current flows per unit area can be increased.
This eliminates or substantially eliminates the region where the collector current which is likely to flow near the center of the width of the emitter electrode and the vicinity of the center of the width of the base electrode disappears or is substantially eliminated. Voltage drops.
In addition, the addition of Ge shortens the switching time and greatly reduces the switching loss.

Further, according to the present invention, since the doping concentration of the emitter layer is increased, there is an effect that a collector current which tends to concentrate in a region where the emitter electrode and the base electrode are close to each other is dispersed to the periphery. The distribution of the collector current is
Since the collector current easily flows to the central region of the width of the emitter electrode and the area where the current flows increases, there is a function of lowering the ON voltage. In addition, the addition of Ge shortens the switch time and reduces switch loss.

[Brief description of the drawings]

FIGS. 1A to 1E are schematic cross-sectional views for explaining steps of manufacturing a low-loss transistor according to the present invention.

FIG. 2 is a schematic plan view showing a low-loss transistor according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a low-loss transistor according to an embodiment of the present invention.

FIG. 4 is a schematic plan view showing a low-loss transistor according to another embodiment of the present invention.

FIG. 5 is a schematic plan view showing a low-loss transistor according to another embodiment of the present invention.

FIG. 6 is a characteristic diagram showing the result of an investigation on the relationship between the emitter doping concentration of ON voltage and the contact length of the transistor manufactured in Example 1.

FIG. 7 is a characteristic diagram showing the result of examining the dependence of the switching time on the Ge concentration of the transistor manufactured in Example 2.

FIG. 8 is a diagram illustrating an example of a common emitter circuit that operates a transistor as a switch element.

FIG. 9 is a schematic cross-sectional view showing a region where a collector current flows at a high density in order to explain the effect of the low-loss transistor of the present invention.

[Explanation of symbols]

 1A: substrate, 1: collector layer, 2: base layer, 3: emitter layer, 4: emitter electrode, 5: base electrode, 6: collector electrode, 14, 14A, 14B: transistor, 16: load, 17: power supply, 18: emitter terminal, 19: base terminal, 20: collector current high density region.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroji Nakano 1-8-1 Koura, Kanazawa-ku, Yokohama-shi, Kanagawa Prefecture, Mitsubishi Heavy Industries, Ltd. (72) Inventor Hiroshi Soda, Nishi-Awaji, Higashi-Yodogawa-ku, Osaka-shi, Osaka No. 3-56 No. 1-56 F-term in Sansha Electric Manufacturing Co., Ltd. (reference) 4M104 AA01 BB02 CC01 DD13 DD63 FF11 GG06 5F003 AP00 BA92 BB00 BB01 BB04 BB08 BB09 BC08 BE01 BE09 BE90 BF06 BH01 BH02 BM01 BP21 BP94

Claims (4)

[Claims] 1. A substrate, a collector layer composed of a first conductivity type Si film laminated on the substrate, and a base layer composed of a second conductivity type SiGe film laminated on the collector layer. An emitter layer made of a Si film of the first conductivity type laminated and formed on the base layer, and a part of the emitter layer is omitted or the conductivity type of a part of the emitter layer is inverted. A base electrode formed by joining a metal terminal to the missing or inverted portion; an emitter electrode formed by joining a metal terminal to the emitter layer; and a metal terminal attached to either the substrate or the collector layer. And a collector electrode formed by bonding the emitter electrode and the base electrode. The length X (mm / cm
² ) and the doping concentration of the emitter layer (atom / cm ³ )
Where Y is Y and the following relationship is satisfied: X ≧ 500 Y ≧ 9.0 × 10 ¹⁸ −3.2 × 10 ¹⁵ X 2. The Ge content of the base layer is 2.5 to 15% in atomic density.
A low-loss transistor as described. 3. The low-loss transistor according to claim 1, wherein the emitter electrode and the base electrode are arranged in a comb-like plane. 4. The low-loss transistor according to claim 1, wherein the on-state voltage is 1.0 V or less and the switch time is 100 nanoseconds or less.