JP2001222885A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of external output operation of read data for a memory block capable of performing parallel operation. SOLUTION: This circuit is provided with read buffers RB0-RB3 which can hold the read data read out from plural memory blocks BNK0-BNK7 capable of performing the parallel operation corresponding to a state that the read data can not be outputted from an external interface means to the outside, and selecting means 40, 41 and 42 which select the read data read out from the read buffer and give the read data to an external interface means when the state that the read data can not be outputted is eliminated. Thus, when there is the possibility of conflict of resources in the output operation of the read data, the read data is stored in the read buffer, and when there is no possibility, the read data can be outputted directly to the outside, thereby improving the throughput of output operation of the read data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a memory block and, more particularly, to a technique for improving the throughput of a data read operation in response to a read access request. The present invention relates to a technology effective when applied to an integrated circuit.

[0002]

2. Description of the Related Art In general, a storage hierarchy of a storage device in consideration of temporal and spatial locality of information reference is constituted by memories of plural levels having different access speeds and storage capacities. A DRAM (Dynamic Random Access Memory) with a low unit cost is used for the main memory, and an SRAM (Static Random Access Memory) or the like is provided at a level close to a processor or a CPU (Central Processing Unit). The cache memory to be used is arranged. The cache memory holds data localized in time and space with respect to data recently used by the processor, and makes it possible to improve throughput as compared with a data read operation from a lower level.

After completing the present invention, the present inventor was informed of the existence of JP-A-2-297791 and JP-A-6-195261. These documents describe dynamic memory (DRAM) and static memory (SRA).
M) on a one-chip semiconductor substrate and the DRAM
And the use of the SRAM as a cache memory. However, the purpose of the present invention and its configuration are not described therein.

[0004]

SUMMARY OF THE INVENTION The present inventor has studied on mounting a large number of DRAM modules having relatively slow access speeds together with logic circuits and making them available for a cache memory. For example, a DRAM integrated semiconductor integrated circuit that can be used as a level 3 (L3) cache memory of a microprocessor having a built-in level 1 (L1) and level 2 (L2) cache memories was studied.

According to the study of the present inventors, a large number of DRAMs
When trying to shorten the memory read cycle apparently by loading modules in parallel to enable parallel operation, consideration must be given to avoiding competition such as data output operation due to parallel operation. In this case, it has been found that it is useless to perform data buffering even when no data conflict occurs when trying to employ a data buffer to avoid data conflict.

In consideration of the data processing efficiency of the processor, the primary purpose is to improve the throughput of the read operation in response to the read access of the processor. At this time, the read operation of the cache memory includes copy back (or write back) associated with write access by the processor.
There is also a read operation for such a read operation, and in such a read operation, high throughput is not required in most cases. That is, copy-back is an operation to save the data to the main memory in order to replace a dirty cache line when a cache miss occurs. Therefore, when considering use as a cache memory,
The present inventors have clarified the necessity of increasing the read data throughput so that a difference in weight can be made depending on the use of the read data so that the logic scale of the logic circuit does not increase unnecessarily. Was.

[0007] In addition, for the write access of the processor, it is not so important to increase the speed of the write process responding to the write access. However, in consideration of the data processing efficiency of the processor, the request for the write access is accepted and the operation is started. Need to be released in a short time. In particular, D
In the case of a RAM, a refresh operation of stored information is required at each refresh interval, and it is necessary to prevent delay in acceptance of a write access request.

An object of the present invention is to provide a semiconductor integrated circuit capable of improving the read operation throughput in a configuration employing a data buffer in order to avoid data competition due to parallel operation of memory blocks.

Another object of the present invention is to provide a semiconductor integrated circuit capable of improving the read operation throughput so that the logic scale of the logic circuit does not increase unnecessarily.

Another object of the present invention is to provide a semiconductor integrated circuit which can easily accept a write access request regardless of the internal memory operation state.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] A read buffer is employed to avoid data competition due to parallel operation of memory blocks, thereby improving the read operation throughput. As a configuration for this, the semiconductor integrated circuit includes a plurality of memory blocks (BNK0 to BNK7) that can operate in parallel, and external interface means (I / O) that can input write data from the outside and output read data to the outside. F1) and a read buffer (RB0 to RB) capable of holding the read data read from the memory block in response to a state in which the read data cannot be output to the outside from the external interface means.
3) and selecting means for selecting the read data read from the memory block or the read data read from the read buffer when the output impossible state is resolved, and providing the read data to the external interface means ( 4
0, 41).

According to the above means, when one of the read data of the memory blocks which can be operated in parallel is output to the outside from the external interface means, if the read operation of the other memory block is performed, the read data becomes the external data. Since resource contention occurs at the output point, the data is temporarily stored in the read buffer, and after the previous data output operation is completed, the data can be output from the read buffer to the outside. Therefore, even if there is a read access request that would cause resource contention in the read data output operation, the read operation can be started without waiting for the request, and if there is no risk of resource contention, the read data can be immediately read from the buffer. Can be output to the outside, and in this regard, the throughput of the read data output operation can be improved.

If there is no resource contention when data is read from the memory block, the read data is directly output from the external interface means to the outside without passing through the read buffer. Waste of buffering the data once can be avoided, and in this respect it contributes to an improvement in the throughput of the read data output operation.

The read buffer may be composed of a memory having a smaller capacity and a higher speed than a memory block. For example, when the memory block is configured by a DRAM module, the read buffer may be configured by an SRAM module.

If the above configuration is described from the viewpoint of control, the semiconductor integrated circuit can hold a plurality of memory blocks (BNK0 to BNK7) that can operate in parallel and read data read from the memory blocks. Read buffer (RB0-RB3), external interface means (I / F1) capable of outputting read data output from the read buffer and read data output from the memory block to the outside, and reading from the memory block. In response to a state where the output read data cannot be output to the outside from the external interface means, the read data is held in the read buffer, and when the output impossible state is resolved, the read data is read from the memory block. Read data read out or read out from the read buffer. A control means for outputting data from said external interface means and (MCNT), the.

[2] In order to easily accept an external write access request regardless of the internal memory operation state, the semiconductor integrated circuit includes a plurality of memory blocks (BNK0 to BNK7) that can operate in parallel. ), External interface means (I / F1) capable of inputting write data from the outside, input write data input to the external interface means and holding the write data, and write data after the memory block is enabled for write operation. A write buffer (WB0-WB3) for supplying the data to the memory block;
Having.

Even if there is a write access request to a memory block during an internal operation such as refreshing or reading of stored information, write data can be buffered in the write buffer in advance, so that write access is performed. It is possible to release the processor and the like from the write access operation in a short time. In consideration of the data processing efficiency of the processor, etc., it is not as important to increase the speed of the write process on the memory side in response to the write access of the processor. Since it does not exist, it contributes to improvement of data processing efficiency of the entire system.

The write buffer may be constituted by a memory having a smaller capacity and a higher speed as compared with the memory block, and as in the above, for example, when the memory block is constituted by a DRAM module, the write buffer may be constituted by an SRAM module.

If the above configuration is mainly described from the viewpoint of control,
The semiconductor integrated circuit includes an external interface unit (I / F1) capable of externally inputting write data, a write buffer (WB0 to WB3) for inputting write data input to the external interface unit, and a write buffer for writing data from the write buffer. A plurality of memory blocks (BNK0 to BNK7) to which data is supplied and write data supplied to external interface means in response to an external access request are stored in the write buffer, and the memory block to be accessed performs a write operation. Control means (MCNT) for waiting for the write data to be supplied to the memory block from the write buffer.

[3] The semiconductor integrated circuit having both the read buffer and the write buffer has a plurality of memory blocks (BNK0 to BNK0) which can operate in parallel.
7) an external interface means (I / F1) capable of externally inputting write data and outputting read data to the outside; inputting and holding the write data input to the external interface means; A write buffer (WB0-WB3) for supplying write data to the memory block after the block is enabled for write operation;
A read buffer (R) capable of holding read data read from the memory block in response to a race condition in which the read data cannot be output to the outside from the external interface means.
B0 to RB3) and the read data read from the memory block or the read data read from the read buffer when the non-outputtable conflict condition is resolved and the external interface means (4
0, 41).

[4] Assume use as a cache memory that can be connected to both lower-level and higher-level storage hierarchies. At this time, the semiconductor integrated circuit includes a plurality of memory blocks (BNK0 to BNK7) that can operate in parallel,
First external interface means (I) capable of inputting write data from the outside and outputting read data to the outside
/ F1) and second external interface means (I / F2) capable of inputting write data from the outside and outputting read data to the outside. Further, the semiconductor integrated circuit inputs and holds the write data input to the first or second external interface means, and supplies the write data to the memory block after the memory block is enabled to perform a write operation. (WB0-WB
3) holding read data to be output from the second external interface means, and a race condition in which read data to be output from the first external interface means cannot be output from the first external interface means; A read buffer (RB0 to RB3) capable of holding read data stored in the memory block and read data read from the memory block or the read buffer read from the memory block when the output impossible race condition is resolved. Selecting means (40, 41) for selecting the read read data and providing the selected read data to the first external interface means.

In this configuration, the first external interface is connected to an upper storage hierarchy, and the second external interface is connected to a lower storage hierarchy. The basic operation of the read buffer and the write buffer for the read / write access request of the processor is the same as described above. In particular, the output of read data to the lower storage hierarchy via the second external interface means is only the data output via the read buffer. This is because a read operation for copy back (or write back) accompanying write access by the processor is assumed as output of read data to the lower storage hierarchy. Copyback is an operation to save the data to the main memory in order to replace a dirty cache line in the event of a cache miss, so high throughput is not required in most cases in such a read operation.
A data path for bypassing the read buffer and directly outputting read data from the second external interface means and a logic circuit therefor are omitted, so that the logic scale of the circuit is not unnecessarily increased.

Considering the application of the semiconductor integrated circuit to a multiprocessor system, another processor is also connected to the lower storage hierarchy side, and the semiconductor integrated circuit can be accessed by another processor. It is assumed that it is operated. To cope with this, the first and second external interface means only need to be able to individually input an access request and an access address to the memory block from the outside.

In consideration of resource contention when read data is supplied from the lower storage hierarchy to the upper storage hierarchy through the semiconductor integrated circuit, data is input from the second external interface means. Further, a memory buffer (54) capable of storing and holding the data and outputting the held data to the outside from the second external interface means increases the convenience of the semiconductor integrated circuit as the cache memory.

[5] When the memory block is composed of, for example, a DRAM, the access time of the DRAM can be shortened in a well-known page mode or static column mode. Furthermore, in order to shorten the apparent access time in a memory block constituted by a DRAM, serial input is subjected to serial / parallel conversion, and data output is subjected to parallel / serial conversion. That is, the semiconductor integrated circuit includes a memory cell array (10), a row selection circuit (11), a column selection circuit (12, 13), and a serial / parallel conversion circuit (2).
1), light amplifier (17W), main amplifier (17W)
R), including a memory block having a parallel / serial conversion circuit (25). The memory cell array has a plurality of memory cells each having a selection terminal connected to a word line and a data input / output terminal connected to a bit line. The row selection circuit responds to a change in the row address strobe signal in synchronization with a clock signal, and selects a word line specified by the row address signal. The column selection circuit responds to a change in the column address strobe signal in synchronization with the clock signal, and selects a plurality of bit lines specified by the column address signal in parallel. The serial / parallel conversion circuit converts write data serially input from the write buffer into parallel data in synchronization with a clock signal. The write amplifier outputs the output of the serial / parallel conversion circuit in parallel to the plurality of bit lines selected by the column selection circuit. The main amplifier amplifies parallel data output in parallel from the plurality of bit lines selected by the column selection circuit. The parallel / serial conversion circuit converts the parallel data supplied from the main amplifier into serial data in synchronization with a clock signal, and outputs the serial data to the read buffer and the selection means.

The memory block receives the column address strobe signal, which is changed at a cycle of n (a positive integer of 2 or more) times the clock signal cycle, and outputs a memory cell array every cycle at which the column address signal is changed. Read out from the
A plurality of serial data subjected to serial conversion is output from the memory block, and is input to the memory block in synchronization with a clock signal cycle, and parallel data subjected to serial / parallel conversion is written to the memory cell array. As described above, the speed of the memory operation can be increased by the access specification of changing the column address strobe signal once every n cycles of the clock signal.

It is preferable that a serial data input path of the serial / parallel conversion circuit and a serial data output path of the parallel / serial conversion circuit are independently provided. In a read operation, data is read from the memory cell array in response to a change in the column address strobe signal, and then serial data is output from the memory block in parallel / serial conversion time. In a write operation, the column address strobe signal is output. Before writing parallel data to the memory cell array in response to the change in the data, the operation of converting serial data input to the memory block into parallel data must be completed in advance. At this time, when a write operation is instructed following the read operation, the serial data for the write operation is sequentially and serially input to the memory block in advance in parallel with the operation of outputting the serial data by the read operation from the memory block. It is often anticipated that action must be taken. That is, there is a high probability that the serial data output timing from the memory block and the serial data input timing to the memory block overlap. As described above, by independently providing the serial data input path and the serial data output path of the memory block, it is possible to avoid data collision and realize efficient processing even when such processing overlaps. Become.

[6] When the propagation delay of read data is considered, it is preferable to adopt the following layout configuration for the semiconductor integrated circuit. For example, a center pad configuration in which external connection electrodes such as signal input / output bonding pads or bump electrodes are arranged in the center of the chip is assumed. At this time, the memory blocks are opposed to each other with a space between them on the semiconductor chip. A read buffer capable of holding read data read from the memory block and a write buffer capable of holding write data given to the memory block are arranged between the opposed memory blocks. External interface means is arranged near the read buffer and the write buffer. An external connection electrode is provided near the external interface means. The write buffer inputs and holds the write data input to the external interface unit, and supplies the write data to the memory block after the memory block is enabled to perform a write operation. The read buffer is capable of holding read data read from the memory block in response to a state where the read data cannot be output from the external interface means to the outside.

[0031]

FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention as a whole. Although the semiconductor integrated circuit 1 shown in FIG. 1 is not particularly limited, it is a semiconductor integrated circuit assumed to be used as an L3 cache memory.
8 memory blocks BNK0 to BNK7, 4 write buffers WB0 to WB3, 4 read buffers RB
0 to RB3, an upper layer interface block I / F1 connected to an upper storage layer (for example, a processor bus);
A lower layer interface block I / F2 connected to a lower storage layer (for example, a memory bus);
Has CNT.

The upper layer interface block I /
F1 is connected to a processor bus or the like to which a processor having a built-in L1 cache memory and an L2 cache memory is connected, and inputs access control information including an access control signal and an access address signal. Data is input and output in 72 bits in parallel.

The lower layer interface block I /
F2 is connected to a lower storage hierarchy, such as a memory bus to which a main memory or an L4 cache memory is connected,
For example, data is input and output in 72 bits in parallel. Although not particularly limited, assuming a multiprocessor system, the lower-layer interface block I / F2 inputs access control information from another processor so that the processor can be accessed from another processor than the processor in the upper storage layer. Thus, the memory blocks BNK0 to BNK7 can be accessed.

The memory control circuit MCNT receives the access control information, decodes a part of the address information included in the access control information, determines the memory block to be accessed, and provides a local memory address and an access control signal to the memory block to be accessed. Is output to control the operation of the memory block.

Memory block BNK0 shown representatively
Is sequentially latched in four write registers (ILTs) 22 by serially inputting write data in units of 72 bits (8 bytes), and DR is written in 288 bits (32 bytes) in parallel.
The AM core 8 is made writable, and the DRAM core 8
The read data read in 288 bits in parallel from
The data is latched in a read register (OLT) 26 in units of 2 bits, and the output of the read register 26 is sequentially selected by a selector 27 so that read data can be output in series in units of 72 bits. Therefore, the memory block BNK0
Can input / output data at a speed four times the access time of the DRAM core 8. In this specification, one byte includes 8-bit data and 1-bit parity data.

Upper layer interface block I / F1
Is supplied to the memory block BNK0 (BNK1 to BNK7) via the write buffer WB0 (WB1 to WB3).

The memory block BNK0 (BNK1 to BN
The output path of the read data read out from K7) is an upper path, an upper buffering path, and a lower buffering path. The upper through route is
This is a path that is output from the upper layer interface block I / F1 to the upper storage layer via selectors 40 and 41 schematically shown. The upper buffering path is a path for outputting the read data temporarily stored in the read buffer RB0 (RB1 to RB3) from the upper layer interface block I / F1 to the upper storage layer via the selectors 40 and 41. The lower buffering path is a path for outputting the read data temporarily stored in the read buffer RB0 (RB1 to RB3) from the lower layer interface block I / F2 to the lower storage layer via the selector 42. No through route to the lower hierarchy is provided.

The read buffers RB0 to RB3 and the write buffers WB0 to WB3 are constituted by SRAMs. Access to these SRAMs is enabled in units of one cycle defined by a system clock signal. Each of the read buffers RB0 to RB3 and each of the write buffers WB0 to WB3,
The RAM can be configured similarly to a known SRAM. The SRAM includes, but is not limited to, a memory array including a plurality of static memory cells, a plurality of word lines, and a plurality of complementary data line pairs, an address decoder for selecting a predetermined word line in response to an address signal, And a data output circuit for outputting the amplified data.

As described below, each SRAM has a configuration in which 72 memory cells are simultaneously selected in response to a set of input address signals. Each static memory cell includes a pair of CMOS inverters including an N-channel MOSFET and a P-channel MOSFET, and an information storage unit formed by cross-connecting the input and output of the pair of CMOS inverters. And a selection transistor including a plurality of N-channel transfer MOSFETs for selecting the information storage unit. The gate terminals of the plurality of select transistors are selectively coupled to one or more word lines, and the source / drain paths of the plurality of select transistors are connected to one or more corresponding pairs of complementary data lines. And multiple input ports
It is configured as a memory cell with multiple output ports. The read buffers RB0 to RB3 and the write buffer WB
Each of the SRAMs constituting each of 0 to WB3 has a configuration of 128 words × 72 bits, although not particularly limited.

It will be easily understood by those skilled in the art that the configuration itself of the memory cell having multiple input ports and multiple output ports can be variously changed.

FIG. 2 illustrates the details of the output path of the read data in the semiconductor integrated circuit 1. The memory blocks BNK0 and BNK1 share the read buffer RB0 and the write buffer WB0. Similarly, the memory blocks BNK2 and BNK3 share the read buffer RB1 and the write buffer WB1, and
4, BNK5 share the read buffer RB2 and the write buffer WB2, and the memory blocks BNK6, BNK7
Share the read buffer RB3 and the write buffer WB3. The write buffers WB0 to WB3 and the read buffers RB0 to RB3 have, but not particularly limited to, two read ports and two write ports. Each port is an 8-byte parallel access port.

A selector 41Aa for selecting one of read data from one memory block BNK0 and read data from the other memory block BNK4.
Is provided. Similar selectors 41Ab to 41Ad are provided for the other memory blocks. S1
0 to S13 are selection control signals of the selectors 41Aa to 41Ad. A selector 40Aa for selecting one of the read data output from the read buffer RB0 and the read data selected by the selector 41Aa is provided. Similar selectors 40Ab to 40Ad are provided for other memory blocks. S20-S2
Reference numeral 3 is a selection control signal for the selectors 40Aa to 40Ad. Outputs of the selectors 40Aa to 40Ad are selected by a selector 41B and supplied to an upper layer interface block I / F1. The operation of the selector 41B is controlled by 2-bit selection signals S30A and S30B. The selector 42 selects the output from one of the read ports of the read buffers RB0 to RB3 and supplies the output to the lower layer interface block I / F2. The operation of the selector 42 is 2
It is controlled by bit selection signals S31A and S31B.

FIG. 3 illustrates control signals generated by the memory control circuit MCNT. Memory control circuit MCNT
Outputs an address signal ADRS, a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and the like for each of the memory blocks BNK0 to BNK7, and outputs an address signal ADRS, a memory enable signal MS, for each of the read buffers RB0 to RB3.
Read / write signal R / W and port select signal PS
L and outputs an address signal ADRS, a memory enable signal MS, a read / write signal for each of the write buffers WB0 to WB3.
A write signal R / W and a port select signal PSL are output, and the selector select signals S10-S13, S20-S
23, S30A, S30B, S31A, and S31B, and output enable signals OEP1 and OEP2 for the interface blocks I / F1 and I / F2. The memory control circuit MCNT inputs access control information from both the upper storage hierarchy and the lower storage hierarchy, and converts a required control signal from the above control signals into a predetermined control signal so as to realize an operation specified by the input access control information. Activation control is performed at the timing. The memory control circuit MCNT outputs signals MRef0 to MRef7 relating to the refresh operation period of the memory blocks BNK0 to BNK7 to each of the memory blocks BN.
It is input from K0 to BNK7.

As shown in FIG. 4, the access control information 43 includes an address designating section 43A and an operation designating section 4.
3B. The address specification unit 43A includes specification information of the memory blocks BNK0 to BNK7 to perform reading and writing, and address information in the memory blocks. The operation specifying unit 43B reads / writes, for example, 8 bytes of data from the address specified by the address specifying unit, and reads / writes 16 bytes of continuous data from the address specified by the address specifying unit to the semiconductor integrated circuit 1. 32 consecutive from the address specified by the address specifying unit
Specifies operations such as reading / writing of byte data.

The memory control circuit MCNT accepts an external access request to operate the memory blocks BNK0 to BNK7 in parallel within a range in which resources do not compete within the semiconductor integrated circuit 1. The memory control circuit MCNT includes memory blocks BNK0 to BNK7.
And one read buffer selected from the read buffers RB0 to RB3 is connected to the interface blocks I / F1 and I / F2 to control the external output of read data.

FIG. 5 representatively shows a main control procedure of the memory control circuit MCNT in response to an external access request.

In response to a write access request, the memory control circuit MCNT pre-writes the write data to the corresponding write buffer among the write buffers WB0 to WB3 regardless of the presence or absence of an internal operation such as refreshing by the memory block to be written. The control for taking in is performed (T1). Thereafter, it is determined whether or not the write target memory block is not performing an internal operation such as refreshing and is capable of a write operation (T2), and data is written to the target memory block after the determination of the write operation is possible (T2). T3).

FIG. 6 shows an example of a write operation when a refresh operation is interposed in the middle of a write access. In FIG. 6, the memory block BNK0 is to be written. 〜 Means an access unit given from outside the semiconductor integrated circuit 1, and the data of the access unit is 72 bits in parallel. In the operation cycles 4 to 9 of the system, the memory block BNK0 performs a refresh operation, and is readable / writable before and after the refresh operation. The write data is sequentially delayed by one cycle with the write buffer WB0
It is stored in. The write data once stored in the write buffer WB0 is the write target memory block BN.
If K0 is readable / writable, write data is sequentially supplied to the write register 22 of the memory block BNK0 every cycle. When the data in the access unit is latched in the write register 22, the memory block BNK0 has already started the refresh operation. The memory control circuit MCNT suspends the data transfer from the write buffer WB0 to the write register 22, and waits for the end of the refresh operation. Meanwhile, the writing of the write data to the write buffer WB0 is continued. When the refresh operation of memory block BNK0 is completed in operation cycle 9, memory control circuit MCNT transmits strobe signals RAS and CA to memory block BNK0 in cycle 10.
S and WE are asserted to give a write address, and data of the access unit ~ is taken by the DRAM core 8 over four cycles.
Write to. In parallel with the writing to the DRAM core 8, the write data of the following access units is sequentially transferred to the write register 22. The memory control circuit MCNT asserts the strobe signals RAS, CAS, and WE to the memory block BNK0 in cycle 14 to give a write address, and writes the data of the access unit to the DRAM core 8 over four cycles. As a result, the processor in the upper storage hierarchy that instructs the write access of the access unit to is released from the current write access processing in cycle 8, and is not affected by the refresh operation interposed in the memory block BNK0.

FIG. 7 shows an example of the write operation when the write buffer WB0 is not provided. When the refresh operation is started in the DRAM core 8 when there is no write buffer WB0, the processor on the upper storage hierarchy side instructing the write access outputs the write address and the write data in cycle 4, that is, issues the write access request. It must suspend and wait while detecting the completion of the refresh operation. After cycle 9 in which the refresh operation has been completed, the processor on the upper storage hierarchy side again
A write access request is issued, and addresses and data of access units are sequentially output from cycle 10. As a result, the write data writing of the access unit to the DRAM core 8 of the memory block BNK0 is completed in cycle 19, but the processor in the upper storage hierarchy that instructs the write access is not released from the write access processing until cycle 13. As apparent from comparison with FIG. 6, the semiconductor integrated circuit 1 serving as the L3 cache memory has the write buffers WB0 to WB3, so that the data processing efficiency of the processor of the upper hierarchy can be remarkably improved. .

On the other hand, the memory control circuit MCNT transfers read data read from the memory blocks BNK0 to BNK7 to the interface blocks I / F1, I / F2.
When controlling the operation of outputting to the outside through the data read operation, the selection of the output path of the read data, that is, the selection control of the upper through path, the upper buffering path, and the lower buffering path is performed to perform the data read operation. Improve throughput.

Whether the upper through-path or the upper buffering path is selected is determined by the memory control circuit MCNT as to whether or not there is a risk of resource contention.

That is, the memory control circuit MCNT responds to a read access request as shown in FIG.
Data is read from the DRAM core 8 of the memory block to be accessed (T4), and it is determined whether there is a resource conflict when the read data is output from the upper layer interface block I / F1 to the outside (T5). In some cases, that is, when it is impossible to output the read data from the upper layer interface block I / F1 to the outside, the read data is held in the corresponding read buffers RB0 to RB3 (T6). . When the output impossible state has been resolved, the read data read from the memory blocks BNK0 to BNK7 or the read buffer RB0 to RB0
The read data read from the RB3 is output from the upper layer interface block I / F1 to the outside (T7).

FIG. 8 shows an example of a read operation using the read buffers RB0 to RB3. In FIG. 8, the processor in the upper storage hierarchy issues access requests A to D continuously in operation cycle units of the system. The access request A is composed of 32-byte data A-0, A-1, A-2, A-continuous from the address A of the memory block BNK0.
This is a read access request for reading No.3. Similarly, the access request B is a sequence of 32 bytes of data B-0, B-1, B-2,... Starting from the address B of the memory block BNK4.
Read access request for reading B-3, access request C
Are 3 consecutive from the address C of the memory block BNK1.
A read access request for reading out 2-byte data C-0, C-1, C-2, and C-3, and an access request D are 32-byte data D-0, D-1,..., Continuous from address D of memory block BNK3. This is a read access request for reading D-2 and D-3.

When the access request A is received, the memory control circuit MCNT reads out the 288-bit data designated by the address A from the DRAM core 8 of the memory block BNK0 in parallel and latches it in the read register 26. Then, the read register 26 is sequentially selected, and the read data A-0, A-1, A-2, and A-3 are output from the memory block BNK0 in units of 8 bytes. The output of the read data is performed in operation cycle units (one cycle unit) of the system. At this time, the upper layer interface block I / F1 is not performing an output operation. According to this, the memory controller MCNT selects the selectors 41Aa, 4Aa, 4A
Output data A-0, A-1, A-2, and A-3 from the memory block BNK0 are directly transmitted to the upper layer interface block I / F1 by 0Aa and 41B and output to the outside.

In parallel with this output operation, the next access request B is issued one cycle later, and the memory block B
From NK4, read data B-0, B-1, B-2,
B-3 is output. The output read data is sequentially stored in the read buffer RB0. Similarly, the memory block BNK1 is transmitted by the next succeeding access request C.
From the read data C-0, C-1, C-2, C-3
Is output and stored in the read buffer RB1, and the memory block BN is generated by the next succeeding access request D.
Read data D-0, D-1, D-2, D sequentially from K3
-3 is output and stored in the read buffer RB3.
During the operation of holding the subsequent read data in the read buffer, when the output of data to the outside by the upper layer interface block I / F1 is completed, the read data of the access request following this is read from the read buffer. Output to the outside. That is, data A
After -3, read data B-0, B-1, B-2, and B-3 are sequentially output from the read buffer RB0, and are selected by the selectors 40Aa and 41B, and are output from the upper layer interface block I / F1. Send data to outside. Thereafter, data C-0 to D-3 are continuously output to the outside.

On the other hand, as shown in FIG. 9, if there is no read buffer, the next access request cannot be accepted until all the read data relating to the first access request A is output to the outside. In different memory blocks, at least the output operation of the read register must not conflict.

As is clear from this, by employing the read buffers RB0 to RB3, it is possible to receive a subsequent read access request in advance and precede the internal operation of the memory block.
By employing an SRAM having an access speed higher than that of the AM, it is possible to improve the throughput of the data read operation without slowing down the buffered data output operation.

Further, the memory blocks BNK0 to BNK7
If there is no resource contention when data is read from the read interface, the read data is directly sent to the upper layer interface block I without passing through the read buffers RB0 to RB3.
Since the data is output from / F1 to the outside, wasteful data buffering can be avoided even when no data conflict occurs. In this respect, the throughput of the read data output operation is improved.

Next, a description will be given of a case where the semiconductor integrated circuit 1 is applied to a cache memory system.

FIG. 10 shows a first example of the cache memory system. The semiconductor integrated circuit 1 is used as an L3 cache memory, and is disposed between the processor 50 and the main memory 51. A processor bus 52 is connected to the upper-layer interface block I / F1 of the semiconductor integrated circuit 1, inputs and outputs data to and from a processor, and inputs access control information output from the processor 50. A memory bus 53 is connected to the lower layer interface block I / F2 of the semiconductor integrated circuit 1, and inputs and outputs data to and from the main memory 51.
The access control information for the main memory 51 is, although not particularly limited, information issued by the processor 50.

The processor 50 is connected to the CPU 50A together with L1.
Cache memory 50B, L2 cache memory 50C
And a tag control logic (TAG) 50D for the L3 cache memory. Semiconductor integrated circuit 1
Are positioned as a data memory section of the L3 cache memory. The tag control logic 50D has information that associates an index address with a tag address of a cache entry for each cache line of the semiconductor integrated circuit 1 as an L3 cache memory. Further, each cache line has a valid bit indicating the validity of the cache line, a dirty bit indicating the necessity of copy-back or write-back to the lower storage hierarchy when replacing the cache line, and the like.

In FIG. 10, the lower storage hierarchy of the semiconductor integrated circuit 1 is not limited to the main memory, but may be an L4 cache memory. The tag control unit of the L4 cache memory may be configured inside the processor 50.

FIG. 11 shows a data flow focusing on the read access operation of the processor in the cache memory system of FIG. If the semiconductor integrated circuit 1 has a cache hit by the tag control logic 50D when the L1 cache memory 50B and the L2 cache memory 50C incorporated in the processor 50 have a cache miss, the processor 50 performs read access to the semiconductor integrated circuit 1 as a target. Request. The path of the access control information at this time is as follows. As described above, if there is no resource contention, the read data is stored in the memory blocks BNK0 to BNK.
It is returned directly from K7 to the processor 50 (path). When there is resource contention, the read data is temporarily held in one of the read buffers RB0 to RB3, and the read buffers RB0 to RB3 are generated at a timing when no resource contention occurs.
B3 is returned to the processor 50 (path '). When the semiconductor integrated circuit 1 also has a cache miss, the processor 50 gives access control information to the main memory 51 (path), and read data of the main memory 51 is returned to the processor 50 (path).

At this time, if a bus conflict occurs on the route due to the influence of another circuit module, the read data cannot be sent from the main memory 51 to the processor 50. Even if the bus contention is resolved, the processor 50 must again issue an access request to the main memory 51 to access the main memory 51 having a slow access speed, such as a DRAM, again. Therefore, as illustrated in FIG. 11, the read buffer RB0
Like RB3, a high-speed accessible memory buffer (MB) 54 composed of an SRAM or the like may be arranged between the main memory 51 and the processor 50.

The memory buffer 54 may be built in the semiconductor integrated circuit 1. The memory buffer 54 may input and hold data from the lower layer interface block I / F2, and output the held data from the upper layer interface block I / F1 to the outside. The read data output of the memory buffer 54 and the read data output of the memory blocks BNK0 to BNK7 may be exclusive. For example, the processor 50 may directly specify the memory buffer 54 to operate.

FIG. 12 shows a data flow focusing on the operation in the write access of the processor in the cache memory system of FIG. In the write access of the processor 50, if the semiconductor integrated circuit 1 hits the cache by the tag control logic 50D when the L1 cache memory 50B and the L2 cache memory 50C incorporated in the processor 50 have a cache miss, the processor 50 Request write access targeting 1 as a target. The path of the access control information at this time is as follows. As described above, the write data is temporarily stored in one of the write buffers WB0 to WB3, and when the memory block to be written becomes operable, the write data is written from the write buffer to the memory block (path). The semiconductor integrated circuit 1 has a write buffer W
Since B0 to WB3 are provided, even if a refresh operation of a memory block is interposed in the middle of a write request, the write request does not have to be interrupted in the middle. Therefore, the processor 50 can be released from the writing process quickly. When the semiconductor integrated circuit 1 also has a cache miss,
The processor 50 stores the access control information in the main memory 51.
(Write) and write data to the main memory 51 (path).

FIG. 13 shows a data flow focusing on replacement of a cache line in the cache memory system of FIG. When replacing a predetermined cache line of the memory blocks BNK0 to BNK7 in response to a cache miss of the semiconductor integrated circuit 1 during a write access or a read access, when the dirty bit of the cache line is enabled, The cache line entry must be copied back to the lower hierarchical area of the corresponding tag address. The data to be copied back is from the memory blocks BNK0 to BNK7 to the read buffers RB0 to RB.
B3, which is actually a DR with a slow access speed
There is no need to wait for actual copy back to the main memory 51 composed of AM. The data of the new cache entry to be replaced can be written from the main memory 51 to the write buffer W without waiting for the data to be copied back to be transferred to the read buffers RB0 to RB3.
B0 to W3 may be written. As a result, the throughput of the final data read by the processor 50 can be improved even when the replacement of the cache line is required.

As described with reference to FIGS. 1 and 2, the connection between the lower layer interface block I / F2 and the memory blocks BNK0 to BNK7 is established by the read buffer R.
Only a route via B0 to RB3 is provided, and a through route such as an upper layer is not provided. Copy-back is an operation to save the data to the main memory in order to replace a dirty cache line at the time of a cache miss. Therefore, in such a read operation, a high throughput is not required in most cases, and therefore, bypasses the read buffers RB0 to RB3. By omitting a data path for directly outputting read data from the lower-layer interface block I / F2 and a logic circuit therefor, the logic scale of the semiconductor integrated circuit 1 does not increase unnecessarily.

FIG. 14 shows a second example of the cache memory system. The semiconductor integrated circuit 1 can be used as a main memory of the processor 50.
In this case, it is not necessary to use the lower layer interface block I / F2 of the semiconductor integrated circuit 1.

FIG. 15 shows a third example of the cache memory system. The cache memory system shown in the figure is an example applied to a multiprocessor system, and is not particularly limited.
0-2, each of which is connected to an L3 cache memory 1-1, 1-2 constituted by the semiconductor integrated circuit 1,
The L3 cache memories 1-1 and 1-2 are connected to the main memory 51 via a bus switch circuit 55.

The L3 cache memory 1-1, 1-2
Are connected to the processors 50-1 and 50-2 via processor buses 52-1 and 52-2 connected to the upper-layer interface block I / F1, and are connected to the processors 50-1 and 50-2.
0-2, input / output data, and processor 5
The access control information output from 0-1 and 50-2 is input. The lower layer interface block I / F2 of the L3 cache memories 1-1 and 1-2 is connected to the memory bus 5
The main memory 51 is connected to the bus switch 55 via the memory bus 53-3 via the memory switch 53-3.

The bus switch circuit 55 selectively realizes the first to fourth bus connection states, although not particularly limited. The first bus connection state transmits access control information output from the processor 50-1 to the main memory 51, and performs data input / output between the main memory 51 and the L3 cache memory 1-1 or the processor 50-1. enable. The second bus connection state transmits access control information output from the processor 50-2 to the main memory 51, and performs data input / output between the main memory 51 and the L3 cache memory 1-2 or the processor 50-2. enable. The third bus connection state stores the access control information output from the processor 50-1 in the L3 cache memory 1-2.
To the L3 cache memory 1-2 and the processor 5
Data input / output with the 0-1 or L3 cache memory 1-1 is enabled. The fourth bus connection state transmits the access control information output from the processor 50-2 to the L3 cache memory 1-1, and transmits the access control information to the L3 cache memory 1-1.
1 and processor 50-2 or L3 cache memory 1-
2 enables data input / output.

The L3 cache memory 1-2 stores the third
In response to the bus connection state, the lower-level interface block I / F2 receives access control information output from the processor 1-1, and is enabled to operate as a cache memory. Similarly, the L3 cache memory 1-1 is
In order to respond to the fourth bus connection state, the cache memory can be operated by receiving the access control information output from the processor 1-2 to the lower hierarchical interface block I / F2.

FIG. 16 shows a chip layout of the semiconductor integrated circuit 1. 1 like single crystal silicon
The central portion of the main surface of each of the rectangular semiconductor chips 1A is a logic circuit region 1B, and memory blocks BNK0 to BNK3 and memory blocks BNK4 to BNK are located above and below, respectively.
7 are arranged separately. At the end of the logic circuit area 1B, the read buffers RB0 to RB3 and the write buffer WB
0 to WB3 are separately arranged. Read buffer RB
Interface blocks I / F1 and I / F2 are separately arranged between the write buffers WB0 to RB3 and the write buffers WB0 to WB3. Many external connection electrodes (not shown) such as bonding pads or bump electrodes are arranged near the interface blocks I / F1 and I / F2. Although not particularly limited, the interface blocks I / F1, I / F
During F2, the buffer memory (M
B) 54 is arranged. Although not shown, other logic circuits are also arranged in the logic circuit area 1B.

By adopting the layout configuration of FIG. 16, the read buffers RB0 to RB3 are
Interface block I / F than NK0 to BNK7
1, I / F2 and external connection electrodes. Thereby, the read buffers RB0 to RB3 can be used for the operation delay and the propagation delay of the path for directly outputting read data from the read registers of the memory blocks BNK0 to BNK7 to the outside without passing through the read buffers RB0 to RB3.
The operation delay and the propagation delay of the path for outputting read data from B3 to the outside can be prevented from being extremely increased. Therefore, the layout configuration contributes to an improvement in the throughput of the data read operation.

FIG. 17 shows a detailed example of a memory block. Memory block BN representatively shown in FIG.
K0 has a memory cell array 10 in which dynamic memory cells (not shown) are arranged in a matrix. A dynamic memory cell includes a capacitor for storing information,
A selection transistor comprising an N-channel MOSFFT coupled thereto; a selection terminal which is a gate of the selection transistor is connected to a word line WL; and one end of a source / drain path of the selection transistor is coupled to the capacitance element. , The other end of the source-drain path, that is, the data input / output terminal is connected to the complementary bit line BL. Although not particularly shown, the complementary bit line has a folded bit line structure centered on the sense amplifier, and a precharge circuit and the like are arranged between the complementary bit lines.

The row decoder 11 is a row selection circuit that selects a word line WL specified by the dress row address signal RASADR in response to a falling transition of the row address strobe signal RAS. The selection of the complementary bit line BL is performed by the column decoder 13 and the column switch circuit 12. The column decoder 13 generates a column selection signal 14 for selecting a plurality of complementary bit lines specified by the column address signal CASADR in parallel in response to a falling transition of the column address strobe signal CAS. Further, the column decoder 13 activates the write signal 15W in response to a write operation instruction by the low level of the write enable signal WE, and activates the read signal 15R in response to an instruction of the read operation by the high level of the write enable signal WE. Become The column switch circuit 12 performs a switching operation by the column selection signal 14 to switch the 32-bit (288-bit) complementary bit lines indicated by the signal 14 to the 32-byte complementary write data lines WIO and 32.
The data is passed through the complementary read data lines RIO for bytes.

The 32-byte write data output from the write amplifier 17W is supplied in parallel to the complementary write data line WIO. The complementary read data line RIO supplies 32-byte read data to the main amplifier 17R in parallel. Write amplifier 17W is 288
And amplifying signals for the 288-bit write data DIN <0> to DIN <3> input in parallel in response to the activation of the write signal 15W. The parallel output operation is enabled by 288 bits to WIO. The main amplifier 17R has 288 read amplifying circuits, and in response to the activation of the read signal, converts the amplified signal corresponding to the input from the complementary read data line RIO into 288-bit read data MAOUT <0. > To MAOUT <3>. The data DIN
, DIN <3> are each 8 bytes, and similarly, the data MAOUT <0>,.
Are also 8 bytes each.

A serial / parallel conversion circuit 21 is arranged between the input path 20 for the write data WD and the write amplifier 17W. Although not particularly limited, the write data W
D is supplied in 8-byte parallel. Series-parallel conversion circuit 2
1 has the four write registers 22 and the data latch control circuit 23. The input terminals of the write register 22 are commonly connected to the input path 20, and the output terminals are individually coupled to the input terminals of the write amplifier circuit of the write amplifier 17W. The data latch control circuit 23 generates a 4-bit latch control signal DINL <3: 0> by decoding the 2-bit latch control data DLAT <1: 0> in synchronization with the clock signal CLK, and generates a corresponding write register. 22 is performed. Latch control data LATD <
1: 0> is sequentially incremented and changed, so that the write data WD input in parallel in units of 8 bytes is sequentially latched by the four write registers 22 in synchronization with the clock signal CLK, and the four write registers 22 are written. Register 22
Is output in 32 bytes in parallel and write data DIN <0
> To DIN <3> are obtained.

Output path 2 of read data MUXOUT
A parallel / serial conversion circuit 25 is disposed between the main amplifier 9 and the main amplifier 17R. Parallel / serial conversion circuit 25
Has four read registers 26, an output selector 27, and a selection control circuit 28. The input terminals of the read register 26 receive read data M from the main amplifier 17R, respectively.
AOUT <0> to MAOUT <3> are input. The latch timing of the read register 26 is determined by the latch control signal P
It is controlled by DOLTT. Latch control signal PDOLTT
Is latched by the read data MAOUT <0> to M according to the data read from the memory cell.
The output control circuit 30 described later controls the timing so that the timing after AOUT <3> is determined.

The selector 27 includes a read register 26
The output data DOUT <0> to DOUT <3> are selected by the selection control signals MSEL <3: 0> in units of 8 bytes and output to the output path 29. The selection control circuit 28 generates a 4-bit selection control signal MSEL <3: 0> by decoding the 2-bit selection control data MUXSEL <1: 0> in synchronization with the clock signal CLK. The selection control data MUXSEL <1: 0> is sequentially incremented and changed, so that the output data DOUT <0
> To DOUT <3> are sequentially output to the output path 29 in units of 8 bytes in synchronization with the clock signal CLK to obtain read data MUXOUT.

The output control circuit 30 generates the latch control signal PDOLTT according to the CAS latency. CA
The S latency is a delay time from the next clock cycle to the time when the data input of the parallel / serial conversion circuit 25 is determined when responding to the falling change of the column address strobe signal CAS in a data read operation in clock synchronization. It is represented by the number of cycles of the clock signal CLK. More specifically, the falling of the column address strobe signal CAS is
When detecting at the falling edge (at the falling edge) of LK, the read data DOUT <0> to the read data DOUT <0> to the falling edge of the clock signal CLK following the falling edge at which the falling edge of the column address strobe signal CAS is detected.
Clock signal C in a state where DOUT <3> is determined
Clock signal CLK up to the first fall edge of LK
Is the CAS latency. Data Read Operation from Memory Cell Array 10 and Main Amplifier 17
The operation of amplifying read data by R is uniquely determined by the circuit configuration, characteristics of circuit elements, and the like. Therefore, in order to output data to the outside at high speed, it is necessary to set a CAS latency having a delay time that is longer than or equal to the operation delay time and closest to the operation delay time. As described above, the CAS latency is equivalent to the number of cycles of the clock signal CLK.
The actual delay time due to the AS latency is the clock signal C
Even if the same delay time is set depending on the frequency of LK, if the frequency of the clock signal CLK is high, CA
The S latency is relatively large, and the CAS latency is relatively small if the frequency of the clock signal CLK is low. In the example of FIG. 1, the output control circuit 30 implements a CAS latency control circuit capable of variably controlling the CAS latency by inputting the latency setting data FRCD <1: 0>. The CAS latency is reflected in a latch timing according to the latch control signal PDOLTT.

The refresh control circuit (RCC) 40
A control circuit for periodically refreshing data of each memory cell in the memory cell array, and a plurality of internal control signals for an internal circuit of the memory block BNK0
Generate and supply ref. On the other hand, the refresh control circuit 40 outputs to the memory control circuit MCNT a refresh period notification signal MRef0 that activates the memory block BNK0 during the refresh period.

As apparent from the above description, the memory blocks BNK0 to BNK7 are connected to the clock signal CL.
The column address strobe signal CAS, which is changed in a cycle that is a multiple of the cycle of K, is input, and is read from the memory cell array 10 and synchronized with the cycle of the clock signal CLK in each cycle in which the column address signal CAS is changed. A plurality of parallel / serial converted serial data is output from the memory block, and the serial data is input to the memory block in synchronization with the cycle of the clock signal CLK, and the parallel / serial converted parallel data is written to the memory cell array 10. As described above, the memory operation can be speeded up by the access specification of changing the column address strobe signal CAS at a rate of once in a plurality of cycles of the clock signal CLK.

Although the invention made by the inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, the semiconductor integrated circuit of the present invention is not limited to a configuration having both upper and lower hierarchical interface blocks. For example, a configuration having a memory block and a read buffer as shown in FIG. 11, a configuration having a memory block and a write buffer as shown in FIG. 12, and a configuration having a memory block, a read buffer and a write buffer as shown in FIG. It is possible to separately grasp the present invention.

If there is room in the chip area, a read buffer or a write buffer may be provided for each memory block.

Further, the number of memory blocks, the number of parallel data input / output bits, the number of stages of read registers and write registers, and the like can be appropriately changed.

The memory block is not limited to a DRAM,
The read buffer and the write buffer are not limited to the SRAM, and may be memories of other storage formats. It is needless to say that the present invention can be widely applied to cache memories, main memories, and other logic-embedded semiconductor integrated circuits of various levels.

[0090]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the throughput of the read operation can be improved in a configuration employing a data buffer in order to avoid data competition due to the parallel operation of the memory blocks.

The throughput of the read operation can be improved so that the logic scale of the logic circuit does not increase unnecessarily.

It is possible to realize a semiconductor integrated circuit that can easily accept a write access request regardless of the internal memory operation state.

[Brief description of the drawings]

FIG. 1 is a block diagram generally showing an example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram illustrating details of an output path of the read data in the semiconductor integrated circuit of FIG. 1;

FIG. 3 is an explanatory diagram illustrating a control signal generated by a memory control circuit;

FIG. 4 is an explanatory diagram illustrating an information format of access control information.

FIG. 5 is a flowchart representatively showing a main control procedure of a memory control circuit in response to an external access request.

FIG. 6 is a timing chart showing an example of a write operation when a refresh operation is interposed in the middle of a write access;

FIG. 7 is a timing chart showing a write operation when a write buffer is not provided as a comparative example.

FIG. 8 is a timing chart showing an example of a read operation using a read buffer.

FIG. 9 is a timing chart illustrating a read operation when a read buffer is not provided as a comparative example.

FIG. 10 is a block diagram of a cache memory system using a semiconductor integrated circuit as an L3 cache memory.

11 is an explanatory diagram showing a data flow focusing on a read access operation of a processor in the cache memory system of FIG. 10;

FIG. 12 is an explanatory diagram showing a data flow focusing on an operation in a write access of a processor in the cache memory system of FIG. 10;

FIG. 13 is an explanatory diagram showing a data flow focusing on replacement of a cache line in the cache memory system of FIG. 10;

FIG. 14 is a block diagram of a memory system using a semiconductor integrated circuit as a main memory of a processor.

FIG. 15 is a block diagram showing an example in which a semiconductor integrated circuit is applied to a multiprocessor system as an L3 cache memory.

FIG. 16 is a layout diagram illustrating a chip layout of the semiconductor integrated circuit according to the present invention;

FIG. 17 is a block diagram showing a detailed example of a memory block.

[Explanation of symbols]

1 Semiconductor integrated circuit BNK0-BNK7 Memory block RB0-RB3 Read buffer WB0-WB3 Write buffer MCNT Memory control circuit I / F1 Upper layer interface block I / F2 Lower layer interface block 40 (40Aa, 40Ab, 40Ac, 40Ad) Selector 41 ( 41Aa, 41Ab, 41Ac, 41Ad, 41
B) Selector 42 Selector 8 DRAM core 22 Write register 26 Read register 50, 50-1, 50-2 Processor 50A CPU 50B L1 cache memory 50C L2 cache memory 50D Tag control logic 51 Main memory 52, 52-1, 52-2 Processor bus 53, 53-1, 53-2, 53-3 Memory bus 54 Memory buffer 55 Bus switch circuit CLK Clock signal BL Complementary bit line WL Word line RAS Row address strobe signal CAS Column address strobe signal

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Tohru Kobayashi 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Shuichi Miyaoka 6--16 Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center (72) Inventor Yuji Yokoyama 6-16, Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center (72) Inventor Hideo Sawamoto 1 Horiyamashita, Hadano City, Kanagawa Prefecture (72) Inventor Shoji Kume 1st Horiyamashita, Hadano-shi, Kanagawa F-term (reference) 5C005 JJ11 MM23 NN73 5B024 AA15 BA29 CA16

Claims (18)

[Claims] A plurality of memory blocks capable of operating in parallel; external interface means capable of inputting write data from outside and outputting read data to the outside; and reading read data read from the memory blocks. A read buffer that can be held in response to a state that cannot be output to the outside from the external interface means, and read data that is read from the memory block when the state that cannot be output has been resolved or Selecting means for selecting read data read from the read buffer and providing the selected data to the external interface means. 2. A plurality of memory blocks capable of operating in parallel, a read buffer capable of holding read data read from the memory block, read data output from the read buffer, and the memory block External interface means capable of outputting read data output from the memory block to the outside; and reading the read data read from the memory block in response to a state in which the read data cannot be output externally from the external interface means. Control means for holding in a buffer, and outputting read data read from the memory block or read data read from the read buffer from the external interface means when the output impossible state is resolved, Semiconductor characterized by having: Integrated circuit. 3. A plurality of memory blocks operable in parallel, external interface means capable of externally inputting write data, and input data held by the external interface means being held, and the memory block is configured to perform a write operation. And a write buffer for supplying write data to the memory block after being made operable. 4. An external interface capable of externally inputting write data, a write buffer for inputting write data input to the external interface, and a plurality of memory blocks to which write data is supplied from the write buffer. Write data supplied to the external interface means in response to an external access request is stored in the write buffer, and the write data is transferred from the write buffer to the memory after the memory block to be accessed is enabled for write operation. And a control unit for supplying the block to the semiconductor integrated circuit. 5. A plurality of memory blocks operable in parallel, external interface means capable of inputting write data from the outside and outputting read data to the outside, and write data input to the external interface means. A write buffer for inputting and holding, and supplying write data to the memory block after the memory block is enabled for write operation; and a read buffer read from the memory block cannot be externally output from the external interface means. Select a read buffer that can be held in response to the state, and read data read from the memory block or read data read from the read buffer when the output disabled state is resolved And selecting means for giving to the external interface means The semiconductor integrated circuit, characterized in that the at it. 6. A plurality of memory blocks operable in parallel, first external interface means capable of externally inputting write data and outputting read data to the outside, and externally inputting write data. A second external interface means capable of outputting read data to the outside, and write data input to the first or second external interface means being input and held, and the memory block is enabled to perform a write operation. A write buffer for supplying write data to a memory block later, holding of read data to be output from the second external interface means, and read data to be output from the first external interface means; It is possible to hold read data that cannot be output to the outside from the external interface means. A read buffer read from the memory block or a read data read from the read buffer when the output disabled state is resolved, and the first external interface means A semiconductor integrated circuit comprising: 7. The semiconductor integrated circuit according to claim 6, wherein said first and second external interface means can individually input an access request and an access address to a memory block from outside. 8. A system comprising a memory buffer capable of inputting and holding data from the second external interface means and outputting the held data to the outside from the second external interface means. 8. The semiconductor integrated circuit according to claim 6, wherein: 9. The memory block is a DRAM,
9. The semiconductor integrated circuit according to claim 5, wherein the read buffer and the write buffer are SRAMs. 10. The memory block includes a memory cell array having a plurality of memory cells each having a selection terminal connected to a word line and a data input / output terminal connected to a bit line, and a word line designated by a row address signal. A row selection circuit to select, a column selection circuit to select a plurality of bit lines specified by a column address signal in parallel, and write data serially input from the write buffer into parallel data in synchronization with a clock signal. A serial / parallel conversion circuit for conversion; a write amplifier for outputting the parallel data of the serial / parallel conversion circuit to a plurality of bit lines selected by the column selection circuit; A main amplifier for amplifying the parallel data output from the bit line, and a clock for the parallel data output from the main amplifier. A parallel-to-serial conversion circuit that converts the data into serial data in synchronization with a read signal and outputs the data to the read buffer and the selection unit
7. The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit comprises: 11. The multi-port memory, wherein the memory block is a multi-port memory having a serial data input path of a serial / parallel conversion circuit and a serial data output path of the parallel / serial conversion circuit independently. Item 11. A semiconductor integrated circuit according to item 10. 12. A memory block opposingly arranged on a semiconductor chip, and a read buffer and a memory block interposed between the opposing memory blocks and capable of holding read data read from the memory block. A write buffer capable of holding write data to be given, external interface means arranged near the read buffer and the write buffer, and an external connection electrode located near the external interface means, The write buffer inputs and holds the write data input to the external interface unit, and supplies the write data to the memory block after the memory block is enabled to perform a write operation. The read data read is transferred to the external interface. It is possible to hold in response from the scan means impossible state output to the outside, the semiconductor integrated circuit, characterized in that. 13. A first dynamic type having a semiconductor chip and a data output unit formed on the semiconductor chip, storing a plurality of data and outputting corresponding data in response to supply of a predetermined address signal. A second dynamic memory formed on the semiconductor chip, having a data output unit for storing a plurality of data and outputting corresponding data in response to supply of a predetermined address signal; An external output circuit formed on the semiconductor chip; a first buffer circuit formed on the semiconductor chip and coupled to the output section of the first dynamic memory; and a first dynamic circuit formed on the semiconductor chip. A first input coupled to the data output of the memory;
A first selection circuit having a second input coupled to an output of the buffer circuit and an output coupled to the external output circuit; and an output section of the second dynamic memory formed on the semiconductor chip. A second buffer circuit formed on the semiconductor chip and coupled to the data output section of the second dynamic memory;
A second selection circuit having a second input coupled to the output of the buffer circuit and an output coupled to the external output circuit; controlling a selection operation of the first and second selection circuits; A control circuit for controlling a write operation of the second buffer circuit. 14. The semiconductor integrated circuit according to claim 13, wherein each of said first and second buffer circuits includes a plurality of static memory cells. 15. A semiconductor chip, comprising: a semiconductor chip; a data input unit formed on the semiconductor chip;
A memory in which a refresh operation of stored data is periodically required; a buffer circuit formed on the semiconductor chip and coupled to the data input unit of the memory; and a buffer circuit formed on the semiconductor chip, An external input circuit coupled to a buffer circuit and supplied with data to be written to the memory; and an external input circuit formed on the semiconductor chip and supplied to the external input circuit during a refresh operation of the memory. A semiconductor integrated circuit comprising: a control circuit for controlling the buffer circuit so as to be selectively held by the buffer circuit. 16. The memory according to claim 1, wherein the plurality of word lines, the plurality of data lines, and the plurality of word lines and the plurality of data lines are coupled such that one memory cell is coupled to one word line and one data line. A plurality of memory cells coupled to the data line, each of the plurality of memory cells includes a capacitive element and a selection transistor, wherein the selection transistor has a selection terminal coupled to a corresponding word line; 16. The semiconductor integrated circuit according to claim 15, further comprising a data input / output terminal coupled to a corresponding data line. 17. A buffer circuit comprising: a memory array including a plurality of static memory cells, a plurality of word lines, and a plurality of complementary data line pairs; and an address decoder for selecting a predetermined word line in response to an address signal. 17. The semiconductor integrated circuit according to claim 16, comprising: a sense amplifier for amplifying data of a plurality of selected memory cells; and a data output circuit for outputting the amplified data. 18. The buffer circuit includes a plurality of static memory cells, and each of the plurality of static memory cells includes a pair of inverters whose input / output terminals are cross-coupled. Claim 1
8. The semiconductor integrated circuit according to 7.