JP2001217726A - Encoding/decoding device and bit error rate detecting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce circuit scale without performing any re-encoding after decoding when detecting the bit error rate of a communication path by a decoder on the side of a receiver in the radio communication by using a systematic code. SOLUTION: In the encoding/decoding device and the bit error rate detecting method, the bit error rate is detected only by using a systematic bit and a partial redundant bit in the systematic code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code decoding apparatus and a bit error rate detecting method for detecting a bit error rate via decoding means on a receiving side in a radio communication system using a systematic code.

[0002]

2. Description of the Related Art It has been widely practiced to measure a bit error rate on a receiver side in a wireless communication system using an organization code in order to know an error caused by noise in a communication path.

Generally, when P messages are transmitted from an information source to a communication channel, if P is P = 2 ^k , the message is k
It is given by a code word of bits (a ₁ , a ₂ ‥‥ a _i ‥‥ _ak ), and further added by m bits (c ₁ , c ₂ ‥‥ c _j }
When an (n, k) code word having a bit length of n (= k + m) is created by adding a redundant bit code of {c _m ), the redundant bit is represented by the following equation (1).
Is selected to satisfy.

[0004]

(Equation 1) Here, a _i and c _j are either 0 or 1. p _{j is} also 0
Or a fixed value that is not a variable.

(N, satisfies the above equation (1))
k) Code words are generally defined as systematic codes. In the present invention, a code in which message data input from an information source appears as it is is defined as a systematic code, and a wireless communication system using a conventional parallel turbo code which is a type of a systematic code will be described with reference to FIGS.

FIG. 3 shows a system diagram of a wireless communication system using a turbo code. On the transmitting side, an information bit composed of a code word having an n-bit length (hereinafter, referred to as a systematic code) is input to the turbo encoder 101 as an input signal x, and at least a systematic bit (message bit) x of the systematic code is output as it is. an encoder 101, (hereinafter referred to as parity bits) redundant bits output from the recursive systematic convolutional encoder 102 provided on the systematic bits x and the turbo encoder 101 of the turbo encoder 101 y ₁ and The modulator 105 receives y ₂ and performs modulation.

[0007] In the turbo encoder 101, an interleaver 1 is provided.
03. Such a turbo encoder 101 incorporates an interleaver into the encoding and uses recursive systematic convolutional encoders 102 and 104 in parallel to produce a parallel concatenated convolutional code. 1 of the specific configuration of the servo encoder 101
An example is shown in FIG.

In FIG. 4, the systematic bit x of the input signal is output to the output side of the turbo encoder 101 as it is. Recursive systematic convolutional encoder (hereinafter referred to as encoder) 102 and 1
04 is a plurality of delay elements 111A, 112A, 113A, cascade-connected to the first adders 110A and 110B, respectively.
114A and 111B, 112B, 113B, 114B
And these delay elements 111A, 112A, 113A, 11
The delay outputs of 4A and 111B, 112B, 113B and 114B are fed back to the first adders 110A and 110B, and the outputs of the first adders 110A and 110B and the outputs of the delay units 114A and 114B at the final stage are supplied. The parity bits y ₁ and y ₂ are output from the second adders 115A and 115B.

[0009] The input information x, which is a systematic code, is input to an encoder 10.
2 is supplied to the first adder 110A and the delay circuit 116. The output of the delay circuit 116 is supplied to the interleaver 103, and the output of the interleaver 103 is supplied to the first
Of the encoders 102 and 10
4 are independent encoded sequences.

Returning to the system diagram of the wireless communication system shown in FIG.
As the description proceeds, the modulation output signal from the modulator 105 on the transmission side is obtained.
The signal is generally transmitted to the receiving side via a communication path 106 such as in the air.
Transmitted. In this communication path 106, avoid mixing of noise.
I can't. On the receiving side, demodulation of operation reverse to that of modulator 105
Is performed by the demodulator 107. Here, after demodulation by demodulator 107
Systematic bit x and parity bit y of₁And y_TwoDemodulation
X 'and y ₁', Y_Two′, These are
Decoded by the turbo decoder 108, the turbo decoder 10
8 outputs the decoding result.

The above turbo code turbo decoder 108
(108A, 108B) improves the decoding performance by repeatedly decoding using, for example, a soft decision output of the decoding result.

FIG. 5 shows an example of a specific configuration of such a turbo decoder 108. K-th systematic bit x in the demodulated data output from the demodulator 107 '(hereinafter x _k' hereinafter) is supplied to the first decoder 117A, the k-th parity bits y ₁ 'and y _2' ( Hereinafter, referred to as y _1k ′ and y _2k ′) are transmitted through the switching means 118A.
Are supplied to the demodulators 117A and 119A. Soft decision outputs are obtained from the first demodulator 117A and the second demodulator 119A, respectively.

The soft-decision output of the first decoder 117A is interleaved by an interleaver that rearranges and disperses the code sequence in an interleaver 120A, and then supplies it to a second decoder 119A for repeated decoding.

The second decoder 119A has an interleaver 1
20A and the parity bit y _2k ′ are input, and the second
Of the decoder 119A is supplied to first and second deinterleavers 121A and 122A, and after deinterleaving, the output of the first deinterleaver 121A is the same as that described above for performing the second turbo decoding. Z ₁ and _kD are output to the _first decoder 117B of the second turbo decoder 118B (the same parts are denoted by the same reference numerals with the letter B).

The output of the second de-interleaver 122A outputs a first decoded output via a frequency discriminator 123A. The delay unit 124A is provided for time adjustment of the systematic codes x _k ′, y _1k ′, and y _2k ′ of the received input in the next decoding with the decoding decision output delayed by D bits. , The second decoded output is obtained and the third
Is repeated a plurality of times. In this case, the MAP (Maximum A-Posterori) algorithm is actually used.

The above-described demodulator 107 and turbo decoder 10
FIG. 6 shows a system diagram of a conventional bit error rate measuring device in the case of measuring the bit error rate before decoding in order to estimate the state of the communication path 106 on the receiver side using FIG.

Referring to FIG. 6, turbo decoder 108 (10
8A, 108B}) have the same configuration as that described with reference to FIG.
The systematic bit x 'and parity bit from the modulator 107
y₁', Y _Two'To the turbo decoder 108.

The decoding result output from the turbo decoder 108 is supplied to the turbo encoder 101 similar to that described with reference to FIG. 4, and the systematic bits x ″ and the parity bits y ₁ ″ and y ₂ ″ are output.
Is output. Demodulator 1 supplied to turbo decoder 108
A systematic bit x from 07 'and the parity bits y _1' y ₂ 'are to each first third register 125,
127 is temporarily stored. First
The registered outputs of the third through third registers 125, 126, 127 are output from the first through third comparators 128, 129, 1
30 x supplied _{as', y 1 ', y 2} '.

In the first comparator 128, the turbo encoder 10
The systematic bit x ″ from 1 is compared with the systematic bit x ′ output from the first register 125 and output to the first counter 131.

In the second comparator 129, the turbo encoder 10
The parity bit y ₁ ″ from ₁ and the second register 126
Parity bits y ₁ 'output is compared from the compared output is output to the second counter 132.

In the third comparator 130, the turbo encoder 10
The parity bit y ₂ ″ from 1 and the third register 127
Parity bits y ₂ 'output is compared from the comparison output is outputted to the third counter 133.

The first to third counters 131, 132,
133 is a first to third comparators 128, 129, 130
When the respective comparison values are different, the counting is performed, and these count values are added by the adder 134,
The bit error rate is output from the adder 134.

[0023]

As described with reference to the prior art configuration of FIG. 5, a systematic code sequence is generated by adding a parity bit to a systematic bit at the time of error correction coding to improve the error rate characteristics. When measuring the bit error rate before decoding, the receiver side inputs the data decoded by the turbo decoder 108 to the turbo decoder 101 and performs encoding again. At this time, assuming that the entire codeword is to be measured for the bit error rate, the receiver must have exactly the same turbo encoder 101 as the transmitter.

This leads to an increase in the circuit size of the receiver.
In the turbo encoder 101 using the above systematic code, two recursive systematic convolutional encoders 102 and 1 are used for re-encoding.
In addition to the necessity of an interleaver 04, an interleaver 103 and a delay unit 116 are required. In particular, the interleaver 103 requires storage units for the number of input data, and has a large effect on the circuit scale.

Further, as is apparent from FIG. 6, three registers 125 to 127, comparators 128 to 130, and counters 131 to 133 are required respectively, and this part also causes an increase in the circuit scale.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides a code decoding apparatus and a bit error rate detection method capable of omitting or simplifying an encoder for re-encoding on a receiver side. What you want to do.

[0027]

A first code decoding apparatus of the present invention transmits a systematic code to a communication path 106 via a coding means 101 from which a systematic code is output as it is on a transmitting side, and a decoding means 108 on a receiving side. A code decoding apparatus for obtaining a decoded output, wherein a bit error rate is detected using at least a systematic bit of a systematic code input to a decoding unit.

According to a second code decoding apparatus of the present invention, in the first invention, a bit error rate is detected by using a part of the redundant bits and the systematic bits of the systematic code.

In a third aspect of the present invention, in the second aspect, the decoding means is a servo decoding means 108,
A storage unit 125 for storing a systematic bit of a systematic code input to the servo decoding unit 108;
A comparing means 128 for comparing the decoded output of the data 08 with the systematic bit stored in the storage means 125, a counting means 131 for counting different values of the comparing means 125, and an arithmetic means 135 for dividing the output of the counting means by the number of systematic bits. Is provided.

The fourth code decoding means of the present invention is the servo decoding means in the second invention, wherein the decoding means is a servo decoding means, and the first storage for storing the systematic bits of the systematic code inputted to the servo decoding means. Means 125, a second storage means 126 for storing one of the redundant bits of the systematic code inputted to the servo decoding means 108, and a turbo decoding means 108
, A first comparison means 128 for comparing the decoded output of the first decoding means with the systematic bits stored in the first storage means 125, a recursive systematic convolutional coding means 102 for coding the decoded output of the turbo decoding means 108, and a second Comparing means 136 with the encoded output of the recursive systematic convolutional encoding means 102, and first and second comparing means 128 and 13
First and second counting means 131 for counting six different values
And 132, and first and second counting means 131 and 13
It has an adding means 134 for adding the count output of 2 and an arithmetic means 137 for dividing the output of the adding means 134 by the number of the sum of the systematic bit and one redundant bit.

The bit error rate detecting method of the present invention transmits information data to a communication channel using a systematic code, and detects the bit error rate of the communication channel when decoding and obtaining a decoded output on the receiving side. In this detection method, a bit error rate is detected using at least systematic bits in a systematic code input at the time of decoding on a receiving side.

According to the code decoding apparatus and the bit error rate detection method of the present invention, it is possible to omit or simplify the encoder for performing re-encoding at the time of decoding on the receiver side, and to reduce the circuit scale on the receiver side. It is possible to prevent an increase.

[0033]

FIG. 1 is a block diagram showing a code decoding apparatus using a systematic code and a bit error rate detection method according to the present invention.
This will be described in detail with reference to FIG. Note that the same reference numerals are given to the corresponding parts described with reference to FIGS.

FIG. 1 shows a communication path 106 on the receiver side of the present invention.
FIG. 6 is a system diagram of a bit error rate measuring device for performing a bit error rate measurement (detection) in a medium, and corresponds to FIG.

The servo decoder 108 has the same configuration as that described in detail with reference to FIG. 5, and the information bits x 'and the parity bits y ₁ ', y ₂ 'from the demodulator 107 in FIG. , And the servo decoder 108 outputs a decoding result. This decoding result output is output to the first comparator 1
28.

The hard decision value of the organization bit x 'is temporarily the first
, And absorbs the time lag due to the decoding process of the decoder 108 to obtain the first systematic bit x ″.
, And is compared with the decoding result output of the turbo decoder.

When the comparison output is different in the first comparator 128, the internal count value in the counter 131 is increased by one.

Since the count value after all such data processing is the number of errors with respect to the organization bit x, when the arithmetic unit 135 divides the count value by the number N of x, a bit error with respect to the organization bit x results.

In the present invention, since the bit error is detected by effectively using the organization bit x in the organization code as described above, the turbo encoder 101 for re-encoding can be omitted on the receiver side. And the second and third two registers 12
6, 127, comparators 129, 130, counter 132,
133 is also unnecessary.

FIG. 2 is a system diagram showing another embodiment of the bit error rate measuring (detecting) apparatus according to the present invention, and the same reference numerals are assigned to parts corresponding to those in FIG.

The servo decoder 108 has the same configuration as that described in detail with reference to FIG. 5, and the information bits x 'and the parity bits y ₁ ', y ₂ 'from the demodulator 107 in FIG. , And the servo decoder 108 outputs a decoding result. This decoding result output is output to the first comparator 1
The parity bit y ₁ ″ is supplied to a second comparator 136 via one recursive systematic convolutional encoder 102, which is supplied to the turbo encoder 101 and similar to that described in detail for the turbo encoder 101 of FIG.

On the other hand, the decoding supplied to the turbo decoder 108 is
Parity bit y from modulator 107 ₁'Is the second Regis
Temporarily stored in the decoder 126 and decoded by the turbo decoder 108.
The processing time and the timing are matched to the second comparator 136.
Organization bit y₁'And input the organization bit y₁Compared to ″
And output to the second counter 132.

The first register 125 stores the hard decision value of the systematic bit x 'in the same manner as in FIG.
08 and the comparison output is the first
Is output to the counter 131.

When the comparison outputs from the first and second comparators 128 and 136 are different, the internal count value in the first and second counters 131 and 132 is increased by one.

In this manner, the adder 134 adds the count value after processing the data of the number of errors for the organization bit x and the number of errors for the parity bit y ₁ , and adds the result to the sum of the organization bit x and the parity bit y ₁ . bit error rate for the systematic bits x and parity bits y ₁ is divided by the number 2 · N by computing means 137 is obtained.

The recursive systematic convolutional encoders in the case of using the parity bits of the systematic bits x and y ₁ as in this example 10
2, the second register 126, the second comparator 136, the second
The counter 132 increases, and the circuit scale increases as compared with the case where only the systematic bits in FIG. 1 are used. However, since the turbo encoder 101 is not provided and the interleaver 103 is not particularly required, the parity bit of y ₂ is targeted. Compared with FIG. 6 and the like, the degree of increase in the circuit scale is far less, and the accuracy of the measurement or detection of the parity bit is increased as compared with FIG. Incidentally, it is clear that may have been described the manner used parity bits y ₂ a case where a parity bit y ₁ is described.

[0047]

Effects of the Invention In code decoding apparatus and the bit error rate of the detection (measurement) receiver using a systematic code according to the method of the present invention, the systematic bits systematic bits or parity bits y ₁ or y ₂ By using, an encoder such as a turbo encoder can be omitted or simplified.

[Brief description of the drawings]

FIG. 1 is a system diagram showing one embodiment of a bit error rate measuring (detecting) device of the present invention.

FIG. 2 is a system diagram showing another embodiment of the bit error rate measuring (detecting) device of the present invention.

FIG. 3 is a system diagram of a wireless communication path using a general turbo code.

FIG. 4 is an example of an encoding circuit of a conventional turbo code.

FIG. 5 is an example of a conventional turbo code decoding circuit.

FIG. 6 is a system diagram showing an example of a conventional bit error rate measuring (detecting) device.

[Explanation of symbols]

101 ‥‥ turbo encoder, 108 ‥‥ turbo decoder, 1
25, 126, 127 {first to third registers, 12
8, 129, 130 {first to third comparators, 131,
132, 133 {first to third counters, 134}
Adder, 135, 137 operation unit

Continued on front page F term (reference) 5B001 AA01 AA10 AB05 AC01 AC04 AC05 AD06 5J065 AC02 AD02 AD10 AE01 AF03 AG06 AH02 AH03 AH06 AH07 AH15 AH22 5K014 AA01 BA02 BA10 EA01 EA04 FA16 GA02

Claims (5)

[Claims] 1. An encoding / decoding device which transmits a systematic code to a communication channel via an encoding unit which outputs a systematic code as it is on a transmission side, and obtains a decoded output by a decoding unit on a receiving side. A code error detecting unit that detects a bit error rate using at least a systematic bit of the systematic code. 2. The code decoding apparatus according to claim 1, wherein said bit error rate is detected by using a part of redundant bits and systematic bits of said systematic code. 3. The decoding means is a turbo decoding means,
A storage unit for storing a systematic bit of the systematic code input to the turbo decoding unit; a comparing unit for comparing a decoded output of the turbo decoding unit with the systematic bit stored in the storage unit; 3. The code decoding apparatus according to claim 2, further comprising: counting means for counting a value; and calculating means for dividing the output of the counting means by the number of the systematic bits. 4. The decoding means is a turbo decoding means,
First storage means for storing the systematic bits of the systematic code input to the turbo decoding means, and second storage means for storing one of the redundant bits of the systematic code input to the turbo decoding means. First comparing means for comparing the decoded output of the turbo decoding means with the systematic bits stored in the first storage means; and recursive systematic convolutional coding means for coding the decoded output of the turbo decoding means. A second comparing means for comparing the second storage means with the coded output of the recursive tissue convolutional coding means, and a first comparing means for counting different values of the first and second comparing means.
And second counting means, adding means for adding the count outputs of the first and second counting means, and calculating means for dividing the output of the adding means by the number of sums of the systematic bits and one redundant bit. 3. The code decoding apparatus according to claim 2, comprising: 5. A bit error rate detection method for transmitting information data to a communication path using a systematic code, decoding the data on a receiving side, and detecting a bit error rate of the communication path when obtaining a decoded output. A bit error rate detection method comprising: detecting a bit error rate using at least systematic bits in the systematic code input at the time of decoding on the receiving side.