JP2001217280A - Semiconductor mounting structure - Google Patents
Semiconductor mounting structureInfo
- Publication number
- JP2001217280A JP2001217280A JP2000028471A JP2000028471A JP2001217280A JP 2001217280 A JP2001217280 A JP 2001217280A JP 2000028471 A JP2000028471 A JP 2000028471A JP 2000028471 A JP2000028471 A JP 2000028471A JP 2001217280 A JP2001217280 A JP 2001217280A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- mounting
- semiconductor
- substrate
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体実装構造に
関する。[0001] The present invention relates to a semiconductor mounting structure.
【０００２】[0002]
【従来の技術】従来の半導体実装構造として、特開昭６
３−２７５１２７号公報に記載されたフリップチップ実
装構造がある。図７(a)(b)に示すように、フリップチッ
プは半導体チップ２１の入出力電極上に電気的接続接点
となるスタッドバンプ２２を備えたものであり、スタッ
ドバンプ２２を介して回路基板２３の導体端子部に接合
され、封止材１４で封止される。2. Description of the Related Art A conventional semiconductor mounting structure is disclosed in
There is a flip chip mounting structure described in Japanese Patent Application Laid-Open No. 3-275127. As shown in FIGS. 7A and 7B, the flip chip is provided with stud bumps 22 serving as electrical connection contacts on input / output electrodes of a semiconductor chip 21, and a circuit board 23 is provided via the stud bumps 22. And is sealed with a sealing material 14.
【０００３】このようなフリップチップ実装は、ボンデ
ィングワイヤやリードを必要とするパッケージＩＣに比
べて、ＩＣを小型化できる利点だけでなく、接合部を大
幅に小さくできるため電気的な特性（特に高周波特性）
が良いという利点を持っている。[0003] Such flip-chip mounting not only has the advantage of downsizing the IC as compared with a packaged IC that requires bonding wires and leads, but also has the advantage that electrical characteristics (particularly high frequency Characteristic)
Has the advantage of being good.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら従来のフ
リップチップ実装では、上記したように半導体チップを
直接実装しているため、ＩＣの信頼性を保つのが容易で
ない。たとえば、パッケージＩＣと比較すると、チップ
ＩＣの方が、出荷時に行われる長時間通電試験がプロー
ビングの点で難しく、また高周波特性の測定がプロービ
ングの点で難しい。また、実装後に不良が判明し不良原
因を探るために半導体チップを取り外す際にＩＣの破壊
を来たすことがある、などの問題もある。However, in the conventional flip chip mounting, since the semiconductor chip is directly mounted as described above, it is not easy to maintain the reliability of the IC. For example, as compared with a package IC, a chip IC is more difficult to probe for a long-term energization test performed at the time of shipment, and it is more difficult to measure high-frequency characteristics in terms of probing. In addition, there is another problem that the IC may be destroyed when the semiconductor chip is removed to find out the cause of the defect and to find the cause of the defect after mounting.
【０００５】本発明は上記問題を解決するもので、高周
波特性が良く、かつ信頼性が高い、半導体実装構造を提
供することを目的とするものである。An object of the present invention is to solve the above problems and to provide a semiconductor mounting structure having good high frequency characteristics and high reliability.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に本発明は、半導体チップを個々にあるいは少数個、た
とえば２〜３個ずつ小さな基板上に実装し、その基板を
半導体チップに対向するより大きな基板上に実装するこ
とで、小さな基板単位での半導体チップの取り扱いを可
能にし、信頼性を向上させるものである。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention comprises mounting semiconductor chips individually or in small numbers, for example, two or three, on a small substrate, and facing the semiconductor chip to the semiconductor chip. By mounting the semiconductor chip on a larger substrate, it is possible to handle a semiconductor chip in a unit of a small substrate, thereby improving reliability.
【０００７】[0007]
【発明の実施の形態】請求項１記載の発明は、電気的接
続接点となる突起を備えた半導体チップをキャリヤ基板
に実装し、前記キャリヤ基板を半導体チップ側のキャリ
ヤ基板表面に対向する実装基板に実装したことを特徴と
する半導体実装構造であり、これにより、半導体チップ
がキャリヤ基板単位で取り扱い可能となるため、長時間
通電試験、高周波特性の測定を容易に行えるとともに、
不良原因を探る際もＩＣ破壊を防止することができ、信
頼性を向上できる。半導体チップは突起において接合さ
れるフリップチップ方式なので、フリップチップ実装特
有の利点、良好な電気的な特性（特に高周波特性）は保
持される。According to a first aspect of the present invention, there is provided a mounting substrate in which a semiconductor chip having a projection serving as an electrical connection contact is mounted on a carrier substrate, and the carrier substrate is opposed to the surface of the carrier substrate on the semiconductor chip side. This is a semiconductor mounting structure characterized by being mounted on a substrate, which enables semiconductor chips to be handled on a carrier substrate basis, making it possible to easily conduct long-term current tests and measure high-frequency characteristics.
Even when the cause of the defect is searched for, IC destruction can be prevented, and reliability can be improved. Since the semiconductor chip is flip-chip bonded at the protrusions, advantages unique to flip-chip mounting and good electrical characteristics (particularly high-frequency characteristics) are maintained.
【０００８】請求項２記載の本発明は、請求項１記載の
構成において、半導体チップを１個ずつキャリヤ基板に
実装したことを特徴とする半導体実装構造であり、上記
した利点がより大きくなる。According to a second aspect of the present invention, there is provided a semiconductor mounting structure according to the first aspect, wherein the semiconductor chips are mounted one by one on a carrier substrate, and the above advantages are further enhanced.
【０００９】請求項３記載の本発明は、請求項１記載の
構成において、実装基板が半導体チップを収容する貫通
穴を有したことを特徴とする半導体実装構造であり、こ
れにより、小型化が可能になる。According to a third aspect of the present invention, there is provided a semiconductor mounting structure according to the first aspect, wherein the mounting substrate has a through hole for accommodating a semiconductor chip. Will be possible.
【００１０】請求項４記載の本発明は、請求項１記載の
構成において、実装基板が半導体チップを収容する凹部
を有したことを特徴とする半導体実装構造であり、これ
により、小型化が可能になる。According to a fourth aspect of the present invention, there is provided a semiconductor mounting structure according to the first aspect, wherein the mounting substrate has a concave portion for accommodating a semiconductor chip. become.
【００１１】以下、本発明の実施の形態を図面を参照し
ながら具体的に説明する。図１(a)は本発明の第１の実
施の形態における半導体実装構造を持った集積回路の断
面図、図１(b) は同集積回路の一部平面図である。An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1A is a sectional view of an integrated circuit having a semiconductor mounting structure according to a first embodiment of the present invention, and FIG. 1B is a partial plan view of the integrated circuit.
【００１２】図１(a)(b)において、１はセラミックなど
からなるキャリヤ基板である。２はキャリヤ基板１の一
側面（以下、下面という）に形成された導体パターンで
あり、場合によって５０Ω線路とされる。３は各キャリ
ヤ基板１の下面に１個ずつ実装された半導体チップ（フ
リップチップ）であり、導体パターン２との間を電気的
に接続するハンダなどの接合用バンプ４を持っている。In FIGS. 1A and 1B, reference numeral 1 denotes a carrier substrate made of ceramic or the like. Reference numeral 2 denotes a conductor pattern formed on one side surface (hereinafter, referred to as a lower surface) of the carrier substrate 1, which may be a 50Ω line in some cases. Reference numeral 3 denotes a semiconductor chip (flip chip) mounted on the lower surface of each carrier substrate 1 one by one, and has a bonding bump 4 such as solder for electrically connecting the semiconductor chip to the conductor pattern 2.
【００１３】５はキャリヤ基板１より大きく形成された
実装基板であり、キャリヤ基板１の下面に対向して配置
されている。６はキャリヤ基板１に対向する実装基板５
の一側面に形成された導体パターンであり、７は半導体
チップ２を実装すべき実装基板５の所定位置に形成され
半導体チップ２を収容する貫通穴である。８はキャリヤ
基板１の導体パターン２と実装基板５の導体パターン６
との間を電気的に接続するハンダなどの接合バンプであ
る。Reference numeral 5 denotes a mounting substrate formed to be larger than the carrier substrate 1, and is arranged to face the lower surface of the carrier substrate 1. 6 is a mounting substrate 5 facing the carrier substrate 1
Is a through hole formed at a predetermined position on the mounting board 5 on which the semiconductor chip 2 is to be mounted, and for accommodating the semiconductor chip 2. Reference numeral 8 denotes the conductor pattern 2 of the carrier substrate 1 and the conductor pattern 6 of the mounting substrate 5.
And a bonding bump such as solder for electrically connecting between them.
【００１４】図示を省略するが、実装基板２には、半導
体チップ２と外部回路との入出力整合を行う整合回路お
よび半導体チップ２に合った電源を供給する電源回路が
形成されている。Although not shown, on the mounting board 2, a matching circuit for performing input / output matching between the semiconductor chip 2 and an external circuit and a power supply circuit for supplying power suitable for the semiconductor chip 2 are formed.
【００１５】上記集積回路を製造する際には、予め各キ
ャリヤ基板１，実装基板５に導体パターン２，６を形成
しておく。そして、各キャリヤ基板１に対して、導体パ
ターン２に適合する所定位置に半導体チップ３を位置決
めし、接合用バンプ４を介して実装する。この時の実装
工程は従来と同様に行う。When the integrated circuit is manufactured, conductor patterns 2 and 6 are formed on each carrier substrate 1 and mounting substrate 5 in advance. Then, the semiconductor chip 3 is positioned at a predetermined position corresponding to the conductor pattern 2 with respect to each carrier substrate 1 and mounted via the bonding bumps 4. The mounting process at this time is performed in the same manner as in the related art.
【００１６】この状態で、各半導体チップ２（チップＩ
Ｃ）に対して、長時間通電試験、高周波特性の測定など
の試験を実施する。不良が検出されなかったら、実装基
板５の貫通穴７に半導体チップ３が収容され、かつ導体
パターン２と導体パターン６とが対向するように各キャ
リヤ基板１を位置合わせし、接合バンプ８を介して実装
基板５に実装する。また、実装基板５上に整合回路や電
源回路など、他の部品を実装する。In this state, each semiconductor chip 2 (chip I
For C), tests such as a long-time conduction test and measurement of high-frequency characteristics are performed. If no defect is detected, each carrier substrate 1 is positioned so that the semiconductor chip 3 is accommodated in the through hole 7 of the mounting substrate 5 and the conductor pattern 2 and the conductor pattern 6 are opposed to each other. And mounted on the mounting board 5. Further, other components such as a matching circuit and a power supply circuit are mounted on the mounting board 5.
【００１７】このような実装構造によれば、半導体チッ
プ３がキャリヤ基板１単位で取り扱い可能となるので、
長時間通電試験、高周波特性の測定を容易に行えるとと
もに、不良原因を探る際も半導体チップ３の破壊が発生
せず、信頼性を向上できる。キャリヤ基板１に対する半
導体チップ３の接合は小さな接合用バンプ４によるの
で、フリップチップ実装特有の良好な電気特性（特に高
周波特性）を保持できる。また半導体チップ３は貫通穴
７に収容しているので小型化を実現できる。According to such a mounting structure, the semiconductor chip 3 can be handled by one carrier substrate.
A long-time current test and measurement of high-frequency characteristics can be easily performed, and the reliability of the semiconductor chip 3 can be improved without destruction of the semiconductor chip 3 even when searching for a cause of a defect. Since the bonding of the semiconductor chip 3 to the carrier substrate 1 is performed by the small bonding bumps 4, good electrical characteristics (particularly, high-frequency characteristics) unique to flip chip mounting can be maintained. Further, since the semiconductor chip 3 is housed in the through hole 7, downsizing can be realized.
【００１８】以下、本発明の半導体実装構造における電
気特性を従来の半導体実装構造と比較して説明する。図
２(a)は上記実施の形態と同様に、半導体チップ３を個
々にキャリヤ基板１に実装し、各キャリヤ基板１を半導
体チップ３側の基板１表面に対向する実装基板５に実装
した構造を示す。この実装構造によれば、基板上の導体
パターンを、インピーダンス整合された構造（例えばマ
イクロストリップライン構造やコプレナー構造など）に
することによって、インピーダンス整合されない非整合
部分Ｐ（０．２ｍｍ程度）を、ＩＣ１個当たり接合バン
プ２個分にすることができ、図２(b)にした周波数と反
射との関係においてピークが１００ＧＨｚ程度となる、
良好な周波数特性を実現できる。Hereinafter, the electrical characteristics of the semiconductor mounting structure of the present invention will be described in comparison with a conventional semiconductor mounting structure. FIG. 2A shows a structure in which semiconductor chips 3 are individually mounted on a carrier substrate 1 and each carrier substrate 1 is mounted on a mounting substrate 5 facing the surface of the substrate 1 on the semiconductor chip 3 side, as in the above embodiment. Is shown. According to this mounting structure, a non-matching portion P (about 0.2 mm) that is not impedance-matched can be formed by making the conductor pattern on the substrate an impedance-matched structure (for example, a microstrip line structure or a coplanar structure). One IC can be equivalent to two bonding bumps, and the peak is about 100 GHz in the relationship between the frequency and the reflection shown in FIG.
Good frequency characteristics can be realized.
【００１９】図３(a)は、半導体チップ３を個々にキャ
リヤ基板１に実装し、各キャリヤ基板１を半導体チップ
３に背反する基板１表面に対向する実装基板５に実装し
た従来の構造を示す。半導体チップ３および基板１，５
は図２(a)とほぼ同条件としている。この半導体実装構
造によれば、キャリヤ基板１に形成されるスルーホール
９などが、インピーダンス整合されない非整合部分Ｐ
（１ｍｍ程度）となるため、図３(b)に示した周波数と
反射との関係においてピークが２５ＧＨｚ付近となり、
図２(a)の実装構造に比べて周波数特性が悪くなる。FIG. 3A shows a conventional structure in which semiconductor chips 3 are individually mounted on a carrier substrate 1 and each carrier substrate 1 is mounted on a mounting substrate 5 opposed to the surface of the substrate 1 which is opposite to the semiconductor chip 3. Show. Semiconductor chip 3 and substrates 1, 5
Are almost the same as those in FIG. According to this semiconductor mounting structure, the through-holes 9 formed in the carrier substrate 1 and the like do not match the impedance-unmatched portions P
(About 1 mm), the peak is around 25 GHz in the relationship between the frequency and the reflection shown in FIG.
The frequency characteristic becomes worse as compared with the mounting structure of FIG.
【００２０】図４(a)は従来の一般的なパッケージＩＣ
を実装した構造を示し、この実装構造によれば、シリコ
ンＩＣ１０を囲むパッケージ材１１の内外のリード１２
やボンディングワイヤ１３が、インピーダンス整合され
ない非整合部分Ｐとなるため、場合によっては４ｍｍ〜
１０ｍｍ程度の非整合部分Ｐを持つことになる。そのた
め、図４(b)に示した周波数と反射との関係においてピ
ークが１ＧＨｚ付近となり、図２(a)の実装構造に比べ
て周波数特性がさらに悪くなる。FIG. 4A shows a conventional general package IC.
According to this mounting structure, the leads 12 inside and outside the package material 11 surrounding the silicon IC 10 are shown.
And the bonding wire 13 becomes a non-matching portion P where impedance matching is not performed.
It has a non-aligned portion P of about 10 mm. Therefore, in the relationship between the frequency and the reflection shown in FIG. 4B, the peak is around 1 GHz, and the frequency characteristic is further deteriorated as compared with the mounting structure in FIG.
【００２１】なお、図１を用いて説明した実施の形態で
は基板５に半導体チップ３を収容する貫通穴７を形成し
たが、貫通穴７に代えて図５に示すような凹部１４を形
成しても同様の効果が得られる。In the embodiment described with reference to FIG. 1, the through hole 7 for accommodating the semiconductor chip 3 is formed in the substrate 5, but a recess 14 as shown in FIG. The same effect can be obtained.
【００２２】また、図６に示すように、十分に薄い半導
体チップ３を用い、半導体チップ３−基板１間の接合バ
ンプ４の高さと、基板１−基板５間の接合バンプ８の高
さを相違させることにより、基板５を平面構造、すなわ
ち貫通穴や凹部のない構造にすることも可能である。As shown in FIG. 6, a sufficiently thin semiconductor chip 3 is used, and the height of the bonding bump 4 between the semiconductor chip 3 and the substrate 1 and the height of the bonding bump 8 between the substrate 1 and the substrate 5 are reduced. By making the difference, the substrate 5 can have a planar structure, that is, a structure having no through-hole or concave portion.
【００２３】さらには、図５や図６に示したような構造
において、半導体チップ３と基板５とが接触するように
構成したり、あるいは半導体チップ３に放熱グリスなど
を塗布することにより、チップＩＣの放熱性を高め熱抵
抗を低減することも可能である。基板５側に放熱を兼ね
た導体パターンを形成しておくことで更に放熱性を高め
ることも可能である。Further, in the structure shown in FIGS. 5 and 6, the semiconductor chip 3 and the substrate 5 are configured to be in contact with each other, or the semiconductor chip 3 is coated with heat-radiating grease or the like. It is also possible to enhance the heat dissipation of the IC and reduce the thermal resistance. By forming a conductor pattern that also functions as heat radiation on the substrate 5 side, it is possible to further enhance heat radiation.
【００２４】[0024]
【発明の効果】以上のように本発明によれば、電気的接
続接点となる突起を備えた半導体チップを個々にあるい
は少数個ずつキャリヤ基板に実装し、そのキャリヤ基板
を半導体チップ側の基板表面に対向する実装基板に実装
した構造とすることにより、高周波特性、並びに信頼性
の向上を実現できる。As described above, according to the present invention, semiconductor chips each having a projection serving as an electrical connection contact are mounted individually or in small numbers on a carrier substrate, and the carrier substrate is mounted on the substrate surface on the semiconductor chip side. With the structure mounted on the mounting substrate facing the above, improvement in high-frequency characteristics and reliability can be realized.
【図1】本発明の第１の実施の形態における半導体実装
構造を持った集積回路の断面図および一部平面図FIG. 1 is a cross-sectional view and a partial plan view of an integrated circuit having a semiconductor mounting structure according to a first embodiment of the present invention.
【図2】図１に示した半導体実装構造における周波数特
性を説明するための実装構造図および周波数と反射との
関係を示すグラフFIG. 2 is a mounting structure diagram for explaining frequency characteristics in the semiconductor mounting structure shown in FIG. 1 and a graph showing a relationship between frequency and reflection.
【図3】従来の半導体実装構造における周波数特性を説
明するための実装構造図および周波数と反射との関係を
示すグラフFIG. 3 is a mounting structure diagram for explaining frequency characteristics in a conventional semiconductor mounting structure and a graph showing a relationship between frequency and reflection.
【図4】従来の他の半導体実装構造における周波数特性
を説明するための実装構造図および周波数と反射との関
係を示すグラフFIG. 4 is a mounting structure diagram for explaining frequency characteristics of another conventional semiconductor mounting structure and a graph showing a relationship between frequency and reflection.
【図5】本発明の第２の実施の形態における半導体実装
構造を持った集積回路の断面図FIG. 5 is a cross-sectional view of an integrated circuit having a semiconductor mounting structure according to a second embodiment of the present invention.
【図6】本発明の第３の実施の形態における半導体実装
構造を持った集積回路の断面図FIG. 6 is a sectional view of an integrated circuit having a semiconductor mounting structure according to a third embodiment of the present invention.
【図7】従来の半導体実装構造を持った集積回路の断面
図および一部平面図FIG. 7 is a cross-sectional view and a partial plan view of an integrated circuit having a conventional semiconductor mounting structure.
１ キャリヤ基板 ２ 導体パターン ３ 半導体チップ ４ 接合バンプ ５ 実装基板 ６ 導体パターン ７ 貫通穴 ８ 接合バンプ 14 凹部 DESCRIPTION OF SYMBOLS 1 Carrier board 2 Conductor pattern 3 Semiconductor chip 4 Bonding bump 5 Mounting board 6 Conductor pattern 7 Through hole 8 Bonding bump 14 Depression
Claims (4)
体チップをキャリヤ基板に実装し、前記キャリヤ基板を
半導体チップ側のキャリヤ基板表面に対向する実装基板
に実装したことを特徴とする半導体実装構造。1. A semiconductor mounting, comprising: mounting a semiconductor chip having a projection serving as an electrical connection contact on a carrier substrate; and mounting the carrier substrate on a mounting substrate facing a surface of the carrier substrate on the semiconductor chip side. Construction.
実装したことを特徴とする請求項１記載の半導体実装構
造。2. The semiconductor mounting structure according to claim 1, wherein the semiconductor chips are mounted one by one on a carrier substrate.
穴を有したことを特徴とする請求項１記載の半導体実装
構造。3. The semiconductor mounting structure according to claim 1, wherein the mounting substrate has a through hole for accommodating the semiconductor chip.
を有したことを特徴とする請求項１記載の半導体実装構
造。4. The semiconductor mounting structure according to claim 1, wherein the mounting substrate has a recess for accommodating the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000028471A JP2001217280A (en) | 2000-02-07 | 2000-02-07 | Semiconductor mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000028471A JP2001217280A (en) | 2000-02-07 | 2000-02-07 | Semiconductor mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001217280A true JP2001217280A (en) | 2001-08-10 |
Family
ID=18553869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000028471A Pending JP2001217280A (en) | 2000-02-07 | 2000-02-07 | Semiconductor mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001217280A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7678589B2 (en) | 2006-06-20 | 2010-03-16 | Denso Corporation | Semiconductor device for providing capacitive semiconductor sensor and method for manufacturing capacitive semiconductor sensor |
| JP2010141365A (en) * | 2010-03-23 | 2010-06-24 | Panasonic Electric Works Co Ltd | Semiconductor device and method of manufacturing the same |
| US7762134B2 (en) | 2006-09-20 | 2010-07-27 | Denso Corporation | Dynamic quantity sensor |
| DE102006049004B4 (en) * | 2005-10-21 | 2011-03-31 | DENSO CORPORATION, Kariya-shi | Sensor with semiconductor chip and circuit chip |
-
2000
- 2000-02-07 JP JP2000028471A patent/JP2001217280A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006049004B4 (en) * | 2005-10-21 | 2011-03-31 | DENSO CORPORATION, Kariya-shi | Sensor with semiconductor chip and circuit chip |
| US7678589B2 (en) | 2006-06-20 | 2010-03-16 | Denso Corporation | Semiconductor device for providing capacitive semiconductor sensor and method for manufacturing capacitive semiconductor sensor |
| US7762134B2 (en) | 2006-09-20 | 2010-07-27 | Denso Corporation | Dynamic quantity sensor |
| DE102007044204B4 (en) * | 2006-09-20 | 2012-02-09 | Denso Corporation | Sensor of a dynamic size |
| JP2010141365A (en) * | 2010-03-23 | 2010-06-24 | Panasonic Electric Works Co Ltd | Semiconductor device and method of manufacturing the same |
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