JP2001210601A - Semiconductor manufacturing method and device therefor - Google Patents

Semiconductor manufacturing method and device therefor

Info

Publication number
JP2001210601A
JP2001210601A JP2000020218A JP2000020218A JP2001210601A JP 2001210601 A JP2001210601 A JP 2001210601A JP 2000020218 A JP2000020218 A JP 2000020218A JP 2000020218 A JP2000020218 A JP 2000020218A JP 2001210601 A JP2001210601 A JP 2001210601A
Authority
JP
Japan
Prior art keywords
temperature
phosphine
reaction furnace
substrate
phosphorus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000020218A
Other languages
Japanese (ja)
Inventor
Yoshitaka Ooura
由貴 大浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Kokusai Electric Inc
Original Assignee
Hitachi Kokusai Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Kokusai Electric Inc filed Critical Hitachi Kokusai Electric Inc
Priority to JP2000020218A priority Critical patent/JP2001210601A/en
Publication of JP2001210601A publication Critical patent/JP2001210601A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To enable a silicon film to be doped with phosphorus using PH3 (phosphine) in a batch reaction furnace. SOLUTION: A semiconductor manufacturing method includes a thermal diffusion process, in which phospine or mixed gas that contains phosphine is introduced into reaction furnaces 1 and 3 which thermally treat wafers 5 so as to be diffused into a silicon film on a wafer 5. By conducting thermal diffusion process is carried out, in such a manner in which the wafer 5 is introduced into a reaction furnace which is heated to a temperature (e.g. 350 deg.C) at which anatural oxide film is hardly influenced, and which is lower than a prescribed treatment temperature (e.g. 800 deg.C), phosphine or mixed gas containing phosphine is introduced into the reaction furnace 1 as the reaction furnace is gradually raised to the above treatment temperature (e.g. 800 deg.C) at a prescribed temperature rise rate (e.g. 5 to 20 deg.C/min) by controlling a heater 2, and phosphorus doping is carried out.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ガラスやウェハ等
の基板上に形成される下地膜であるポリシリコン膜やア
モルファスシリコン膜などのシリコン膜中に燐を拡散さ
せる工程を有する半導体製造方法、及び、該方法を実施
する装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method comprising a step of diffusing phosphorus into a silicon film such as a polysilicon film or an amorphous silicon film which is a base film formed on a substrate such as glass or a wafer. And an apparatus for performing the method.

【0002】[0002]

【従来の技術】従来、燐(P)がドープされたポリシリ
コン(Poly−Si)膜を形成するには、POCl3
(オキシ塩化リン)を用いてPoly−Si膜に燐を拡
散させる方法や、PH3(ホスフィン)とSiH4 等の
シラン系ガスを用いてCVD法によりD−Poly−S
i(ドープトポリシリコン)膜を成膜する方法などがあ
る。
2. Description of the Related Art Conventionally, to form a polysilicon (Poly-Si) film doped with phosphorus (P), POCl 3 is used.
(Phosphorus oxychloride) to diffuse phosphorus into the Poly-Si film, or D-Poly-S by CVD using a silane-based gas such as PH 3 (phosphine) and SiH 4.
There is a method of forming an i (doped polysilicon) film.

【0003】近年、メモリの集積化や小型化に伴い、小
型化及び表面積の増大に対する技術が開発されてきてい
る。その技術を生かすためには、従来のPOCl3を用
いる方法やPH3とシラン系ガスを用いるCVD法では
対応できなくなってきた。そこで、バッチ式の真空保持
可能な反応炉を用いてPH3 による燐ドープを試みた。
In recent years, with the integration and miniaturization of memories, techniques for miniaturizing and increasing the surface area have been developed. In order to make use of this technology, it has become impossible to cope with the conventional method using POCl 3 or the CVD method using PH 3 and a silane-based gas. Therefore, phosphorus doping with PH3 was attempted using a batch-type reactor capable of holding a vacuum.

【0004】[0004]

【発明が解決しようとする課題】しかし、ウェハを搭載
したボートを反応炉内に挿入した後、基板を昇温させ、
基板の温度が所望の基板処理温度(800℃等)に達し
て安定化した段階で、PソースであるPH3(ホスフィ
ン)を導入する、という従来のシーケンスを実行して
も、有効な燐ドープが行われなかった。
However, after the boat on which the wafer is mounted is inserted into the reaction furnace, the temperature of the substrate is raised,
Even when the conventional sequence of introducing PH 3 (phosphine) as a P source is performed when the substrate temperature reaches a desired substrate processing temperature (eg, 800 ° C.) and is stabilized, effective phosphorus doping is performed. Was not done.

【0005】本発明は、上記事情を考慮し、PH3(ホ
スフィン)を用い、バッチ式の反応炉にてシリコン膜に
燐ドープすることができ、さらに燐濃度を制御すること
ができる半導体製造方法、及び、半導体製造装置を提供
することを目的とする。
SUMMARY OF THE INVENTION In view of the above circumstances, the present invention provides a semiconductor manufacturing method capable of doping phosphorus into a silicon film in a batch-type reactor using PH 3 (phosphine) and controlling the phosphorus concentration. , And a semiconductor manufacturing apparatus.

【0006】[0006]

【課題を解決するための手段】請求項1の発明は、基板
を熱処理する反応炉内に、ホスフィン又はホスフィンを
含む混合ガスを導入することにより、基板のシリコン膜
中に燐を拡散させる熱拡散工程を有する半導体製造方法
において、熱拡散工程を実行するに際し、基板を予め定
められた基板処理温度よりも低い温度で反応炉内に挿入
した後、反応炉内の温度を前記基板処理温度まで所定の
温度上昇率にて上昇させつつ、ホスフィン又はホスフィ
ンを含む混合ガスを反応炉内に導入することを特徴とす
る。
According to a first aspect of the present invention, a phosphine or a mixed gas containing phosphine is introduced into a reaction furnace for heat-treating a substrate to diffuse phosphorus into a silicon film of the substrate. In the semiconductor manufacturing method having a step, in performing the thermal diffusion step, after inserting the substrate into the reaction furnace at a temperature lower than a predetermined substrate processing temperature, the temperature in the reaction furnace is reduced to the substrate processing temperature by a predetermined amount. It is characterized in that phosphine or a mixed gas containing phosphine is introduced into the reaction furnace while increasing the temperature at a rate of temperature increase.

【0007】この発明では、反応炉内に基板を挿入した
後、炉内温度を基板処理温度まで所定の温度上昇率にて
上昇させながら、同時に燐ソースであるホスフィン(P
3)又はホスフィンを含む混合ガスを炉内に導入して
熱拡散を行うようにしたので、基板のシリコン膜に燐を
ドープすることができる。その際、温度上昇率を変化さ
せることにより、シリコン膜中に拡散させる燐の濃度を
制御することができる(請求項2)。その場合の温度上
昇率は5〜20℃/minの範囲で設定することが望ましい
(請求項3)。
According to the present invention, after a substrate is inserted into a reaction furnace, the temperature in the furnace is raised to a substrate processing temperature at a predetermined temperature increase rate, and at the same time, phosphine (P) as a phosphorus source is used.
Since a gas mixture containing H 3 ) or phosphine is introduced into the furnace for thermal diffusion, the silicon film on the substrate can be doped with phosphorus. At this time, the concentration of phosphorus diffused into the silicon film can be controlled by changing the rate of temperature rise (claim 2). In this case, it is desirable that the rate of temperature rise be set in the range of 5 to 20 ° C./min.

【0008】請求項4の発明は、上記の製造方法を実施
するためのものであって、基板のシリコン膜中に燐を熱
拡散させるための反応炉と、反応炉内の雰囲気温度を調
節するヒータと、反応炉内にホスフィン又はホスフィン
を含む混合ガスを導入するガス導入手段と、反応炉内に
基板を挿入するときに前記ヒータを制御して反応炉内を
予め定められた基板処理温度よりも低い自然酸化膜の影
響の少ない温度に設定し、基板挿入後、前記ヒータを制
御して反応炉内の温度を前記基板処理温度まで所定の温
度上昇率にて上昇させると共に、前記ガス導入手段を制
御してホスフィン又はホスフィンを含む混合ガスを反応
炉内に導入させる制御手段とを備えることを特徴として
いる。
According to a fourth aspect of the present invention, there is provided a reaction furnace for thermally diffusing phosphorus into a silicon film of a substrate, and an atmosphere temperature in the reaction furnace is adjusted. A heater, gas introduction means for introducing phosphine or a mixed gas containing phosphine into the reaction furnace, and controlling the heater when a substrate is inserted into the reaction furnace to control the inside of the reaction furnace from a predetermined substrate processing temperature. After the insertion of the substrate, the heater is controlled to increase the temperature in the reaction furnace to the substrate processing temperature at a predetermined temperature increase rate, and the gas introducing means is set. Phosphine or a mixed gas containing phosphine into the reaction furnace.

【0009】[0009]

【発明の実施の形態】以下、本発明の実施形態を図面を
参照しながら説明する。図1は実施形態の半導体製造方
法を実施するための半導体製造装置を示す。図におい
て、1は外部反応管で、外部反応管1の周囲には、外部
反応管1内の雰囲気温度を上昇させるヒータ2が配置さ
れている。外部反応管1内には筒状の内部反応管3が設
けられ、内部反応管3により反応室が画成されている。
そして、内部反応管3内に画成された反応室に、ボート
4に保持されたウェハ5が挿入されるようになってい
る。外部反応管1及び内部反応管3で構成される反応炉
内は、ボート4が載置される炉蓋により気密に閉塞され
るようになっている。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor manufacturing apparatus for performing the semiconductor manufacturing method according to the embodiment. In the figure, reference numeral 1 denotes an external reaction tube, and around the external reaction tube 1, a heater 2 for increasing the ambient temperature in the external reaction tube 1 is arranged. A cylindrical internal reaction tube 3 is provided in the external reaction tube 1, and a reaction chamber is defined by the internal reaction tube 3.
The wafer 5 held by the boat 4 is inserted into a reaction chamber defined in the internal reaction tube 3. The inside of the reaction furnace constituted by the outer reaction tube 1 and the inner reaction tube 3 is airtightly closed by a furnace lid on which the boat 4 is placed.

【0010】燐(P)ソースであるホスフィン(P
3)は、反応ガス導入管6より内部反応管3の内側に
導入される。反応ガス導入管6は、途中で分岐してお
り、内部反応管3内の下端から、又、内部反応管3の内
側に配した反応ガス導入ノズル9から、内部反応管3内
の反応室にホスフィンを供給する。この場合のホスフィ
ンの導入流量は、反応ガス導入管6の途中に設けられた
流量調整器(マスフローコントローラ)11、12によ
って調整される。又、内部反応管3で画成された反応室
内のガスは、内部反応管3の上端を通って、外部反応管
1と内部反応管3の間に確保された流路を経由し、外部
反応管1の下端に設けた排気口8から反応炉外に排出さ
れる。なお、ボート4は、図示しない回転機構によって
回転されるようになっている。又、この装置には図示し
ない制御手段が設けられており、この制御手段により、
ヒータ2による炉内温度制御、及び、炉内へのホスフィ
ンの供給制御が行われるようになっている。
Phosphine (P) which is a phosphorus (P) source
H 3 ) is introduced from the reaction gas introduction tube 6 to the inside of the internal reaction tube 3. The reaction gas introduction pipe 6 branches on the way, and from the lower end in the internal reaction pipe 3 and from the reaction gas introduction nozzle 9 arranged inside the internal reaction pipe 3, to the reaction chamber in the internal reaction pipe 3. Supply phosphine. In this case, the introduction flow rate of phosphine is adjusted by flow regulators (mass flow controllers) 11 and 12 provided in the middle of the reaction gas introduction pipe 6. The gas in the reaction chamber defined by the internal reaction tube 3 passes through the upper end of the internal reaction tube 3, passes through a flow path secured between the external reaction tube 1 and the internal reaction tube 3, and The gas is discharged from the reactor through an exhaust port 8 provided at the lower end of the tube 1. The boat 4 is rotated by a rotation mechanism (not shown). The apparatus is provided with control means (not shown).
Furnace temperature control by the heater 2 and supply control of phosphine into the furnace are performed.

【0011】次に、この装置によって実施される半導体
製造方法を説明する。ウェハ5上のシリコン膜に対して
燐のドープを行う場合には、まず、自然酸化膜の影響が
少ない挿入温度(例えば、約350℃)に炉内温度を制
御し、所定枚数のウェハ5を搭載したボード4を炉内に
挿入(ロード)する。
Next, a semiconductor manufacturing method performed by this apparatus will be described. When doping the silicon film on the wafer 5 with phosphorus, first, the furnace temperature is controlled to an insertion temperature (for example, about 350 ° C.) where the influence of the natural oxide film is small, and a predetermined number of wafers 5 are removed. The mounted board 4 is inserted (loaded) into the furnace.

【0012】ボート4をロードしたら、炉内を所定の圧
力(例えば、640Pa程度の圧力)に維持し、反応炉
内の温度を所定の温度上昇率にて上昇させる。本実施形
態においては、20℃/min程度の温度上昇率にて昇温を
行った。又、昇温と同時に、反応炉内に燐ソースである
ホスフィン(PH3)の供給も行う。ホスフィンの供給
量は、例えば480(0.5%PH3/Heベース)scm
m程度とする。反応炉内の温度が基板処理温度(本実施
形態においては800℃程度)に到達した後も、燐ソー
スであるホスフィンの供給は、燐の拡散処理が終了する
まで続ける。
After loading the boat 4, the inside of the furnace is maintained at a predetermined pressure (for example, a pressure of about 640 Pa), and the temperature in the reaction furnace is increased at a predetermined temperature increase rate. In the present embodiment, the temperature was raised at a temperature rise rate of about 20 ° C./min. At the same time as the temperature is raised, phosphine (PH 3 ) as a phosphorus source is supplied into the reactor. The supply amount of phosphine is, for example, 480 (0.5% PH 3 / He base) scm
m. Even after the temperature in the reactor reaches the substrate processing temperature (about 800 ° C. in the present embodiment), the supply of phosphine as a phosphorus source is continued until the phosphorus diffusion processing is completed.

【0013】拡散処理が終了したら、ホスフィンの供給
をスットプし、反応炉内の残留ガスを除去して、反応炉
内の圧力を大気圧に戻す。又、反応炉内の温度は、処理
温度よりも若干低い温度、例えば600℃程度まで下げ
る。その後、燐ドープ処理を施したウェハ5を保持して
いるボート4を、反応炉内よりアンロードし、ウェハ5
を回収する。
When the diffusion process is completed, the supply of phosphine is stopped, the residual gas in the reactor is removed, and the pressure in the reactor is returned to the atmospheric pressure. Further, the temperature in the reaction furnace is lowered to a temperature slightly lower than the processing temperature, for example, about 600 ° C. Thereafter, the boat 4 holding the phosphorus-doped wafers 5 is unloaded from the reactor, and
Collect.

【0014】上記のように、本実施形態においては、自
然酸化膜の影響の少ない挿入温度(約350℃)でウェ
ハ5を挿入した後、反応炉内温度を上昇させ始めるタイ
ミングから燐ソースであるホスフィンPH3を供給し、
しかも、ホスフィンを供給しつつ、所定の温度上昇率に
て処理温度まで昇温を行うようにしたので、ウェハ5の
シリコン膜に所望の濃度の燐Pを拡散することができ
た。これは、表面のH2被覆率とP被覆率の関係により
低温時(400℃以下)ではH2の被覆率が大きいが、
温度を上昇することにより水素脱離が生じ、それに伴い
Pの被覆率が上昇しP濃度が高くなる。さらに550℃
以上ではP脱離も生じているが、PH3を流し続けるこ
とにより、P脱離を抑制することができ、十分に拡散を
行なうことができるためであると考えられる(なお、P
3を流さない状態で550℃以上で放置しておくとP
濃度は下がると考えられる)。
As described above, in this embodiment, after the wafer 5 is inserted at the insertion temperature (about 350 ° C.) where the influence of the natural oxide film is small, the phosphorus source is used from the timing when the temperature inside the reaction furnace is started to rise. to supply phosphine PH 3,
In addition, since the temperature is raised to the processing temperature at a predetermined temperature increase rate while supplying phosphine, a desired concentration of phosphorus P can be diffused into the silicon film of the wafer 5. This is at a low temperature by the relationship of H 2 coverage and P coverage of the surface (400 ° C. or less) in the H 2 coverage is large,
Increasing the temperature causes hydrogen desorption, which increases the coverage of P and increases the P concentration. 550 ° C
Although P desorption occurs in the above, it is considered that P desorption can be suppressed and PH can be sufficiently diffused by continuing the flow of PH 3 (P.
If left at 550 ° C or higher without flowing H 3 , P
The concentration is expected to decrease).

【0015】具体的には、燐濃度=平均9.45×10
19atoms/cc 、面内均一性=2.7〜3.9%を得るこ
とができた。この結果を処理温度到達後にホスフィン
(PH 3)を供給した場合(従来のシーケンスで行った
場合)と比較して、次の表1に示す。
Specifically, phosphorus concentration = average 9.45 × 10
19atoms / cc, in-plane uniformity = 2.7 to 3.9%
I was able to. After the processing temperature reaches the phosphine
(PH Three) Is supplied (performed in the conventional sequence)
Case 1) is shown in Table 1 below.

【0016】[0016]

【表1】 [Table 1]

【0017】なお、燐の濃度は、図2に示すように、ウ
ェハ5の所定の5つのポイントにて蛍光X線分析装置に
て測定した。即ち、直径φ200(8インチ)のウェハ
5の中心のポイントと、中心から55mmの円周方向に
等間隔の4つのポイントである。なお各ポイントにおけ
る燐濃度測定範囲は、各ポイントを中心とするφ23m
mの円の内部である。
As shown in FIG. 2, the concentration of phosphorus was measured at five predetermined points on the wafer 5 by an X-ray fluorescence analyzer. In other words, there are four points at the center of the wafer 5 having a diameter of φ200 (8 inches) and four equally spaced points in the circumferential direction of 55 mm from the center. The phosphorus concentration measurement range at each point is φ23m centered on each point.
m inside the circle.

【0018】又、処理温度を750℃とし、温度上昇率
を5℃/minと10℃/minの2通りに変えて処理した場合
の結果を次の表2に示す。
Table 2 shows the results when the treatment temperature was set at 750 ° C. and the temperature was increased at two different rates, 5 ° C./min and 10 ° C./min.

【0019】[0019]

【表2】 [Table 2]

【0020】この場合も、前者が、燐濃度=平均6.0
5×1019atoms/cc 、面内均一性=6.2〜5.9
%、後者が燐濃度=平均8.03×1019atoms/cc 、
面内均一性=1.0〜4.2%という、前記同様の良好
な結果を得ることができた。以上のデータにより、温度
上昇率を高くする方が、燐濃度を高くすることができ、
面内均一性も良好にすることができることが分かる。従
って、温度上昇率を変化させることにより、燐濃度を制
御することが可能である。
Also in this case, the former is based on the phosphorus concentration = 6.0 on average.
5 × 10 19 atoms / cc, in-plane uniformity = 6.2 to 5.9
%, The latter being phosphorus concentration = 8.03 × 10 19 atoms / cc on average,
As a result, the same excellent result as in-plane uniformity = 1.0 to 4.2% was obtained. According to the above data, the higher the temperature rise rate, the higher the phosphorus concentration,
It can be seen that the in-plane uniformity can be improved. Therefore, it is possible to control the phosphorus concentration by changing the rate of temperature rise.

【0021】なお、温度上昇率は、5〜20℃/minの範
囲の任意の値を採ることができる。又、処理温度も75
0℃や800℃に限定されるものではない。又、処理ガ
ス導入管6から炉内に導入するガスは、ホスフィンのみ
に限らず、ホスフィンを含む混合ガスであってもよい。
The temperature rise rate can take any value in the range of 5 to 20 ° C./min. Also, the processing temperature is 75
It is not limited to 0 ° C. or 800 ° C. The gas introduced into the furnace from the processing gas introduction pipe 6 is not limited to phosphine, but may be a mixed gas containing phosphine.

【0022】[0022]

【発明の効果】以上説明したように、本発明によれば、
反応炉内に基板を挿入した後、炉内温度を基板処理温度
まで所定の温度上昇率にて上昇させながら、同時に燐ソ
ースであるホスフィン(PH3)又はホスフィンを含む
混合ガスを炉内に導入して熱拡散を行うようにしている
ので、基板のシリコン膜に燐を確実にドープすることが
できる。その際、温度上昇率を変化させれば、シリコン
膜中に拡散させる燐の濃度を制御することもできる。従
って、現状のバッチ式の反応炉を用いて、メモリの高集
積化を可能にすることができる。
As described above, according to the present invention,
After the substrate is inserted into the reaction furnace, the temperature inside the furnace is raised to the substrate processing temperature at a predetermined rate while simultaneously introducing phosphine (PH 3 ) as a phosphorus source or a mixed gas containing phosphine into the furnace. In this case, thermal diffusion is performed, so that the silicon film on the substrate can be doped with phosphorus without fail. At this time, by changing the rate of temperature rise, the concentration of phosphorus diffused into the silicon film can be controlled. Therefore, high integration of the memory can be realized by using the current batch type reaction furnace.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態の半導体製造装置の概略構成
図である。
FIG. 1 is a schematic configuration diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

【図2】燐濃度の測定ポイントを示す図である。FIG. 2 is a diagram showing measurement points of phosphorus concentration.

【符号の説明】[Explanation of symbols]

1 外部反応管(反応炉) 2 ヒータ 3 内部反応管(反応炉) 5 ウェハ(基板) 6 処理ガス導入管 DESCRIPTION OF SYMBOLS 1 External reaction tube (reactor) 2 Heater 3 Internal reaction tube (reactor) 5 Wafer (substrate) 6 Processing gas introduction tube

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板を熱処理する反応炉内に、ホスフィ
ン又はホスフィンを含む混合ガスを導入することによ
り、基板のシリコン膜中に燐を拡散させる熱拡散工程を
有する半導体製造方法において、 前記熱拡散工程を実行するに際し、基板を予め定められ
た基板処理温度よりも低い温度で反応炉内に挿入した
後、反応炉内の温度を前記基板処理温度まで所定の温度
上昇率にて上昇させつつ、ホスフィン又はホスフィンを
含む混合ガスを反応炉内に導入することを特徴とする半
導体製造方法。
1. A method for manufacturing a semiconductor device comprising a heat diffusion step of diffusing phosphorus into a silicon film of a substrate by introducing phosphine or a mixed gas containing phosphine into a reaction furnace for heat-treating the substrate. In performing the process, after inserting the substrate into the reaction furnace at a temperature lower than a predetermined substrate processing temperature, while increasing the temperature in the reaction furnace to the substrate processing temperature at a predetermined temperature increase rate, A semiconductor manufacturing method, wherein phosphine or a mixed gas containing phosphine is introduced into a reaction furnace.
【請求項2】 前記温度上昇率を変化させることによ
り、シリコン膜中に拡散させる燐の濃度を制御すること
を特徴とする請求項1記載の半導体製造方法。
2. The method according to claim 1, wherein the concentration of phosphorus diffused into the silicon film is controlled by changing the rate of temperature rise.
【請求項3】 前記所定の温度上昇率を5〜20℃/min
の範囲で設定することを特徴とする請求項1又は2記載
の半導体製造方法。
3. The method according to claim 1, wherein the predetermined temperature rise rate is 5 to 20 ° C./min.
The method according to claim 1, wherein the semiconductor device is set in a range of:
【請求項4】 基板のシリコン膜中に燐を熱拡散させる
ための反応炉と、 反応炉内の雰囲気温度を調節するヒータと、 反応炉内にホスフィン又はホスフィンを含む混合ガスを
導入するガス導入手段と、 反応炉内に基板を挿入するときに前記ヒータを制御して
反応炉内を予め定められた基板処理温度よりも低い温度
に設定し、基板挿入後、前記ヒータを制御して反応炉内
の温度を前記基板処理温度まで所定の温度上昇率にて上
昇させながら、前記ガス導入手段を制御してホスフィン
又はホスフィンを含む混合ガスを反応炉内に導入させる
制御手段とを備えたことを特徴とする半導体製造装置。
4. A reaction furnace for thermally diffusing phosphorus into a silicon film of a substrate, a heater for adjusting an ambient temperature in the reaction furnace, and a gas introduction for introducing phosphine or a mixed gas containing phosphine into the reaction furnace. Means for controlling the heater when inserting a substrate into the reaction furnace, setting the inside of the reaction furnace to a temperature lower than a predetermined substrate processing temperature, and controlling the heater after inserting the substrate to control the heater. Control means for controlling the gas introduction means to introduce phosphine or a mixed gas containing phosphine into the reaction furnace while raising the internal temperature to the substrate processing temperature at a predetermined temperature increase rate. Characteristic semiconductor manufacturing equipment.
JP2000020218A 2000-01-28 2000-01-28 Semiconductor manufacturing method and device therefor Pending JP2001210601A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000020218A JP2001210601A (en) 2000-01-28 2000-01-28 Semiconductor manufacturing method and device therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000020218A JP2001210601A (en) 2000-01-28 2000-01-28 Semiconductor manufacturing method and device therefor

Publications (1)

Publication Number Publication Date
JP2001210601A true JP2001210601A (en) 2001-08-03

Family

ID=18546819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000020218A Pending JP2001210601A (en) 2000-01-28 2000-01-28 Semiconductor manufacturing method and device therefor

Country Status (1)

Country Link
JP (1) JP2001210601A (en)

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