JP2001209349A - Display driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily actualize scrolling. SOLUTION: The timing in which each common line driven repeatedly in sequence is driven individually is delayed or advanced by a specific pitch at intervals at every specific number of frames.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving apparatus for a dot matrix display panel such as a liquid crystal display, and more particularly to a technique for easily realizing vertical scrolling.

[0002]

2. Description of the Related Art A dot matrix liquid crystal display driving device is
The outline is configured as shown in FIG. 1 is nx
An m-dot liquid crystal dot matrix display panel, an n-bit common signal driver for driving n common lines of the display panel 1, and an m-bit segment signal for driving m segment lines of the panel 1. Driver.

The common signal driver 2 is controlled by an n-bit shift register 4 'to drive the common lines sequentially and cyclically. The segment signal driver 3 takes in the m-bit data latched by the m-bit latch circuit 5 and sends it out to m segment lines every time one common line is driven. 6 is character ROM
A parallel / serial data conversion circuit 7 for converting parallel data read from the / RAM or the display RAM into serial data, and an m-bit shift register 7 for taking in the output of the data conversion circuit 6. When data is stored in the m-bit latch circuit 5,
Send the data to

[0004]

By the way, with respect to vertically scrolling the contents displayed on the display panel 1 (display shift in the direction in which the common lines are arranged), conventionally,
This cannot be performed with a display drive device having a character ROM / RAM. Also, in a driving device that uses a bitmap type display RAM to write display data therein, vertical scrolling can be realized by rewriting the contents of the display RAM, but this method requires a large amount of programs, There is a problem that the number of execution instructions increases, the current consumption increases, and the time for rewriting RAM data also increases.

An object of the present invention is to provide a display driving apparatus which solves the above-mentioned problem, can easily perform vertical scrolling, and does not increase current consumption.

[0006]

According to a first aspect of the invention, there is provided a common signal driver for sequentially driving a plurality of common lines of a dot matrix display panel one by one, and a plurality of segment lines of the panel. A display driver comprising a segment signal driver for simultaneously driving a predetermined number of selected ones of the above, wherein the common signal driver sets a timing at which each of the common lines is individually driven by a predetermined pitch every predetermined number of frames. Delayed or advanced.

In a second aspect based on the first aspect, when the common signal driver delays the timing by a predetermined pitch, the common signal driver stops driving the common line at the subsequent stage by the number of the delayed timing per frame. I made it.

In a third aspect based on the first aspect, the common signal driver periodically drives each common line.

In a fourth aspect based on any one of the first to third aspects, the shift register for controlling the common signal driver includes a DFF for a common line and the DFF for the common line.
And a data selector for a common line connected in a ring shape. The data register can be switched between a state in which the preceding and following DFFs are directly connected and a state in which data set at a predetermined timing is sent to the subsequent DFF. did.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a dot matrix display content of one digit and two rows (common signals COM1 to COM16, segment signals SEG1 to SEG5) on a display panel 1. FIG. (a) is a normal display (no scrolling), (b) is a display obtained by moving the display of (a) one dot upward, and (c) is a display obtained by moving the display one dot higher than (b). is there. (D) moves the display of (a) downward by one dot, and (e) moves the display of (a) upward by one dot and brings the display missing on the upper side to the lower side. (F) is
(e) is further moved one dot upward. (a) → (b) → (c), and (a) → (e) → (f),
A vertical scroll operation is performed. In this embodiment, the vertical scroll is realized by controlling the output timing of the common signals COM1 to COM16.

In the present embodiment, the shift register 4 for transmitting a signal to the common signal driver 2 shown in FIG. 9 has the configuration shown in FIG. The shift register 4 has 16 DFFs 41 connected in a ring via 16 data selectors 42. The data selector 42 outputs the Q output of the preceding DFF 41 and the D output of the subsequent DFF 41.
It is connected between the D input of the FF 41 and when the externally set data is output, the input and output are cut off. Otherwise, the input and output are conducted. Each DFF 41
Are sent to the common signal driver 2 as COM1 to COM16. Reference numeral 10 denotes a dot scroll controller controlled by a dot shift instruction from the CPU, and reference numeral 11 denotes a data bus.

FIG. 3 shows the display of FIG. 1A (without scrolling).
Signals (COM1, COM2,...)
., COM15, COM16) and segment signal (SE)
G1, SEG2). In display panel 1,
VDD- is applied between the electrodes by the common signal and the segment signal.
The liquid crystal cell (dot) to which the voltage having the potential difference of V5 is applied turns on (displays). Then, a positive polarity voltage and a negative polarity voltage are applied to the lighting liquid crystal cell in two consecutive frames to prevent the influence of the charge accumulation effect.

In the operation without scrolling shown in FIG. 3 and FIG. 1A, the DF for COM1 is supplied from the dot scroll controller 10 via the data bus 11 by the dot shift instruction at the timing 16 in FIG.
The data selector 42 on the input side of F41 is set to "1", the other data selectors 42 are set to "0",
Output to the output side. Thereafter, after one clock ck (clock synchronized with timings 1 to 16) is input, the input and output of all the data selectors 42 are made conductive. After that, the data selector 42 keeps conduction between input and output.

As described above, every time the clock ck arrives, the data of "1" is sequentially shifted in the DFF 41, and the CFF is shifted in accordance with the timing 1 → 2 →... → 16 → 1 →.
OM1 → COM2 → ... → COM16 → COM1 →
Are sequentially “1”, and at this time, the others are “0”. The data “1” is a drive signal (VDD) whose polarity is inverted by the common signal driver 2 for each cycle (one frame).
Or V5) and output to the display panel 1.

The combination of the segment signals SEG1 to SEG5 is output at every timing 1 → 2 →... → 16.
Combination of G5, segment signal S at timing 2
The polarity of the combination of EG1 to SEG5,..., The combination of the segment signals SEG1 to SEG5 at the timing 16 is inverted in successive frames. Therefore, the content of FIG. 1A is fixedly displayed (no scrolling).

FIG. 4 is a waveform diagram of the common signal and the segment signal when the display of FIG. 1B is performed (moving upward by one dot). Here, the common signals COM1 to COM15
Is delayed by one timing as compared with the case of FIG. Segment signals SEG1 to SEG5
Is not changed. That is, COM1 → C corresponding to timing 2 → 3 →.
OM2 →... → COM15 are sequentially driven. At this time, at timing 1, the common signal COM16 is not driven. Therefore, the content of FIG. 1B is displayed.

This operation is performed at the timing 1 shown in FIG.
Of the input DFF 41 for the COM1 of the shift register 4 is set to "1", the other data selector 42 is set to "0", and output to the output side. Thereafter, after one clock ck is input, the input and output of all the data selectors 42 are made conductive. However, at timing 16, “0” is set to the data selector 42 on the input side of the DFF 41 for COM16. Thereafter, the data setting / input / output conduction of the data selector 42 is repeated for each frame.

FIG. 5 shows the display of FIG.
FIG. 7 is a waveform diagram of a common signal and a segment signal when performing (dot movement). Here, the common signals COM1 to CO
The timing at which M16 is driven is further delayed by one timing as compared with the case of FIG. Segment signal SEG
The switching timing of 1 to SEG5 is not changed.
That is, COM1 → COM2 →... → COM14 are sequentially driven in accordance with the timings 3 → 4 →. At this time, at timings 1 and 2, the common signal CO
M15 and COM16 are not driven. Therefore, the content of FIG. 1C is displayed.

This operation is performed at the timing 2 shown in FIG.
, The data selector 42 on the input side of the DFF 41 for COM3 of the shift register 4 is set to “1”, the other data selectors 42 are set to “0”, and output to the output side. Thereafter, after one clock ck is input, the input and output of all the data selectors 42 are made conductive. However, at timing 16, “0” is set to the data selector 42 on the input side of the DFF 41 for COM15. Thereafter, the data setting / input / output conduction of the data selector 42 is repeated for each frame.

By switching the display operation from FIG. 3 to FIG. 4 to FIG. 5 in units of an integral multiple of two frames, the drive timing of the common signals COM1 to COM16 is delayed by the unit of time. As a result, the display content can be scrolled upward. Contrary to the above, if the drive timing of the common signals COM1 to COM16 is advanced in the unit of time, the display content is scrolled downward (see FIG. 1D and FIG. 6).

Also, in FIGS. 3 to 5, the lower common line is not driven by the amount moved upward, but it is also driven (at timing 16, data of "0" is set in a predetermined data selector 42). Do not.)
The content that has been moved upward and the missing content is located below, as shown in Fig. 1 (e) (Fig. 7).
And FIG. 1 (f) (FIG. 8).

In FIG. 7, corresponding to timings 2 to 16, 1, COM1 → COM2 →... → COM15 → CO
M16 is sequentially driven. In FIG. 8, timing 3 → 4 →
... → 16 → 1 → 2, corresponding to COM1 → COM2 →
... → COM15 → COM16 are driven in order.

In the above description, the upward scroll is performed by delaying the drive timing of the plurality of common lines at a pitch of one dot (one timing) in units of an integral multiple of two frames, and the downward scroll is performed by proceeding. Has been described, but the time unit may be one frame unit or three or more frames. The scroll speed decreases as the number of frames increases. Also, the pitch may be 2 dots or more, and the scroll speed increases as the number of dots increases.

[0024]

As described above, according to the present invention, the drive timing of the common line is delayed or advanced by a predetermined pitch every predetermined number of frames. At this time, there is no need to change the segment signal at all. Therefore, no rewriting of the display RAM is required, and the character ROM / RA
Even when M is used, vertical scrolling can be realized.

[Brief description of the drawings]

FIGS. 1A to 1F are explanatory diagrams of dot matrix display in each case of one digit and two rows of the LCD panel of the present embodiment.

FIG. 2 is a block diagram of a shift register according to the embodiment.

FIG. 3 shows COM1 and CO when the display of FIG.
It is a waveform diagram of M2, COM15, COM16, SEG1, SEG2.

FIG. 4 shows COM1 and CO when the display of FIG.
It is a waveform diagram of M2, COM15, COM16, SEG1, SEG2.

FIG. 5 shows COM1 and CO when the display of FIG.
It is a waveform diagram of M2, COM15, COM16, SEG1, SEG2.

FIG. 6 shows COM1 and CO when the display of FIG.
It is a waveform diagram of M2, COM15, COM16, SEG1, SEG2.

FIG. 7 shows COM1 and CO when the display of FIG.
It is a waveform diagram of M2, COM15, COM16, SEG1, SEG2.

FIG. 8 shows COM1 and CO when the display of FIG.
It is a waveform diagram of M2, COM15, COM16, SEG1, SEG2.

FIG. 9 is a block diagram of a conventional dot matrix liquid crystal display driving device.

[Explanation of symbols]

4: shift register, 41: DFF, 42: data selector.

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2H093 NA16 NC16 NC22 ND49 5C006 AB01 AC22 AF42 AF71 BB12 BC03 BF03 FA00 FA47 5C080 AA10 BB05 DD26 EE04 FF12 GG02 JJ01 JJ02 JJ04

Claims (4)

[Claims] A common signal driver for sequentially driving a plurality of common lines of a dot matrix display panel one by one, and a segment signal driver for simultaneously driving a selected predetermined number of a plurality of segment lines of the panel. The display drive device according to claim 1, wherein the common signal driver delays or advances a timing at which each of the common lines is individually driven by a predetermined pitch every predetermined number of frames. 2. The device according to claim 1, wherein the common signal driver stops driving the common line at a subsequent stage by the number of the delayed timings per frame when delaying the timing by a predetermined pitch. Display driving device. 3. The display driving device according to claim 1, wherein the common signal driver periodically drives each common line. 4. The shift register according to claim 1, wherein the shift register for controlling the common signal driver comprises:
The data register includes a DFF for a common line and a data selector for a common line that connects the DFFs in a ring. The data register sends data set at a predetermined timing to a state in which the preceding and succeeding DFFs are directly connected to a subsequent DFF. A display driving device, wherein the state is switchable.