JP2003108084A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need of a transistor for a reset operation in a field sequential system liquid crystal display device. SOLUTION: The device is provided with a gate driver 22 which successively and selectively outputs gate line signals of a pixel section 21 and a drain driver 23 which supplies writing data signals to drain lines corresponding to respective display data and drives them. During a reset time prior to a display writing time in which the writing data signals corresponding to the display data in a subframe are to be written, the gate line signals are successively and selectively outputted by the driver 22 with a high speed clock that is faster than the speed of the display writing. In synchronism with the above, the driver 23 supplies the writing data signals, that make the transmissivity of the section 21 to be the maximum or the minimum, to all drain lines and drives them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field sequential type liquid crystal display device.

[0002]

2. Description of the Related Art Recently, as a liquid crystal display device for displaying a color image, a liquid crystal element in which a liquid crystal is sandwiched between a pair of substrates having electrodes formed on opposite inner surfaces is used to control light transmission. A liquid crystal display element for displaying an image, a backlight arranged behind the liquid crystal display element for sequentially emitting light of a plurality of colors toward the liquid crystal display element in a predetermined cycle, and displaying one color image For writing a display data corresponding to one of the plurality of colors to the liquid crystal display element for each of a plurality of sub-frames obtained by dividing one frame by the number of colors of light emitted by the backlight. A method for displaying one color image by synthesizing display of a plurality of colors for each of the plurality of sub-frames, the control means causing the backlight to emit light of a color corresponding to the display data. It has been studied ones.

This system is generally called a field-sequential system. In the conventional field-sequential system liquid crystal display device, light of one color is emitted from the backlight for each of the plurality of sub-frames during the sub-frame period. The display data is emitted and the display data corresponding to the one color is written in the liquid crystal display element in that state.

In this field-sequential type liquid crystal display device, since the liquid crystal display element is not provided with a color filter, light is not absorbed by the color filter, and one frame is represented by the number of colors of light emitted by the backlight. A liquid crystal display device using a liquid crystal display element having color filters of a plurality of colors respectively corresponding to a plurality of pixels in order to display one color image by combining bright light of a plurality of colors of a plurality of divided sub-frames Compared with, it is possible to display a bright and high-definition color image.

FIG. 4 shows a general circuit configuration of a conventional field-sequential liquid crystal display device. In the same figure, as the liquid crystal display element, an active matrix type in which thin film transistors (hereinafter referred to as “TFT”) 11a, 11a, ... TFT11
The plurality of gate lines G1 to Gn connected to the gate terminals of a, 11a, ...
A gate driver 12 for supplying a gate signal for turning on a, ... And a plurality of drain lines D1 to Dm connected to the drain terminals of the TFTs 11a, 11a ,. A drain driver 13 for supplying a corresponding write data signal.

At each pixel position of the pixel section 11, the TFT 11 connected to the above gate line and drain line
The source terminal of a is connected to both ends of the liquid crystal capacitance CLC and the auxiliary capacitance CS formed between the pixel electrodes of the liquid crystal, and the other end of the liquid crystal capacitance CLC is connected to the common electrode COM with another pixel to the auxiliary capacitance CS. The other end is connected to the auxiliary capacitance electrode CS, respectively.

In addition, the liquid crystal capacitance CLC and the auxiliary capacitance CS
The source terminal of the reset TFT 11b is also connected to one end of the TFT 11a and the source terminal of the TFT 11a. The reset TFT 11b has a drain terminal to which a reset drain signal RED is applied and a gate electrode to which a reset gate signal REG is applied, common to all pixels.

FIG. 5 exemplifies each signal waveform in the circuit configuration of FIG. 4, wherein the number of gate lines n is “160”, and the gate lines G1 to G160 are sequentially driven for scanning.

Further, the drain latch signal shown in FIG. 5A is generated inside the drain driver 13, and the drain latch signal shown in FIG.
Gate start signal shown in FIG. 5, gate shift signal shown in FIG. 5 (3), each gate signal G shown in FIGS.
It is assumed that all of 1 to G160 are generated inside the gate driver 12.

As shown in FIG. 5 (13), in the field-sequential type liquid crystal display device, "(reset of all pixels)", "(write of display data)" and "(display data) are held for each subframe. And “lighting of the backlight (BL) (while holding display data)” are repeatedly executed.

In the initial "reset" state, FIG.
The reset drain signal shown in (5) becomes the “H” level for one subframe, while one gate is synchronized with the reset gate signal shown in FIG. 5 (6) and the gate shift signal shown in FIG. 5 (3). "H" level only for the scanning time,
As a result, all the gates G1 to G160 are collectively selected as shown in FIGS. 5 (7) to (10), the reset TFTs 11b, 11b, ... Of all the pixels are turned on, and the respective liquid crystal capacitors CLC are turned on. And reset the auxiliary capacitance CS.

In the subsequent "writing" state, as shown in FIGS. 5 (7) to 5 (10), in synchronization with the gate start signal shown in FIG. 5 (2) and the gate shift signal shown in FIG. 5 (3). , All the gates G1 to G160 are sequentially scanned and driven, the display TFTs 11a, 11a, ... Are turned on for each gate line, and the display data shown in FIG. 5 (4) is written.

The display state is changed to the "holding" state from the time when the display writing on the last gate line G160 is completed. In this "holding" state, the backlight provided on the back side of the pixel portion 11 is configured. The LED (light emitting diode) is turned on as shown in FIG. 5 (11) to be turned on, and the held display content is transparently displayed.

In FIG. 5, the reset drain signal shown in FIG. 5 (5) remains "H" during one subframe.
The common electrode COM shown in FIG.
However, this is done in order to drive the liquid crystal display device with an alternating current, and this is done for each sub-frame, and each "L" level and "H" level. And are alternately inverted.

[0015]

As described above, in the conventional general field-sequential liquid crystal display device, the TFT 11a for writing the display data and the resetting TFT 11a for each pixel constituting the pixel portion 11 are provided. TFT1
This requires two TFTs 1b, which leads to a reduction in aperture ratio, a complicated wiring layout on the liquid crystal display element panel, an increase in wiring capacitance, and the like, and a short circuit between the elements. There are many problems such as a factor that reduces the manufacturing yield.

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the aperture ratio of each pixel by eliminating the need for a transistor for reset operation and to improve the liquid crystal display panel. An object of the present invention is to provide a field sequential liquid crystal display device capable of simplifying the wiring.

[0017]

The invention according to claim 1 is
A liquid crystal element in which a liquid crystal is sandwiched between a pair of substrates each having electrodes formed on opposite inner surfaces thereof, and arranged on the inner surface of one of the pair of substrates arranged in a matrix in row and column directions. A plurality of pixel electrodes, a plurality of thin film transistors arranged one by one corresponding to the plurality of pixel electrodes respectively, each source electrode being connected to the corresponding pixel electrode, and wiring corresponding to each pixel electrode row. A plurality of gate lines connected to the gate electrodes of the thin film transistors, a plurality of drain lines connected to the pixel electrode columns and connected to the drain electrodes of the thin film transistors, and the other of the pair of substrates. Has an opposite electrode provided on the inner surface of the substrate and facing the plurality of pixel electrodes, and controls light transmission to display an image. A liquid crystal display element and a backlight arranged behind the liquid crystal display element and sequentially emitting light of a plurality of colors toward the liquid crystal display element in a predetermined cycle are provided for displaying one color image. Writing of display data corresponding to one of the plurality of colors into the liquid crystal display element for each of a plurality of subframes obtained by dividing one frame by the number of colors of light emitted by the backlight; A liquid crystal display device for displaying one color image by synthesizing display of a plurality of colors for each of the plurality of sub-frames by causing a light of a color corresponding to the display data to be emitted from a backlight. Gate driving means for sequentially and selectively outputting the gate line signals to the display element, and display data corresponding to one of the plurality of colors on the drain line. A drain driving means for supplying and driving a write data signal, and a reset signal prior to the display writing for writing the write data signal according to the display data in the sub-frame, at a faster clock than the display writing by the gate driving means. Reset control means for sequentially and selectively outputting the gate line signals, and in synchronization with this, driving and supplying a write data signal for maximizing or minimizing the transmittance of the liquid crystal display element to all the drain lines by the drain driving means. And is provided.

With such a structure, the reset operation is performed without the need for the reset operation transistor, thereby improving the aperture ratio of each pixel and wiring on the liquid crystal display panel. It is possible to simplify.

According to a second aspect of the present invention, in the first aspect of the invention, the reset control means has a maximum transmittance when the liquid crystal display element is a normally black type by the drain driving means at the time of resetting. In the case of a normally white system, the write data signal that becomes the above is supplied and driven to all the drain lines.

According to this structure, in addition to the operation of the invention described in claim 1, resetting is performed in a state where the maximum voltage corresponding to the write data signal is applied to all pixels of the liquid crystal display element at the time of resetting. Therefore, the responsiveness and stability during subsequent display writing can be further improved.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which the present invention is applied to a field-sequential liquid crystal display device will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration. In the figure, the liquid crystal display elements include TFTs 21a, 21a ,.
Is used as an active element (pixel driver) for the pixel portion 21 using the active matrix type.
The plurality of gate lines G1 to Gn connected to the gate terminals of T21a, 21a, ...
, and a plurality of drain lines D1 connected to the drain terminals of the TFTs 21a, 21a ,.
Dm is provided with a drain driver 23 which supplies a write data signal corresponding to display data in synchronization with the gate signal.

At each pixel position of the pixel portion 21, the TFT 21 connected to the gate line and the drain line is connected.
The source terminal of a is connected to both ends of the liquid crystal capacitance CLC and the auxiliary capacitance CS formed between the pixel electrodes of the liquid crystal, and the other end of the liquid crystal capacitance CLC is connected to the common electrode COM with another pixel to the auxiliary capacitance CS. The other end is connected to the auxiliary capacitance electrode CS, respectively.

However, the gate driver 22 has a shift clock switching circuit 31 as shown in FIG. The shift clock switching circuit 31 is based on a signal from a display controller (not shown) that controls the control operation of the liquid crystal display device. The switching signal from the switching circuit 32 is input directly to the AND circuit 33 and inverted to the AND circuit 34 via the inverter 35.

The reference clock M of this liquid crystal display element
clk is input to the first frequency dividing circuit (Gpck1) 36 and the second frequency dividing circuit (Gpck2) 37.

The first frequency dividing circuit 36 frequency-divides the reference clock Mclk and sends a sufficiently fast shift clock (Gpck1) of, for example, 1.6 [μS] period at the time of reset to the AND circuit 33. To do.

On the other hand, the second frequency dividing circuit 37 divides the reference clock Mclk and shifts the shift clock (Gpck2) of 8.0 [μS] cycle corresponding to the number of gate lines at the time of display writing. It is sent to the circuit 34.

Therefore, the output of the AND circuit 33 or 34 is passed through the OR circuit 38 to the gate shift clock Gpc.
is output to the gate driver 22 as k, and the gate signal G1 is output based on the gate shift clock Gpck.
~ Gn will be output.

Further, the drain driver 23 outputs the write data signal corresponding to the display data as described above to the drain lines D1 to D during the display writing in the sub-frame.
In the reset operation prior to the display writing, the write data signal that provides the maximum or minimum transmittance in each pixel of the pixel portion 21 is supplied instead of the halftone.

This corresponds to the write data signal at each pixel at the time of reset so that, for example, "black" is displayed when the pixel portion 21 is a normally white system and "white" is displayed when the normally black system is used. The maximum voltage is applied and reset.

Next, the operation of the above embodiment will be described.

FIG. 3 exemplifies the signal waveforms in the circuit configuration of FIG. 1, and here it is assumed that the number of gate lines n is “160” and the gate lines G1 to G160 are sequentially scanned and driven.

Further, the drain latch signal shown in FIG. 3A is generated inside the drain driver 23, and the gate shift clock Gpck of FIG. 3B also shown in FIG.
3 (4) gate start signal, and FIG. 3 (5)-
It is assumed that all of the gate signals G1 to G160 in (8) are generated inside the gate driver 22.

As shown in FIG. 3 (11), in the field sequential type liquid crystal display device according to the present invention,
4 "Reset (for all pixels)", "Write (for display data)", "Hold (for display data)" and "Lit back light (BL) while holding display data" for each subframe The two states will be executed repeatedly.

In the first "reset" state, FIG.
In synchronization with the drain latch signal shown in (1) and the gate start signal shown in FIG. 3 (4), the gate shift clock Gpck shown in FIG. 3 (2) is output by 160 times the number of gate lines.

At this time, the switching circuit 32 shown in FIG.
Is at the "H" level, and therefore the AND circuit 33 side is in the open state and the AND circuit 34 side is in the closed state, so that a faster gate shift clock Gpck having a period of 1.6 [μS] is output.

As a result, as shown in FIGS. 3 (5) to 3 (8), all the gate lines G1 to G160 are sequentially scanned and driven in a reset state in a shorter time. As shown in 3), as write data,
A signal (indicated as “1 (or 0)” here) such that the maximum voltage is applied to the pixel electrodes is applied to all the drain lines D1 to Dm, not the halftone.

Therefore, as a result, all the pixels of the pixel portion 21 are "black" if the pixel portion 21 is a normally white type.
In the normally black mode, it becomes "white", and it will be reset when the maximum voltage is applied between the pixel electrodes, but since the backlight is not lit at this time, the actual display contents Does not affect

In the subsequent "writing" state, FIG.
3 (5) in synchronization with the gate start signal shown in (4) and the gate shift clock Gpck shown in FIG. 3 (2).
To (8) all the gate lines G1 to G160
Are sequentially scanned and driven, and TF for display is provided for each gate line.
T21a, 21a, ... Are turned on, and the display data shown in FIG. 3C is written.

At this time, the switching circuit 32 shown in FIG.
Is set to the “L” level, and therefore the AND circuit 34 side is in the open state and the AND circuit 33 side is in the closed state, and the gate shift clock Gpck of 8.0 [μS] cycle suitable for display writing is sequentially gated. The line is scan driven.

Then, "holding" is started from the time when the scanning drive of the last gate line G160 and the writing of the display data are completed.
In this “holding” state, the LED (light emitting diode) that constitutes the backlight provided on the back side of the pixel portion 11 is driven to light up as shown in FIG. 3 (9) in this “holding” state. Further, the state is changed to the “lighting” state, and the held display contents are transparently displayed.

The above operation is repeatedly executed in units of subframes.

As described above, the resetting of the pixel portion 21 and the writing of the display data are surely executed while the display TFT 21a is provided for each pixel of the pixel portion 21 without the need for the resetting TFT. It is possible to improve the aperture ratio of each pixel and to avoid complication of the wiring layout on the liquid crystal display element panel including the pixel portion 21 and increase of the wiring capacitance. It is possible to eliminate a factor such as a short circuit which lowers the yield of device manufacturing, which contributes to a large reduction in manufacturing cost.

In addition to this, as the gate driver 22 and the drain driver 23 themselves of the pixel portion 21, the conventional general structure is used as it is, and a relatively small-sized additional circuit such as the shift clock switching circuit 31 described above is used. It can be realized only by the configuration.

Further, according to this embodiment, as shown in FIG.
As in the conventional driving method shown in Fig. 3, without selecting all the gate lines at the same time and applying the reset signal, all the gate lines are sequentially selected by the high-side clock signal at different timings. Since the gate driver 22 does not operate to supply a large number of gate signals at the same time, the gate driver 22
The load on the gate driver 22 is reduced, and the gate driver 22 can be configured by a general integrated circuit.

In the above embodiment, it is assumed that the display data written in each pixel at the time of reset is a signal that causes the maximum potential difference between the pixel electrodes. Specifically, the pixel portion 21 is normally white. “Black” data is written in the case of the method, and “white” data is written in the case of the normally black method.

This is because the responsiveness and stability of the liquid crystal material in the actual display data writing period following the reset period is taken into consideration depending on the characteristics of the liquid crystal display element. If this is not the case, a signal that does not cause a potential difference at all between the pixel electrodes of each pixel portion may be given at the time of reset in view of power consumption.

In addition, the present invention is not limited to the above-described embodiment, and various modifications can be carried out without departing from the scope of the invention.

Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, at least one of the problems described in the section of the problem to be solved by the invention can be solved, and it is described in the section of the effect of the invention. When at least one of the effects described above is obtained, a configuration in which this constituent element is deleted can be extracted as an invention.

[0050]

According to the first aspect of the present invention, the reset operation is performed while the transistor for the reset operation is unnecessary, so that the aperture ratio of each pixel is improved and the liquid crystal display panel is improved. It is possible to simplify the wiring in.

According to the second aspect of the invention, in addition to the effect of the first aspect of the invention, a state in which the maximum voltage corresponding to the write data signal is applied to all the pixels of the liquid crystal display element at the time of resetting Since it is reset by, the responsiveness and stability at the time of subsequent display writing can be further improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a shift clock switching circuit provided in the gate driver of FIG.

FIG. 3 is a timing chart showing drive waveforms of each signal according to the same embodiment.

FIG. 4 is a diagram showing a circuit configuration of a general field-sequential liquid crystal display device.

5 is a timing chart showing drive waveforms of each signal in FIG.

[Explanation of symbols]

11 ... Pixel part 11a ... (for display) TFT 11b ... (for reset) TFT 12 ... Gate driver 13 ... Drain driver 21 ... Pixel part 21a ... (for display) TFT 22 ... Gate driver 23 ... Drain driver 31 ... Shift clock switching circuit 32 ... Timing signal generation circuit (TG) 33, 34 ... AND circuit 35 ... Inverter 36 ... First frequency dividing circuit 37 ... Second frequency divider circuit 38 ... OR circuit CLC ... Liquid crystal capacity CS: auxiliary capacity

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 624 G09G 3/20 624B 641 641E 3/34 3/34 F term (reference) 2H093 NA16 NA65 NC09 NC11 NC15 NC16 NC29 NC34 NC43 ND04 ND17 5C006 AA14 AC21 AC22 AC24 AC25 BB16 BC03 BC06 BC11 BC16 BF31 FA42 FA43 FA47 5C080 AA10 BB05 DD22 FF11 JJ02 JJ03 JJ04

Claims (2)

[Claims] 1. A liquid crystal element in which a liquid crystal is sandwiched between a pair of substrates each having electrodes formed on opposing inner surfaces, and arranged in a matrix in the row and column directions on the inner surface of one of the pair of substrates. A plurality of pixel electrodes provided by
A plurality of thin film transistors arranged one by one corresponding to the plurality of pixel electrodes, each source electrode being connected to the corresponding pixel electrode, and being wired corresponding to each pixel electrode row, the gate of the thin film transistor A plurality of gate lines connected to the electrodes, a plurality of drain lines connected to the respective pixel electrode columns and connected to the drain electrodes of the thin film transistors,
And a liquid crystal display element that is provided on the inner surface of the other substrate of the pair of substrates and that has a counter electrode that faces the plurality of pixel electrodes, and that controls the transmission of light to display an image, and the liquid crystal display. A backlight disposed behind the element and sequentially emitting light of a plurality of colors toward the liquid crystal display element at a predetermined cycle, and the backlight emits one frame for displaying one color image. Write display data corresponding to one of the plurality of colors to the liquid crystal display element for each of a plurality of sub-frames divided by the number of light colors to In a liquid crystal display device for displaying one color image by combining the display of a plurality of colors for each of the plurality of sub-frames by causing the emission of light of a corresponding color, the gate line to the liquid crystal display element is provided. Gate drive means for sequentially and selectively outputting a color signal and one of the plurality of colors for the drain line.
Drain driving means for supplying and driving a writing data signal corresponding to display data corresponding to one color, and the gate driving means for resetting prior to display writing for writing a writing data signal corresponding to the display data in the subframe By the above, the gate line signals are sequentially and selectively output at a faster clock than the time of writing the display,
In synchronism with this, there is provided a liquid crystal display device comprising: reset control means for supplying and driving a write data signal for maximizing or minimizing the transmittance of the liquid crystal display element to all the drain lines by the drain driving means. . 2. The reset control means outputs a write data signal having a maximum transmittance when the liquid crystal display element is a normally black type by the drain driving means at the time of resetting, and a writing data signal when the liquid crystal display element is a normally white type. 2. The liquid crystal display device according to claim 1, wherein a write data signal having a minimum transmittance is supplied to and driven by all the drain lines.