JP2001209025A - Projection type display and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal light valve enabling high-speed video signal writing excellent in light stability by using a semiconductor substrate, and to provide a projection type display and liquid crystal display device which can display a high-quality image having high definition with a liquid crystal panel. SOLUTION: The liquid crystal display device has a liquid crystal display panel which has a transparent substrate, the semiconductor substrate, a switching element having a liquid crystal layer held between these substrates and disposed on the semiconductor substrate, a plurality of metallic layers divided by a plurality of slits and disposed on the switching element, and a semiconductor area disposed on the semiconductor substrate and corresponding to the slit of the metallic layer nearest to the semiconductor substrate among a plurality of metallic layers, a light source which supplies light to the liquid crystal display panel, and an optical system which expands and projects the light from the liquid crystal display panel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display which controls the intensity of light with the amplitude of a voltage, and more particularly to a liquid crystal light valve suitable for a projection type display and a projection type display using the same.

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display in which light is controlled by laminating a switching element and a liquid crystal, a MOS (Metal Oxide Semiconductor) formed on a single crystal silicon substrate as a switching element.
Liquid crystal displays using transistors are USP 3,862,3
60 and IE80 of IEICE Technical Report (1980)
-81.

When light is irradiated on a MOS transistor,
PN forming source and drain of MOS transistor
A photocurrent is generated at the junction. This photocurrent changes a video signal written to a liquid crystal pixel of the display unit, and a predetermined image to be displayed cannot be displayed. Therefore, in a liquid crystal display using MOS transistors formed on a single crystal silicon substrate, it is necessary to reduce the photocurrent so as not to affect the display screen. Each of the above-mentioned conventional displays is a method of directly viewing an image controlled by a switching element, and is usually used indoors. For this reason, it was sufficient to prevent the illuminance on the display panel surface from being affected by light of tens of thousands lux.

In order to reduce this photocurrent, the technical report of the Institute of Electronics and Communication Engineers states that the source region of a MOS transistor is arranged as far as possible from the light incident region.
A method has been adopted in which a silicon substrate surface on which an S transistor is formed is covered with two wiring layers, a stopper diffusion layer is provided, and generated carriers are recombined.

[0005] The display size of the display is:
Since the size is as small as about 2 inches due to the limitation of the silicon wafer, the number of pixels of such a display is about 40,000 from the viewpoint of the display size and the recognizable resolution.

[0006]

As described above, a liquid crystal display using a MOS transistor formed on a single crystal silicon substrate has been limited to a direct view type.

On the other hand, in a projection display, a panel in which switching elements and liquid crystal are laminated is called a liquid crystal light valve, and an image controlled by the light valve is enlarged and projected on a screen. For this reason, the light irradiated to the light valve becomes stronger as the screen is enlarged, and the brightness reaches several million lux. Further, since the pixels controlled by the light valve are enlarged and the image becomes coarse, the number of pixels of the light valve is required to be 300,000 or more.

As described above, in the projection type display, when a liquid crystal light valve using a transistor formed on a semiconductor substrate such as silicon is used, the light resistance of the liquid crystal light valve is increased, and the number of pixels is increased to increase the number of pixels. Writing a video signal at high speed is required.

The present invention has been made in view of such a situation, and an object of the present invention is to provide a liquid crystal light valve which uses a semiconductor substrate such as silicon and is excellent in light resistance without being affected by strong irradiation light. To provide a liquid crystal light valve capable of writing a video signal at a high speed, and to provide a projection type display that displays a high-definition, bright, high-quality image using such a liquid crystal light valve. It is in.

[0010]

In order to achieve the above object, according to the present invention, a projection type liquid crystal display is constituted as follows.

A semiconductor substrate having a plurality of switching element regions formed in a matrix on one surface; and a semiconductor substrate formed on one surface of the semiconductor substrate with an insulating layer interposed therebetween and divided into a plurality of first slits. A first metal layer, a second metal layer formed on the first metal layer via an insulating layer, and divided into a plurality of pieces by a second slit, and a counter electrode on one surface. The counter electrode comprises a counter substrate facing the second metal layer with a gap therebetween, and liquid crystal filled in a gap between the counter electrode and the second metal layer. A liquid crystal light valve provided with a semiconductor region connected to a reference potential at a position where light incident through the slit and the second slit reaches the semiconductor substrate; and a light source for supplying light irradiated to the liquid crystal light valve from the counter substrate side. From the liquid crystal light valve A structure in which an optical system for enlarging and projecting an Shako.

A capacitor element region is provided on one surface of the semiconductor substrate corresponding to each of the switching element regions, and a substrate power supply line for supplying a substrate potential to the substrate potential region of the switching element region and a metal layer is provided. Formed.

Further, a video signal line for supplying a video signal to the video signal input terminal portion in the switching element region is formed of one of metal layers, and the substrate power supply line and the video signal line are arranged in parallel with each other.

Since the metal layer reflects the irradiated light, the light incident on one surface of the semiconductor substrate is weakened, and the photocurrent flowing in the switching element region can be greatly reduced.

The photocurrent generated by irradiating the semiconductor region connected to the reference potential with light flows through the wiring portion on the reference potential side and is consumed, and does not affect the switching element region.

By forming the substrate power supply line and the video signal line in a metal layer and arranging both wirings in parallel with each other, the impedance of these wirings is reduced and the writing of the video signal to each pixel can be performed at high speed.

Since the switching elements of the liquid crystal light valve are not affected by the irradiation light and the number of pixels can be increased by increasing the video signal writing speed, a projection type display for displaying a high-definition, bright and high-quality image is provided. Can be provided.

[0018]

FIG. 1 shows a circuit configuration of a liquid crystal light valve used in a projection type display. This light valve includes a pixel circuit 1, a sample circuit 2, a horizontal scanning circuit 3, a vertical scanning circuit 4, and an AND gate 5. The pixel circuit 1 includes a plurality of first signal lines (scanning signal lines) 11, a plurality of second signal lines (video signal lines) 12 intersecting with the first signal lines, and a third signal line provided next to the second signal line. It comprises a signal line (substrate feed line) 13 and a MOS transistor 1a, a storage capacitor 1b, and a liquid crystal capacitor 1c provided at the intersection of the first signal line and the second and third signal lines. One set of MO
The S transistor 1a, the storage capacitor 1b, and the liquid crystal capacitor 1c are 1
One pixel is formed, and M pixels in the horizontal direction and N pixels in the vertical direction are arranged in a matrix as a whole. The number M × N of the pixel arrangement is 640 × 480 as an example.
The scanning signals Vg1 to VgN are applied to the gate electrode of the MOS transistor 1a via the first signal line 11 and the luminance signals Vd1 to VgV to the drain electrode via the second signal line 12.
dM, and the source electrode is connected to one electrode of the storage capacitor 1b and one electrode (reflection electrode) of the liquid crystal capacitor 1c. Further, the other electrode of the storage capacitor 1b is connected via a third signal line 13 to a voltage VSS for supplying a substrate voltage. The liquid crystal capacitance 1c is an equivalent capacitance of a liquid crystal element formed by filling liquid crystal between a substrate on which the pixel circuit 1 is formed and an opposing substrate provided opposite thereto.

The horizontal scanning circuit 3 receives a clock signal CLK and a start signal STA and receives M-phase multiphase signals PH1 to PH1.
Output PHM. The sample circuit 2 is constituted by a MOS switch, and the gate electrode of the MOS switch is connected to the output signal PH1
To the PHM and the drain electrode of the MOS switch are connected to the video signal VI1 or VI2 having different polarities, and output the luminance signals Vd1 to VdM to the source electrode of the MOS switch.

The vertical scanning circuit 4 receives a clock signal CKV and a start signal FST and receives N-phase multiphase signals PV1 to PV1.
It outputs PVN. The AND gate 5 outputs the multi-phase signal P
V1 to PVN and the control signal CNT are input, and the scanning signal Vg
1 to VgN are output.

The horizontal scanning circuit 3 and the sample circuit 2 are formed by a light shielding layer 6, and the vertical scanning circuit 4 and the AND gate 5 are formed by a light shielding layer 7.
And the light-shielding layers 6 and 7 are applied with the voltage of the counter electrode.
Connected to COM.

The operation of the liquid crystal light valve configured as described above will be described with reference to a timing chart shown in FIG. The start signal FST of the vertical scanning circuit 4 indicates the head of the frame of the video to be displayed, and the clock signal CKV indicates the switching timing of the scanning line. The vertical scanning circuit 7 captures the start signal FST at the timing of the rise of the clock signal CKV, and outputs the multi-phase signal PV1.
~ PVN is output.

The AND gate 5 outputs the multi-phase signals PV1 to PV
N and the control signal CNT are inputted, and the scanning signal V of the pixel circuit is inputted.
g1 to VgN are output. Here, at the time of the sequential scanning in which the scanning is performed line by line, by setting CNT to “H”, the scanning signals Vg1 to VgN are equal to the multi-phase signals PV1 to PVN,
Pixel circuits 1 arranged in a matrix are sequentially selected in the vertical direction. On the other hand, in the case of two-line simultaneous scanning for scanning every two lines, a double clock of two consecutive pulses is used as the clock signal CKV. The control signal CNT is set to "L" only during this double clock period to cut off the multi-phase signal. This is because the combination of the multi-phase signals differs only momentarily during the double clock period, and at this time, the voltage written to the storage capacitor fluctuates, so that the fluctuation is prevented by the control signal CNT.

The video signals VI1 and VI2 are signals that change with reference to the voltage COM of the common electrode, and have polarities opposite to each other and inverted for each frame.

The start signal STA of the horizontal scanning circuit 3 indicates the head of the scanning line. Like the vertical scanning circuit 4, the horizontal scanning circuit 3 captures the start signal STA at the rising timing of the clock signal CLK, and outputs the multi-phase signal PH.
1 to PHM are output.

The sample circuit 2 outputs the video signals VI1, VI
2 are sequentially sampled at the timing of the multi-phase signals PH1 to PHM, and the luminance signals Vd1 to VdM are output.

The luminance signals Vd1 to VdM are input to the pixel circuits 1 arranged in a matrix for each column. At this time, since only the MOS transistors of the pixel circuits 1 selected by the scanning signals Vg1 to VgN are on, the luminance signals Vd1 to VdM are written and held in the storage capacitors 1b of the pixel circuits in the selected row. Since the voltage held in the storage capacitor 1b is applied to the liquid crystal, the liquid crystal light valve can display an image according to the image signals VI1 and VI2.

Here, the charging current of the storage capacitor 1b is supplied from the video signal VI1 through the MOS switch of the sample circuit, the second signal line 12, the MOS transistor 1a of the pixel circuit, the storage capacitor 1b, and the third signal line 13. Board power supply terminal VSS
Flows to To shorten the charging time at this time, it is effective to reduce the series resistance, inductance, and parasitic capacitance of the wiring in the charging path.

The charging speed of the storage capacitor 1b will be described in detail. The voltage held in the storage capacitor 1b changes due to crosstalk noise caused by the scanning signal and the luminance signal, off-state current of the MOS transistor, leak current due to the resistance of the liquid crystal, and the like. For this reason, when the hold time becomes long, flicker occurs in the displayed image. Usually, in order to prevent this flicker, the cycle of the start signal FST is 1/60
Set to seconds. At this time, the sampling time Ts of the sample circuit 2 is approximately represented by the following equation, where M is the number of pixels in the horizontal direction and N is the number of pixels in the vertical direction.

[0030]

Ts = 1 / (M × N × 60) (Equation 1) From this equation, the sampling time is about 400 ns for the conventional 40,000 pixels, whereas the sampling time is required for the projection display. It can be seen that 300,000 pixels are reduced to about 50 ns. In a conventional liquid crystal display using MOS transistors, the third signal line 13 is not specially provided, and has a structure in which a silicon substrate or a diffusion layer is used as a current path. However, the sheet resistance of this portion becomes several hundred Ω even in the case of diffusion resistance, and when the pitch of the pixel circuits of the liquid crystal light valve for a projection type display is set to about 60 μm, the resistance of the substrate power supply line becomes several hundred kΩ or more. For this reason, high-speed writing was impossible with the conventional substrate power supply line. On the other hand, in the present invention, the resistance of the substrate power supply line is reduced to several hundred ohms by using a metal wiring layer for the substrate power supply line (third signal line), as described later.

Next, a scanning circuit constituting the liquid crystal light valve and its operation will be described. FIG. 3 shows the configuration of the horizontal and vertical scanning circuits of the liquid crystal light valve. This circuit is a D-type flip-flop FF,
It is composed of an inverter INV and a level conversion circuit LS. These circuits have M stages of horizontal scanning circuits and N stages of vertical scanning circuits, and constitute a shift register by connecting FFs in series. The level conversion circuit LS includes two PMOS transistors (MP) whose sources are connected to VDD.
1, MP2) and two NMOs with sources connected to VSS
The output of the flip-flop FF is connected to the gate of MP1 and is connected to the gate of MP2 in the opposite phase by the inverter INV, which is composed of S transistors (MN1, MN2). The gates of MN1 and MN2 are connected to each other and to the drains of MN1 and MP1.
Further, the drains of MN2 and MP2 are connected to each other, and this point is used as the output PH (PV) of the scanning circuit. With this configuration, when the output of the FF is “H” (VDD), MP
1 and MN2 are turned off, MP2 is turned on, and the output PH (P
V) becomes VDD. On the other hand, the output of the FF is “L” (GN
In the case of D), MP1 and MN2 are turned on, MP2 is turned off, and the output PH (PV) becomes VSS. In this way, the level conversion circuit LS converts the 0-VDD signal to the VSS-VDD signal.
Is converted to a signal. Here, the level conversion circuit LS is composed of a high voltage CMOS transistor that operates with a power supply of VDD (+5 V) -VSS (−15 V), and the FF and INV are low voltage CMOS transistors that operate with a power supply of VDD (+5 V) -0.
It is composed of transistors.

Next, the device structure of the liquid crystal light valve of the present invention will be described in detail.

FIG. 4 is a sectional view of the first embodiment of the present invention. The liquid crystal light valve has, on one surface of a single crystal silicon plate, a pixel circuit 1 composed of a MOS transistor 1a composed of an enhancement type NMOS transistor, a storage capacitor 1b composed of a MOS capacitor, and a reflective electrode. The first substrate 100 and an opposing substrate 301 made of a transparent material such as glass are provided on one surface with ITO.
A liquid crystal 200 is filled between a second substrate 300 on which a counter electrode 302 made of a transparent conductive material such as (Indium-tin-oxide) is formed. The sample circuit 2, the horizontal scanning circuit 3, the vertical scanning circuit 4, and the AND gate 5 shown in FIG. 1 are also formed on the surface of the first substrate, like the pixel circuit 1.

The first substrate 100 has an MO on one surface side.
A single-crystal silicon plate 111 in which a source region, a drain region constituting the S transistor 1a and a region to be one electrode of the storage capacitor 1b are formed, and a polysilicon layer 120 selectively formed on the single-crystal silicon plate 111; A first insulating layer 130 formed on the polysilicon layer 120;
A first metal layer 140 formed on the first insulating layer 130 and penetrating through the first insulating layer 130 to contact the surface of the single crystal silicon plate 111 and the polysilicon layer 120;
A second insulating layer 150 formed on the second metal layer, and a second metal layer 160 formed on the second insulating layer. The first metal layer 140 and the second metal layer 160 are formed of, for example, aluminum.

The single-crystal silicon plate 111 has a pair of surfaces, an n-type semiconductor layer 111 adjacent to one surface, a p-type semiconductor layer 112 adjacent to the other surface and the n-type semiconductor layer 111, an n ⁺ region 113 of the plurality of pairs which are formed to extend in the p-type semiconductor layer 112 from the other surface, n ⁺
A plurality of n formed so as to extend into p-type semiconductor layer 112 from the other surface at a position distant from region 113
And an area 114. Multiple pairs of n ⁺ region 1
13 is a source region of the MOS transistor 1a,
As a drain region, as shown in FIG. 5, a pair is provided for each unit pixel (indicated by a dashed line). Further, the plurality of n regions 114 serve as one electrode of the storage capacitor 1b, and are provided one by one in each unit pixel.

The polysilicon layer 120 is selectively formed on one surface of the single crystal silicon plate 111 via the silicon oxide layer 115. Specifically, on the p-type semiconductor layer 112 exposed between the pair of n ⁺
4 and on the p-type semiconductor layer 112 in the vicinity thereof,
A portion 123 constituting a part of the gate electrode of the OS transistor 1a or the first signal line (scanning signal line);
and a portion 124 to be the other electrode b. The storage capacitor 1b is composed of an n region 114, a polysilicon layer 124, and a silicon oxide layer 115 interposed therebetween.

The first metal layer 140 formed on the first insulating layer 130 is divided into a plurality of parts by slits 144, a wiring 141 connecting the MOS transistor 1a and the storage capacitor 1b, and a second signal line. 142, third signal line 1
43. The wiring 141 is the first insulating layer 130
A contact hole 131 provided in the through pair of n ⁺
In one of the regions 113 and the polysilicon layer 124, the second signal line 142 penetrates through the contact hole 131 provided in the first insulating layer 130 and in the other of the pair of n ⁺ regions 113,
I'm in contact with each. Also, the second signal line 14
2 is a contact hole 13 provided in the first insulating layer 130
1 is also in contact with the p-type semiconductor layer 112.

The second metal layer 160 serves as a reflective electrode, has substantially the same shape as each unit pixel, and forms a plurality of pixel electrodes 161 separated by slits 162 for each pixel. Although not shown in the figure, the pixel electrode 161
Are in contact with the wiring 141 via the through holes 151 provided in the second insulating layer 150 (see FIG. 7). Therefore, one (source region) of the n ⁺ region 113 of the MOS transistor is connected to the pixel electrode 161 via the contact hole 131 and the through hole 151 via the wiring 141 (see FIG. 7), and the voltage applied to the pixel electrode 161 is set to M.
Switching is performed by the OS transistor 1a.

Here, the wiring 141 and the pixel electrode 161 are
In order to shield the MOS transistor 1a from light radiated to the liquid crystal light valve from the side of the counter substrate 300 and to reduce unevenness on the surface of the pixel electrode, the layout is made such that the space between the patterns is minimized and the area is as large as possible. are doing. That is, the area of the slit between the first metal layer 140 and the pixel electrode 161 is made as small as possible, and the amount of light incident from these slits is reduced to improve the light blocking effect.

Further, by reducing the width of the slit 144 provided in the first metal layer 140, the unevenness on the surface of the first insulating layer formed by coating or the like on the slit 144, and the width of the 2, the unevenness on the surface of the metal layer is reduced, and the unevenness on the surface of the pixel electrode 161 serving as the reflective electrode is reduced. Accordingly, the light emitted from the light source to the liquid crystal light valve is not irregularly reflected by the pixel electrode 161 and is effectively used and projected on the screen, so that a bright image can be formed.

The figure shows an area of one pixel. In this embodiment, the size of each pixel is set to 64 μm in both the horizontal and vertical directions using a high breakdown voltage process of 2 μm.

FIGS. 5 and 6 show the planar structure of various patterns formed on the first substrate 100. FIG. FIG. 5 shows a planar pattern of a diffusion layer such as a diffusion layer 113 of a MOS transistor and a diffusion layer 114 of a storage capacitor formed on the surface of a silicon substrate 110, and a polysilicon layer 120 formed thereon. FIG. 6 shows a plane pattern of a first metal layer 140 and a second metal layer 160 formed on the pattern of FIG. 5 with a first insulating layer 130 and a second insulating layer 150 interposed therebetween. 4 shows a layout pattern of contact holes (CONT) 131 and through holes (TC) 151 formed in a first insulating layer 130 and a second insulating layer 150 for electrically connecting layers. The contact hole 131 connects the diffusion layer or the polysilicon layer to the first metal layer, and the through hole 151 connects the first metal layer and the second metal layer. FIG. 4 described above shows a cross section along the line IV-IV shown in FIG. The wiring 141, the second signal line 142, and the third signal line 143 formed of the first metal layer
4 and a plurality of pixel electrodes (reflection electrodes) 161 formed of the second metal layer are separated from each other by slits 162 formed in the same layer.

A first signal line is formed by forming a polysilicon layer 123 of a MOS transistor from a first metal layer formed of a first metal layer.
And are connected to each other at the metal layer portion 145 of the signal line. The connection between the two is made through a contact hole 131 formed in the first insulating film.

The liquid crystal light valve of the present invention comprises a counter substrate 3
It is a reflection type in which strong light emitted from the 00 side is reflected by the pixel electrode 161, and the intensity of the reflected light is controlled in the state of the liquid crystal 200. For example, when a polymer-dispersed liquid crystal is used for the liquid crystal 200, the voltage of the pixel electrode 161 causes
The liquid crystal 200 changes from a scattering state to a transparent state. Therefore, the reflectance of each pixel is high when the liquid crystal 200 is in the transparent state and low when the liquid crystal 200 is in the scattering state. This light valve is
An image is displayed by controlling the state of the liquid crystal by the voltage of the pixel electrode 161.

Next, a description will be given of how light is shielded from irradiation light. When light is applied to a pn junction of a semiconductor, a photocurrent is generated. This photocurrent is a problem in the source electrode portion of the diffusion layer 113 of the MOS transistor. When a photocurrent flows through the source electrode portion, the voltage written to the storage capacitor 1b changes, and a predetermined display image cannot be obtained. Therefore, the light to the diffusion layer 113 of the MOS transistor 1a is shielded by the first metal layer 140 and the second metal layer 160. In particular, as shown in FIGS.
Light passing through the first inter-electrode slit 162 takes the wiring width of the third signal line 143 sufficiently larger than the inter-electrode space,
By arranging this immediately below the space between the electrodes, light is shielded. FIG. 7 is a sectional view taken along the line VII-VII in FIGS. 5 and 6,
This is a view in which the source electrode portion of the MOS transistor 1a is viewed in the vertical direction. Interelectrode slit 162 of pixel electrode 161
Passing through the wiring 141 corresponding to the pixel electrode 161
Is arranged so as to protrude below the slit 162 to shield light.

FIG. 8 is a sectional view taken along line VIII-VIII in FIGS. 5 and 6, showing a slit portion of the first metal layer 140.
In this region, the light is not shielded by the first metal layer 140 and the second metal layer 160, and passes through the slit 144 formed in the first metal layer and the slit 162 formed in the second metal layer. In this case, the surface of the silicon substrate 110 is directly irradiated with light. The direct light passes through slits between the patterns of the wiring 141, the second signal line 142, and the third signal line 143, and irradiates the n ⁺ layer 116 thereunder. Diffusion layer 114 of storage capacitor and third signal line 1
The connection with 43 is made via the n ⁺ layer 116 to secure an ohmic contact. The irradiation light is the n ⁺ layer 116
At the pn junction of the p-type well layer 112. As described above, the p-type well layer 112 and the n ⁺
Since both the layers 116 are connected to the third signal line (substrate feed line) 143 and are supplied with the lowest voltage (VSS),
The photocurrent generated at the pn junction flows through the third signal line through the p-type well layer and is consumed. As a result, the photocurrent is
Since the current does not flow to the diffusion layer 113 of the MOS transistor, particularly to the source region, the voltage written to the storage capacitor 1b can be stably held, and the image quality does not deteriorate even if the light is irradiated as in a projection display.

The photocurrent can also be reduced by using a light-absorbing insulating layer for at least one of the first insulating layer 130 and the second insulating layer 150. For this light-absorbing insulating layer, colored polyimide or the like can be used. further,
Photocurrent can also be obtained by providing a layer made of a black material on the front surface or back surface of the aluminum layer serving as the first metal layer or on the back surface of the aluminum layer serving as the second metal layer, and patterning each wiring layer in the same shape. Can be reduced. For this black material, chromium oxide, tantalum oxide, or the like can be used. Next, the charging speed of the storage capacitor 1b will be described. As described above, the second signal line 142 is connected to the drain region of the diffusion layer 113 of the MOS transistor, and the third signal line 143 is connected to the diffusion layer 114 of the storage capacitor and the p-type well layer 112 via the contact holes 131, respectively. Connected. With such an element structure, a current path for charging the storage capacitor 1b is the second signal line 142 → the MOS transistor 1a → the storage capacitor 1b → the third signal line 143. Second
The signal line 142 and the third signal line 143 are arranged so as to be parallel to each other. Therefore, the currents flowing through the second signal line and the third signal line are opposite to each other, and the magnetic fields formed outside by the two wirings cancel each other, and the inductance of the wirings is reduced. Further, the wiring resistance is reduced by using the metal wiring layers for the second signal line and the third signal line.

With the above configuration, the impedance of the wiring portion during charging is reduced, and writing of the video signal to the storage capacitor can be performed at high speed. Next, FIGS.
Another embodiment of the liquid crystal light valve of the present invention will be described with reference to FIG. The difference from the embodiments shown in FIGS. 4 to 8 is that the metal layer has a three-layer structure, and another light-shielding layer is provided between the wiring 141 and the pixel electrode serving as the reflective electrode. However, the patterns of the diffusion layer and the polysilicon layer of the pixel circuit shown in FIG. 5 are the same as in the previous embodiment.

FIG. 9 is a sectional view of the liquid crystal light valve of this embodiment. In the present embodiment, the first metal layer 14 on which the second signal line 142, the third signal line 143, and the wiring 141 are formed is formed.
0, a second metal layer on which a light-shielding layer 163 and an intermediate electrode 164 are formed via a first insulating layer 150 is provided, and a pixel electrode (reflective electrode) is further provided thereon via a second insulating layer 170. 181 are provided. Light shielding layer 163 and intermediate electrode 16
4 is a slit 162, and pixel electrodes are connected to the slit 1
They are separated from each other at 82. The source region of the diffusion layer 113 of the MOS transistor is connected to the wiring 141 by the through hole 131, the wiring 141 is connected to the intermediate electrode 164 by the through hole 151, and the intermediate electrode 164 is connected to the pixel electrode 181 by the through hole 171. The voltage applied to the pixel electrode is switched by the MOS transistor 1a.

FIG. 10 shows the planar structure of each pattern in the first metal layer 140, the second metal layer 160, and the third metal layer 180. FIG. 9 is a sectional view taken along line IX-IX in FIG.

As can be seen from FIGS. 9 and 10, light incident from the inter-electrode slit 182 of the pixel electrode 181 formed by the uppermost third metal layer 180 is reflected by the second metal layer 160.
The light is completely shielded by the light-shielding layer 163 formed by the above. That is, when viewed from the counter substrate 300 side, the third metal layer 18
The slit 182 formed in the first substrate 300 and the slit 162 formed in the second metal layer 160 are shifted from each other without overlapping each other.
Light incident from the side is reflected by either the third metal layer or the second metal layer and does not reach the silicon substrate 110.

As described above, in this embodiment, light incident from the second substrate side is blocked by the second metal layer and the third metal layer provided on the first substrate. In order to prevent the incident light from reaching the silicon substrate, the slits formed in the first metal layer, the second metal layer, and the third metal layer are shifted so as not to overlap each other. It should just be arranged.

In the configuration shown in FIGS. 9 and 10, the first
Insulating layer 130, second insulating layer 150, third insulating layer 170
The photocurrent can also be reduced by using a light-absorbing insulating layer for at least one of the layers. In this light absorbing insulating layer,
A colored polyimide or the like can be used. Further, the first metal layer 140, the second metal layer 160, and the third metal layer 18
The photocurrent can also be reduced by providing a black material layer on at least one back surface or front surface of 0 and patterning it in the same shape as each metal layer. This black material contains chromium oxide,
Tantalum oxide or the like can be used.

Next, mounting of the liquid crystal light valve of the present invention will be described. 11 and 12 show an example of a planar structure and an example of a sectional structure of a liquid crystal light valve mounted on a ceramic substrate.

The first substrate 100 in which the pixel circuit, the horizontal scanning circuit, the vertical scanning circuit, etc. are formed on the surface of the above-mentioned single crystal silicon substrate is adhered to the ceramic substrate 500 with a conductive paste with the circuit portion facing upward. . A first substrate 100;
The liquid crystal 200 is interposed between the liquid crystal 200 and a second substrate 300 provided opposite thereto. The liquid crystal 200 is sealed by a seal member 510 provided on the periphery thereof, and is protected from external humidity and the like.

The signal terminals provided on the periphery of the first substrate are:
It is connected to the wiring pattern formed on the ceramic substrate by wire bonding. In addition, a conductive paste 530 is used to connect the counter electrode 302 provided on the surface of the second substrate 300 to the wiring pattern on the ceramic substrate. As shown in FIG. 11, the wire bonding position on the first substrate is the upper side and the left side of the same substrate, and the contact position of the second substrate surface with the counter electrode is the right side. By setting the wire bonding position to two sides or less, the distance between each substrate and the wire bonding portion can be reduced.

The flexible printed board 550 is made of solder 5
It is connected to the wiring pattern of the ceramic substrate 500 by 40 and supplies a control signal for the liquid crystal light valve.

FIG. 13 shows the configuration of a projection display to which the liquid crystal light valve of the present invention is applied. The projection type display comprises a light source 700, a first lens 710, a mirror 7
20, a second lens 730, a liquid crystal light valve 740,
It comprises a projection lens 750 and a screen 760. The light from the light source 700 is focused on the mirror 720 by the first lens 710. This light is converted into parallel light by the first lens 730 and applied to the liquid crystal light valve 740. In the liquid crystal light valve, the reflection state of the irradiated light is controlled by a voltage applied to each liquid crystal pixel, and the reflected light from the liquid crystal light valve is enlarged and projected on the screen 760 via the first lens 730 and the projection lens 750. To form an image.

Further, the light beam from the light source is decomposed into three light beams of three primary colors, and a liquid crystal light valve is provided for each light beam. The reflected light from the three liquid crystal light valves is again synthesized and enlarged and projected. Thus, a color projection display can be obtained. Decomposition of light into three primary colors,
The combination of the reflected lights from the three liquid crystal light valves can be performed simultaneously using, for example, a dichroic mirror.

Although the liquid crystal light valve using a single crystal silicon substrate and the projection type display using the same have been described above, the present invention relates to a substrate in which a semiconductor layer is formed on an insulating substrate instead of a single crystal silicon substrate. Needless to say, it is possible to use a compound semiconductor substrate.

According to the present invention, in a liquid crystal light valve using a semiconductor substrate made of silicon or the like on which active elements such as MOS transistors are formed and a projection type display using the same, the semiconductor surface of the pixel circuit portion is subjected to a signal by a metal wiring layer. Since light is shielded by a plurality of light-shielding layers such as lines and pixel electrodes, and light that cannot be shielded by a signal line or a pixel electrode by a metal wiring layer is arranged so as to irradiate a diffusion layer of a semiconductor substrate connected to a reference potential, The photocurrent flowing through the active element of the circuit section can be greatly reduced. Further, metal wiring is used for a signal line for supplying a video signal to each pixel and a substrate power supply line, and these are arranged in parallel with each other. Therefore, the impedance of the signal line can be reduced, and writing of a signal to a pixel can be performed at high speed.

[0062]

According to the present invention, it is possible to realize a projection type display and a liquid crystal display device with high brightness and high definition.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a liquid crystal light valve.

FIG. 2 is a timing chart showing the operation of the liquid crystal light valve.

FIG. 3 is a diagram showing a detailed circuit of a scanning circuit constituting the liquid crystal light valve.

FIG. 4 is a sectional view (a sectional view taken along line IV-IV in FIGS. 5 and 6) of the liquid crystal light valve according to the embodiment of the present invention;

FIG. 5 is a layout diagram of a diffusion layer and a polysilicon layer of a pixel circuit in one embodiment of the liquid crystal light valve of the present invention.

FIG. 6 is a layout diagram of a first metal layer and a second metal layer of a pixel circuit in one embodiment of the liquid crystal light valve of the present invention.

FIG. 7 is a sectional view taken along the line VII-VII of FIGS. 5 and 6;

FIG. 8 is a sectional view taken along the line VIII-VIII in FIGS. 5 and 6;

FIG. 9 is a sectional view (IX-IX sectional view of FIG. 10) of another embodiment of the liquid crystal light valve of the present invention.

FIG. 10 is a layout diagram of a first metal layer, a second metal layer, and a third metal layer of a pixel circuit in another embodiment of the liquid crystal light valve of the present invention.

FIG. 11 is a diagram showing a planar structure of a liquid crystal light valve mounted on a ceramic substrate.

FIG. 12 is a diagram showing a cross-sectional structure of a liquid crystal light valve mounted on a ceramic substrate.

FIG. 13 is a diagram showing a configuration of a projection display to which a liquid crystal light valve is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pixel circuit, 1a ... MOS transistor, 1b ... Storage capacity, 1c ... Liquid crystal capacity, 2 ... Sample circuit, 3 ... Horizontal scanning circuit, 4 ... Vertical scanning circuit, 5 ... AND gate, 6, 7
... light shielding layer, 100 ... first substrate, 110 ... silicon substrate, 120 ... polysilicon layer, 130 ... first insulating layer,
140 ... first metal layer, 150 ... second insulating layer, 160
... second metal layer, 170 ... third insulating layer, 180 ... third
Metal layer of 200, liquid crystal, 300: second substrate.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G09G 3/20 680 G09G 3/36 G02F 1/1335 530 3/36 1/136 500 (72) Inventor Hoshino Minoru 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Yuji Mori 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture, Hitachi Research Laboratory, Hitachi, Ltd. (72 ) Inventor Shinichi Komura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratory (72) Inventor Keiji Nagae 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Inside the laboratory (72) Inventor Tetsuya Nagata 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Yes Akira 7-1-1, Omika-cho, Hitachi City, Ibaraki Pref.Hitachi, Ltd.Hitachi Research Laboratories Co., Ltd. (72) Inventor Akio Hayasaka 3300 Hayano, Mobara-shi, Chiba Pref. Hitachi Process Computer Engineering Co., Ltd., 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture

Claims (9)

[Claims] 1. A semiconductor substrate having a plurality of switching element regions formed in a matrix on one surface, and a plurality of switching element regions formed on one surface of the semiconductor substrate with an insulating layer interposed therebetween. A first metal layer divided into a plurality of pieces, a second metal layer formed on the first metal layer via an insulating layer, and divided into a plurality of pieces by a second slit; A counter electrode, and the counter electrode side is the second
And a liquid crystal filled in a gap between the counter electrode and the second metal layer, and a first slit and a second slit from the counter substrate side. A liquid crystal light valve provided with a semiconductor region at a position where light incident through the slit reaches the semiconductor substrate; a light source for supplying light irradiated from the counter substrate side to the liquid crystal light valve; and reflection from the liquid crystal light valve. A projection display including an optical system for expanding and projecting light. 2. The projection type liquid crystal display according to claim 1, wherein a semiconductor region of a semiconductor substrate of said liquid crystal light valve is connected to a reference potential. 3. The projection type liquid crystal display according to claim 1, wherein a capacitor element region is provided on one surface of the semiconductor substrate in the liquid crystal light valve in correspondence with each of the switching element regions. A projection type liquid crystal display in which a substrate power supply line for supplying a substrate potential to the substrate potential region and the capacitor region is formed by any of the metal layers. 4. A projection type liquid crystal display according to claim 1, wherein a signal circuit area for supplying signals to said plurality of switching element areas is provided on one surface of said semiconductor substrate. Type display. 5. A switching element having a transparent substrate, a semiconductor substrate, and a liquid crystal layer sandwiched between these substrates, a switching element disposed on the semiconductor substrate, and a plurality of slits disposed on the switching element. A liquid crystal display panel comprising: a plurality of metal layers divided by: and, among the plurality of metal layers, a semiconductor region disposed on the semiconductor substrate corresponding to a slit of a metal layer closest to the semiconductor substrate; A liquid crystal display device comprising: a light source for supplying light to a liquid crystal display panel; and an optical system for enlarging and projecting the light from the liquid crystal display panel. 6. The liquid crystal display device according to claim 5, wherein the plurality of metal layers of the liquid crystal display panel are at least two layers. 7. The liquid crystal display device according to claim 5, wherein the semiconductor regions of the liquid crystal display panel are an N-type semiconductor region and a P-type semiconductor region. 8. The liquid crystal display device according to claim 5, wherein said semiconductor region of said liquid crystal display panel is connected to a reference potential. 9. The liquid crystal display device according to claim 8, wherein said semiconductor region of said liquid crystal display panel is connected to a reference potential via one of said plurality of metal layers.