JP2001204171A - Synchronous rectifier type converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply equipment (synchronous rectifier type converter) which can supply stable output voltage by suppressing the back flow (regeneration of power) which has been a problem of the conventional circuit when power supply panels are connected in parallel. SOLUTION: In the synchronous rectifier type converter using FETs, voltage elements whose voltage is higher than the output voltage are respectively connected to the gates of a FET Q2 for rectification and a FET Q3 for commutation, both of which are installed at the secondary side of a transformer, in series and a resistor R1 (R2) for biasing is connected between the gate and the source of each FET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous rectifier type converter, and more particularly to a synchronous rectifier type converter which prevents a malfunction of a synchronous rectifier circuit due to a reverse current flowing from another voltage source.

When operating with a power supply connected in parallel, an FET
A high-efficiency converter is realized by the synchronous rectification circuit method using a power supply.However, the power supply circuit using the synchronous rectification circuit of the power supply consists of a power regeneration circuit to the input circuit side of this power supply by the reverse current from another power supply Since this power supply can be broken, a countermeasure circuit is required.

[0003]

2. Description of the Related Art FIG. 8 shows an example of a conventional circuit of a synchronous rectification type converter. When the DC input voltage Ei is received and the switching transistor (FET) Q1 is on, the rectifying transistor (FE) is connected via the transformer T1 via the output side choke coil L1 and the smoothing capacitor C1.
T) The DC voltage smoothed by the closed circuit of Q2 is
L.

[0004] Switching transistor (FET) Q1
Is off, the energy stored in the coil L1 is transferred to the smoothing capacitor C1 and the output-side commutation transistor (FE).
T) Supply the smoothed DC voltage via Q3 to the load resistor RL.

In this case, the output voltage Eo is equal to the resistance R
The voltage is monitored by a voltage dividing circuit of R3 and R4, and is supplied to a controller 1 that controls the switching transistor Q1. The controller 1 controls the conduction time of the switching transistor Q1 so that the output voltage Eo becomes a constant value.

[0006]

In such a conventional circuit, when used in parallel with another DC power supply, the output voltage of the other power supply is applied to the output capacitor C1 of the main power supply, and is applied via the coil L1. As a result, the rectifying FET Q2 may be turned on, causing a reverse flow (regeneration of power) to the input circuit side via the transformer T1, and the power supply may be damaged.

The present invention has been made in view of such a problem, and a power supply device capable of suppressing a backflow (power regeneration) which has been a problem in a conventional circuit and supplying a stable output voltage. (Synchronous rectification type converter).

[0008]

(1) FIG. 1 is a principle circuit diagram of the present invention. 8 are denoted by the same reference numerals. In the figure, Ei is an input DC voltage, Q1 is a switching transistor, and T1 is a transformer. The input DC voltage Ei, the primary winding N1 of the transformer T1, and the switching transistor Q1 constitute a closed circuit.

N2 is a secondary winding of the transformer T1, Q2 is a rectifying transistor, and Q3 is a commutation transistor.
FETs are used as the transistors Q1 to Q3. D1 is a voltage element connected in series with the gate of FET Q2, and R1 is a bias resistor connected between the gate and source of FET Q2. As the voltage element D1, for example, a Zener diode is used. The other end of the Zener diode D1 is connected to one end of a secondary winding N2.

D3 is a voltage element connected in series with the gate of the FET Q3, and R2 is a bias resistor connected between the gate and the source of the FET Q3. As the voltage element D2, for example, a Zener diode is used. The other end of the Zener diode D2 is connected to one end of the secondary winding.

L1 is a choke coil connected downstream of the secondary rectifier circuit, and C1 is a smoothing capacitor connected to the choke coil L1. RL is a load resistance connected to the output of the smoothing circuit. R3 and R4 are load resistances RL
R3 and R4 form a series circuit, and a monitor signal of the output voltage Eo is extracted from the voltage dividing point.

Reference numeral 1 denotes a controller which applies a control voltage to the gate of the switching FET Q1, inputs the divided voltage as a monitor voltage, and controls the conduction time of the FET Q1 so that the monitor signal of the output voltage becomes constant. .

With this configuration, the voltage element can be replaced by an FET.
By connecting in series to the gate of the, to prevent reverse current from other power supply when used in parallel with other power supply,
The FETs Q2 and Q3 can be prevented from malfunctioning.

(2) The invention according to claim 2 is characterized in that a third winding for emitting excitation energy of a transformer and an energy emission circuit are provided in a rectifying and smoothing circuit of the third winding.

With this configuration, the switching F
When the ET is off, the commutation FET Q3 is continuously turned on, and the efficiency can be improved.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a diagram showing voltage values of respective parts of the principle circuit diagram of FIG.
It is a figure showing a current value. Here, the bias resistors R1 and R2 shown in FIG. 1 are omitted. In the figure,
VQ2 is a voltage applied to both ends of the rectifying FET Q2, and IQ2 is Q
VG2 is the gate voltage of Q2, VQ3 is the voltage applied across the commutation FET Q3, D is the parasitic diode of Q3, IQD3 is the current flowing through the parasitic diode D, IQ
Q3 is a current flowing through the FET Q3, IQ3 is a current flowing through Q3 and the diode D, and is the sum of IQD3 and IQQ3. VG3 is Q3
Gate voltage.

FIG. 3 is a time chart showing operation waveforms of respective parts of the principle circuit diagram shown in FIG. (A) is FET Q1
(B) shows the gate voltage VG2 of the FET Q2, (c) shows the voltage VQ2 applied to both ends of the FET Q2, (d) shows the current IQ2 flowing through the FET Q2,
(E) shows the gate voltage VG3 of the FET Q3, and (f) shows the FE
The voltage VQ3 applied to both ends of TQ3, (g)
(H) shows the current IQD3 flowing through the parasitic diode D of the FET Q3, and (i) shows the total current IQ3 flowing through the parasitic diode D of the FET Q3.
The current IQQ3 flowing through TQ3 is shown.

In (a), t1 indicates the time when Q1 is turned on, and t3 indicates the time when Q2 is turned off. The switching cycle of this circuit is T = t1 + t2. The area S1 where Q1 is turned on and the area S2 where it is turned off indicated by hatching in the figure are equal. In this case, the input voltage E
The amplitude of S2 whose amplitude level is larger than i is calculated as the average value E
Assuming that c ′, the relationship of Ei · t1 = Ec ′ · t3 holds. Since a pulse VG2 synchronized with the cycle of VQ1 is applied to Q2 as a gate voltage, a period during which VG2 is at "H" level is a period during which the FET Q2 is turned on. That is,
It is synchronized with the switching waveform of the primary side FET Q1 of the transformer T1. At this time, the voltage waveform VQ2 applied to Q2 has a waveform as shown in FIG. During the time when Q2 is turned on, a current IQ2 as shown in (d) flows through Q2.

When the switching FET Q1 is turned off,
The gate voltage VG3 of Q3 is as shown in FIG. Then, the time from when the predetermined time t4 elapses after IQ2 stops flowing to when VG3 turns on the FET Q3 is t5. The time from when t5 falls to a predetermined level to when the next VG3 rises to a predetermined level is t6. As shown in FIG. 5F, Q3 is off between t4 and t6, and is on during t5.

The total sum IQ3 of the current flowing through the FET Q3 while the switching FET Q1 is off is Ih shown in (h).
It is the sum of QD3 and IQQ3 shown in (i).

In such a series of operations, the controller 1 controls the conduction time of the switching FET Q1 so that the output voltage Eo becomes constant.

According to the circuit of FIG. 1, when the power supplies are connected in parallel, the backflow from other power supplies is prevented by the Zener diodes D1 and D2 set higher than the output voltage.

As shown in FIG. 1, the Zener diode is
By connecting in series to the gates of ETQ2 and Q3,
When used in parallel with another power supply, a reverse current from the other power supply can be prevented, and the FETs Q2 and Q3 can be prevented from malfunctioning.

FIG. 4 is a circuit diagram showing a first embodiment of the present invention. 1 are denoted by the same reference numerals. The difference between the embodiment shown in the figure and the principle circuit diagram shown in FIG. 1 is a circuit around the rectifying FET Q2. That is, a DC current cutting capacitor C2 is connected in series with the Zener diode D1, and a series circuit of the diode D2 and the Zener diode D4 is provided in the bias resistor R1. The operation of the circuit thus configured will be described as follows.

When the switching FET Q1 is ON, one end of the secondary winding N2 of the transformer T1 (•: positive voltage)
To capacitor C2- Zener diode D1-FET
A voltage is applied to the gate of Q2, turning on Q2. At this time, a smoothed DC voltage is applied to the load resistor RL by the closed circuit of the choke coil L1 and the smoothing capacitor C1.

When the switching FET Q1 is off At this time, the voltage polarity of the secondary winding N2 of the transformer T1 is inverted (marked by a negative voltage), Q2 is turned off, and Q3 is driven via the Zener diode D3. , Turn on. In this case, choke coil L1-smoothing capacitor C1-Q
By the closed circuit of No. 3, a smoothed DC voltage is applied to the load resistor RL.

This DC voltage Eo is detected by a voltage dividing circuit composed of resistors R3 and R4 and supplied to the controller 1, and the output voltage is stabilized by controlling the conduction time of the switching FET Q1.

According to this embodiment, the capacitor C2 is connected in series to the drive circuit for driving the FET Q2 in addition to the Zener diode D1. By providing the capacitor C2, the simultaneous ON current of the FETs Q2 and Q3 can be suppressed by providing the DC current cutting capacitor C2.

Further, according to this embodiment, a series circuit of a reverse current preventing diode D2 and a reverse bias voltage zener diode D4 is provided between the gate and source of the rectifying FET Q2. This determines the reverse bias voltage between the gate and source of the FET, delays the ON operation, and
Simultaneous ON current of ETQ2 and Q3 can be suppressed.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention. The same components as those in FIG. 4 are denoted by the same reference numerals. This embodiment is different from the rectifying FET Q2 shown in FIG.
Is provided also around the commutation FET Q3.

In the figure, C3 is a Zener diode D
3, a DC current cutting capacitor provided in series with Q3, and the other end is connected to the drain of Q2. A series circuit of a diode D5 and a Zener diode D6 is connected between the gate and source of the commutation FET Q3.
The operation of the circuit thus configured is the same as the operation of the circuit shown in FIG. The difference is that the DC current cutting capacitor C3 is connected in series with the driving zener diode D3 of Q3.
Is provided, the simultaneous ON current of the FETs Q2 and Q3 can be suppressed, and a series circuit of a reverse current preventing diode and a reverse bias voltage Zener diode is provided between the gate and the source of the Q3. Of the FET Q2, Q
3 can suppress the simultaneous on-current.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention. 1 are denoted by the same reference numerals. In this embodiment, a transformer T1 is provided with a tertiary winding N3, and the power generated in the tertiary winding is connected to a resistor R5.
And a capacitor C4. Further, the power consumption of the resistor R5 may be used as a power supply of a controller that drives the converter.

FIG. 7 is a time chart showing operation waveforms of respective parts according to the third embodiment of the present invention. (A) is the voltage VQ1 applied across the switching FET Q1, and (b) is the gate voltage VG applied to the gate of the rectifying FET Q2.
2. (c) is the voltage VQ2 across the rectifying FET Q2,
(D) is a current IQ2 flowing through the FET Q2, (e) is a gate voltage VG3 applied to the commutation FET Q3, and (f) is FE.
The voltage VQ3 at both ends of TQ3, (g) is the current IQ3 flowing through the FET Q3, (h) is the current IQD3 flowing through the parasitic diode D of Q3, and (i) is the current IQQ3 flowing through Q3.

In the circuit configured as described above, when the input voltage Ei is ON, the area when Q1 is on is S1, Q1.
Assuming that the area when is off is S2, S1 = S2 holds. If the time when Q1 is on is t1 and the time when Q1 is off is t2, the relationship of Ei · t1 = Ec · t2 holds. Here, Ec is a difference when VQ1 is higher than Ei.

The power PQ3 consumed by the commutation FET Q3 at this time is expressed by the following equation.

PQ3 = IQ3.VQ3.toff / T toff is a period during which Q1 is off, and T is a switching cycle. In this embodiment, the third winding N3 is connected to the transformer T.
And a consumption circuit including the resistor R5 and the capacitor C4 is provided. With such a configuration, when the switching FET Q1 is off, the commutation FET is continuously on, and the efficiency can be improved.

[0038]

As described above, according to the present invention,
The following effects can be obtained.

(1) According to the first aspect of the invention, a voltage element higher than the output voltage is connected in series to each gate of the rectifying FET and the commutating FET provided on the secondary side of the transformer. By connecting a biasing resistor between the gate and source of each FET, connecting the voltage element in series with the gate of the FET, the backflow from another power supply when used in parallel with another power supply Prevent current, FET
Q2 and Q3 can be prevented from malfunctioning.

(2) According to the second aspect of the present invention, switching is provided by providing the third winding for emitting the excitation energy of the transformer and the energy emitting circuit in the rectifying and smoothing circuit of the third winding. When the power FET is off, the commutation FET Q3 is continuously turned on, and the efficiency can be improved.

Further, according to the present invention, by using a Zener diode as the voltage element, the Zener diode is connected in series to the gate of the FET, so that the Zener diode can be connected in parallel with another power source. The back current from the power supply can be prevented, and the FETs Q2 and Q3 can be prevented from malfunctioning.

According to the present invention, the rectifying FET is
By connecting a series circuit of a backflow prevention element and a reverse bias voltage element between the gate and source of the FET, the reverse bias voltage between the gate and source of the FET is determined, the ON operation is delayed, and the simultaneous ON current is suppressed. be able to.

According to the invention, the commutation FET is
By connecting a series circuit of a reverse current prevention diode and a reverse bias voltage element in parallel between the gate and source of
The reverse bias voltage between the gate and the source of the FET is determined, the ON operation is delayed, and the simultaneous ON current can be suppressed.

According to the present invention, a DC current cutting capacitor is connected in series with the voltage element, thereby providing a DC current cutting capacitor.
Simultaneous ON current of TQ2 and Q3 can be suppressed.

As described above, according to the present invention, there is provided a power supply device (synchronous rectification type converter) capable of suppressing a backflow (regeneration of electric power) which has been a problem in a conventional circuit and supplying a stable output voltage. can do.

[Brief description of the drawings]

FIG. 1 is a principle circuit diagram of the present invention.

FIG. 2 is a diagram showing a voltage value and a current value of each part of the principle circuit diagram.

FIG. 3 is a time chart showing an operation waveform of each part of the principle circuit diagram.

FIG. 4 is a circuit diagram showing a first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a time chart showing operation waveforms of respective units according to the third embodiment of the present invention.

FIG. 8 is a diagram showing a conventional circuit example of a synchronous rectification type converter.

[Explanation of symbols]

 1 Controller Q1-Q3 FET T1 Transformer D1, D3 Zener diode R1-R4 Resistance RL Load resistance L1 Choke coil C1 Capacitor

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toshifumi Washio 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within Fujitsu Limited (reference) 5H730 AA14 AS01 BB23 BB57 DD04 EE02 EE08 EE10 EE14 FD01

Claims (2)

[Claims] In a synchronous rectification type converter using an FET, a voltage element higher than an output voltage is connected in series to respective gates of a rectification FET and a commutation FET provided on a secondary side of a transformer, Synchronous rectification type converter characterized in that a bias resistor is connected between the gate and source of each FET. 2. The synchronous rectifier type converter according to claim 1, wherein a third winding for emitting excitation energy of the transformer and an energy emission circuit are provided in a rectifying and smoothing circuit of the third winding.