JP2001203315A - マルチチップ・パッケージにおけるｉｃチップのクラスタ・パッケージング - Google Patents

マルチチップ・パッケージにおけるｉｃチップのクラスタ・パッケージング

Info

Publication number
JP2001203315A
JP2001203315A JP2000362327A JP2000362327A JP2001203315A JP 2001203315 A JP2001203315 A JP 2001203315A JP 2000362327 A JP2000362327 A JP 2000362327A JP 2000362327 A JP2000362327 A JP 2000362327A JP 2001203315 A JP2001203315 A JP 2001203315A
Authority
JP
Japan
Prior art keywords
chip
cluster
chips
functioning
site
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000362327A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001203315A5 (https=
Inventor
Thaddeus John Gabara
ジョン ガバラ サデウス
J Jakara Jerichio
ジェー．ジャカラ ジェリチォ
Kevin John O'connor
ジョン オコナー ケビン
King L Tai
エル．タイ キング
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of JP2001203315A publication Critical patent/JP2001203315A/ja
Publication of JP2001203315A5 publication Critical patent/JP2001203315A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2000362327A 1999-11-29 2000-11-29 マルチチップ・パッケージにおけるｉｃチップのクラスタ・パッケージング Pending JP2001203315A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45052499A 1999-11-29 1999-11-29
US09/450524 1999-11-29

Publications (2)

Publication Number Publication Date
JP2001203315A true JP2001203315A (ja) 2001-07-27
JP2001203315A5 JP2001203315A5 (https=) 2008-01-10

Family

ID=23788426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000362327A Pending JP2001203315A (ja) 1999-11-29 2000-11-29 マルチチップ・パッケージにおけるｉｃチップのクラスタ・パッケージング

Country Status (2)

Country Link
JP (1) JP2001203315A (https=)
KR (1) KR100806060B1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310411A (ja) * 2005-04-26 2006-11-09 Fujitsu Ltd 半導体装置
JP2009503846A (ja) * 2005-07-29 2009-01-29 フリースケール セミコンダクター インコーポレイテッド 多数のダイパネルを用いた３次元集積回路の製造
CN115116880A (zh) * 2022-07-22 2022-09-27 上海壁仞智能科技有限公司 芯片制造方法及设备

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102080865B1 (ko) * 2018-02-12 2020-02-24 세메스 주식회사 다이 본딩 방법
CN113825202B (zh) * 2021-09-28 2025-06-10 上海兆芯集成电路股份有限公司 跨芯片处理系统以及其路由方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52142481A (en) * 1976-05-22 1977-11-28 Toshiba Corp Production of semiconductor device
JPH01235264A (ja) * 1988-03-15 1989-09-20 Toshiba Corp 半導体集積回路装置
JPH03214764A (ja) * 1990-01-19 1991-09-19 Sharp Corp 半導体チップの製造方法
JPH07202003A (ja) * 1993-12-30 1995-08-04 Nec Corp 半導体装置
JPH11330256A (ja) * 1998-05-19 1999-11-30 Tif:Kk 半導体装置およびその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5240866A (en) * 1992-02-03 1993-08-31 At&T Bell Laboratories Method for characterizing failed circuits on semiconductor wafers
US5915231A (en) * 1997-02-26 1999-06-22 Micron Technology, Inc. Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52142481A (en) * 1976-05-22 1977-11-28 Toshiba Corp Production of semiconductor device
JPH01235264A (ja) * 1988-03-15 1989-09-20 Toshiba Corp 半導体集積回路装置
JPH03214764A (ja) * 1990-01-19 1991-09-19 Sharp Corp 半導体チップの製造方法
JPH07202003A (ja) * 1993-12-30 1995-08-04 Nec Corp 半導体装置
JPH11330256A (ja) * 1998-05-19 1999-11-30 Tif:Kk 半導体装置およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310411A (ja) * 2005-04-26 2006-11-09 Fujitsu Ltd 半導体装置
JP2009503846A (ja) * 2005-07-29 2009-01-29 フリースケール セミコンダクター インコーポレイテッド 多数のダイパネルを用いた３次元集積回路の製造
CN115116880A (zh) * 2022-07-22 2022-09-27 上海壁仞智能科技有限公司 芯片制造方法及设备
CN115116880B (zh) * 2022-07-22 2026-04-07 上海壁仞科技股份有限公司 芯片制造方法及设备

Also Published As

Publication number Publication date
KR100806060B1 (ko) 2008-02-21
KR20010051973A (ko) 2001-06-25

Similar Documents

Publication Publication Date Title
US12451436B2 (en) Interconnecting a plurality of dies having spare input/output circuit
CN114664788B (zh) 阵列结构的裸片缝合和收获
US7977156B2 (en) Chipstack package and manufacturing method thereof
US7329899B2 (en) Wafer-level redistribution circuit
US5656553A (en) Method for forming a monolithic electronic module by dicing wafer stacks
US6121677A (en) Reduced size integrated circuits and methods using test pads located in scribe regions of integrated circuits wafers
US5489538A (en) Method of die burn-in
US11862557B2 (en) Selectable monolithic or external scalable die-to-die interconnection system methodology
KR20180111885A (ko) 웨이퍼/다이 스택을 위한 수정 다이
JPH08236688A (ja) 電子モジュールおよびその形成方法
US20020081755A1 (en) Method of testing and constructing monolithic multi-chip modules
EP2790027B1 (en) Two-step interconnect testing of semiconductor dies
US20080318348A1 (en) Method of constructing a stacked-die semiconductor structure
JP2001203315A (ja) マルチチップ・パッケージにおけるｉｃチップのクラスタ・パッケージング
US7208758B2 (en) Dynamic integrated circuit clusters, modules including same and methods of fabricating
US5940680A (en) Method for manufacturing known good die array having solder bumps
JPH09127188A (ja) 集積回路を作る方法およびウェハ上のダイを検査するためのシステム
US20250174501A1 (en) Probing bump placement over multiple via openings
CN222600972U (zh) 芯片封装体、工作组件和计算设备
US7776650B2 (en) Method for fabricating a flip chip system in package
TW202610058A (zh) 陣列化結構的晶粒拼接及採集
EP0155965A1 (en) Wafer

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071116

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071116

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100712

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100720

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20101020

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20101025

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110118

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20110118

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111124

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120224

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120516