JP2001201532A - Method and apparatus for testing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for testing a semiconductor device capable of testing a semiconductor device outputting a reference clock DQS, used for data delivery, simultaneously to data reading, with high accuracy in a short period. SOLUTION: A timing for rising and falling of a reference clock outputted simultaneously with data read from a semiconductor device is read by plural signal reading circuit sampling acting with strobe pulse consisting of polyphase pulse having slight phase difference, and the timing for rising and falling of the reference clock is prescribed by a phase number of the polyphase pulse detecting a changing point, and the phase number is memorized by a memory 32. During testing, the data read from the semiconductor device is read by the timing determined by the phase number and it is judged whether there is a changing point or not with the timing so that quality of the semiconductor device is evaluated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device test method suitable for testing a semiconductor device equipped with a readable memory and a semiconductor device test apparatus that operates using the test method.

[0002]

2. Description of the Related Art Some types of memories composed of semiconductors receive data together with a clock, write data to a semiconductor device in synchronization with the clock, and output data synchronized with the clock together with the clock from the semiconductor device.
There is a memory that transfers data using the timing of this clock. FIG. 10 shows a state of this type of memory at the time of reading. DA, DB, DC shown in FIG. 10A
Indicate data output from the semiconductor device (data output from a certain pin). TD1, TD2 ...
Indicates each test cycle. DQS shown in FIG. 10B indicates a clock output from the memory. Data DA, D
Are output from the semiconductor device in synchronization with the clock DQS. This clock is used as a synchronization signal (data strobe) when transferring data DA, DB, DC... To other circuits in a practical state.

One of the test items for testing this type of semiconductor device is a time difference (from the rising and falling timing of each clock DQS (hereinafter referred to as a reference clock)) to the data change point. Phase difference) d
There are items for measuring I1, dI2, dI3,. The time differences dI1, dI2, dI3,... Are evaluated as devices having, for example, as fast response and excellent characteristics as possible as short as possible. The grade of the semiconductor device under test is determined by the length of the time difference.

In a practical state, a clock generated by a clock source is applied to a semiconductor device as a reference clock DQS output from the semiconductor device under test, and the clock is distributed to a circuit inside the semiconductor device. Data is output in synchronization with. Therefore, even when a test is performed by the test apparatus, a clock is applied to the semiconductor device under test from the test apparatus side, and the clock passes through the inside of the semiconductor device under test and is output together with data as a reference clock for data transfer. . Therefore, the rising and falling timings of the reference clock are measured, and the times dI1, dI from the measured rising and falling timings to the changing points of the data DA, DB, DC.
2, dI3... Will be measured.

As described above, since the reference clock output from the semiconductor device is output after passing through the inside of the semiconductor device, the rising timing and the falling timing are determined by the internal timing of each semiconductor device and the temperature and the like. Due to the influence of the external environment, the reference clocks DQS1 and DQS1
2, a phenomenon in which a difference occurs in the phase of DQS3.
Furthermore, in addition to the difference in phase between the semiconductor devices, the difference in the address of the memory accessed inside the semiconductor device, and the phenomenon that a so-called jitter J that fluctuates with the passage of time (thermal change) is also observed. Can be

Therefore, the data DA and D are determined from the rising and falling timings of the reference clock DQS.
Times dI1, dI2, dI3 until change points of B, DC,...
In order to accurately measure the timing, first, the rising timing and the falling timing of the reference clock DQS output from the semiconductor device must be accurately measured. For this reason, conventionally, the application timing of the strobe pulse of the signal reading circuit provided in the semiconductor device test apparatus is gradually moved, the rising and falling timing of the reference clock DQS is measured, and the time dI1 , DI2, dI3...

FIG. 12 shows a configuration of a portion for measuring the rising and falling timings of a conventionally used reference clock DQS. The level comparator 10 includes a pair of voltage comparators CP1 and CP2. The pair of voltage comparators CP1 and CP2 determine whether the logic value of the reference clock DQS output from the semiconductor device under test DUT satisfies a normal voltage condition. Determine whether or not. The voltage comparator CP1 determines whether or not the H logic voltage value of the reference clock DQS is equal to or higher than the normal voltage value VOH. Further, the voltage comparator CP2 determines whether the voltage value on the L logic side of the reference clock DQS is equal to or lower than the normal voltage VOL.

The results of these determinations are input to a signal reading circuit 11, and the signal reading circuit 11 measures the rising timing and falling timing of the reference clock DQS. The signal reading circuit 11 performs an operation of reading the logical value input at that time for each application timing of the strobe pulse STB. The strobe pulse STB is applied with a slight phase difference (τT) given for each test cycle. That is, the strobe pulse STB is supplied to the signal reading circuit 11 one by one in each test cycle, and the operation of reading the output states of the voltage comparators CP1 and CP2 is executed.

The logic comparator 12 compares the logic value output from the signal reading circuit 11 with a predetermined expected value (H logic in the example in the figure), and the logic value output from the signal reading circuit 11 matches the expected value. At this point, a path signal PA indicating a path (good) is output. The time T1 is known from the generation timing of the strobe pulse STB1 (the generation timing of the strobe pulse STB is known) which reads that the output of the level comparator 10 has been inverted to H logic, and the rising timing of the reference clock DQS is determined.

When detecting the falling timing of the reference clock DQS, the generation of the strobe pulse STB starts at a timing later than the timing when the reference clock DQS rises to the H logic, and similarly to the detection of the rising. The fall timing is determined by the strobe pulse reading the state in which the output of the voltage comparator CP2 is inverted to H logic.

[0011]

As described above, the generation timing of the reference clock DQS is conventionally determined by using the signal reading circuit 11 provided in the semiconductor test apparatus and the strobe pulse STB applied to the signal reading circuit 11. Since the measurement is performed using the timing measuring means, the test cycle TD has to be repeatedly executed many times even if only the rising and falling timings of the reference clock DQS are measured.

Moreover, the rise and fall timings of the reference clock DQS must be measured over the entire period from the start to the end of the test pattern in order to avoid the influence of jitter due to all addresses to be tested or heat generation. Therefore, it takes a long time to measure the rising and falling timings of the reference clock. As a method of shortening the time for measuring the rising and falling timings of the reference clock DQS, it is conceivable to roughly take the phase difference τT applied to the strobe pulse STB to reduce the number of test cycle executions. When the phase difference τT is roughly changed, the accuracy of the timing measurement of the rise and fall of the reference clock DQS decreases, and as a result, the time dI1, dI2, t1 to the change point of the reference clock DQS and the data DA, DB, DC. There is a disadvantage that the reliability of the measurement results of dI3.

An object of the present invention is to provide a semiconductor device test method capable of measuring the rise and fall timings of a reference clock in a very short time and with high accuracy, and a semiconductor device test apparatus using the test method. Is what you do.

[0014]

According to the first aspect of the present invention, a reference clock for delivering the data is output accompanying the data output from the device under test, and the timing of the reference clock and the change in the data are output. In a semiconductor device test apparatus that measures time to a point and evaluates a device under test in accordance with the measured value of this time, the timing at which a reference clock is output in advance for each test cycle is measured over all of the addresses under test. A semiconductor device test method is proposed in which a stored measurement result of each test cycle is determined as a reference phase position for measuring a time until a data change point.

According to a second aspect of the present invention, in the semiconductor device testing method according to the first aspect, a multi-phase pulse having a slight phase difference is sequentially generated from a predetermined phase position of each test cycle in each test cycle. By using this multi-phase pulse as the strobe pulse of the signal reading circuit for detecting the generation timing of the reference clock, the change point of the reference clock is measured by the phase number of the strobe pulse at which the change point of the reference clock is detected. We propose a method for testing semiconductor devices.

According to a third aspect of the present invention, in the semiconductor device testing method according to the first aspect, the phase number of the strobe pulse at which the change point of the reference clock is detected is an address corresponding to the address under test of the semiconductor device under test. When testing the semiconductor device under test stored in the provided memory, a phase number is read from an address corresponding to an address applied to the semiconductor device under test in the memory, and a logical value of data is read based on the read phase number. We propose a semiconductor device test method that determines the timing.

According to a fourth aspect of the present invention, in the semiconductor device testing method according to the first aspect, the phase number of the strobe pulse at which the change point of the reference clock is detected determines the order of generation of the test pattern applied to the semiconductor device under test. Stored in a memory having an address corresponding to the address to be represented,
When testing the semiconductor device under test, a phase number is read from an address indicating the order of generation of test patterns applied to the semiconductor device under test in the memory, and a timing for reading a logical value of data is determined based on the read phase number. We propose a method for testing semiconductor devices.

According to a fifth aspect of the present invention, in the semiconductor device test method according to the first aspect, a strobe pulse is generated at a preset timing in association with a phase number at which a change point of the reference clock is detected. A semiconductor device test method is proposed in which a logic value of data output from a semiconductor device under test is read at a pulse timing. According to a sixth aspect of the present invention, a data reading circuit for reading a logical value of data output from a semiconductor device under test in accordance with a strobe pulse application timing, and a data reading circuit provided for measuring a generation timing of a reference clock output from the semiconductor device under test. A plurality of signal reading circuits, a plurality of signal reading circuits, a multi-phase pulse generating means for applying a strobe pulse composed of a multi-phase pulse having a slight phase difference to each of the plurality of signal reading circuits, and a plurality of signal reading circuits A plurality of comparing and judging means for comparing the result read by each of these with an expected value; a converting means for converting the judgment result of the plurality of comparing and judging means into a phase number of a strobe pulse detecting a change point of the reference clock; An address corresponding to the address applied to the semiconductor device under test with the phase number converted by the conversion means. Memory, a timing selection circuit for setting the generation timing of the strobe pulse corresponding to the phase number each time the phase number stored in the memory is read, and a timing setting set in the timing selection circuit A semiconductor device test apparatus comprising a strobe pulse generating circuit for generating a strobe pulse to be applied to a data reading circuit according to a value is proposed.

According to a seventh aspect of the present invention, there is provided a data reading circuit for reading data output from a semiconductor device under test in accordance with the application timing of a strobe pulse, and a circuit for measuring the generation timing of a reference clock output from the semiconductor device under test. A plurality of signal reading circuits, a plurality of signal reading circuits, a multi-phase pulse generating means for applying a strobe pulse composed of a multi-phase pulse having a slight phase difference to each of the plurality of signal reading circuits, and a plurality of signal reading circuits A plurality of comparing and judging means for comparing the result read by each of these with an expected value; a converting means for converting the judgment result of the plurality of comparing and judging means into a phase number of a strobe pulse detecting a change point of the reference clock; Generation of a test pattern in which the phase number converted by the conversion means is applied to the semiconductor device under test. A memory for storing at an address corresponding to an address indicating an order, a timing selection circuit for setting a generation timing of a strobe pulse corresponding to the phase number each time the phase number stored in the memory is read; The present invention proposes a semiconductor device test apparatus including a strobe generating circuit that generates a strobe pulse to be applied to a data reading circuit according to a timing set value set in a circuit.

According to an eighth aspect of the present invention, in any one of the semiconductor device test apparatuses according to the sixth and seventh aspects, the multi-phase pulse generating means is constituted by a plurality of delay elements having slightly different delay times. We propose a semiconductor device test apparatus that applies a pulse to a delay element to generate a multi-phase pulse with a small phase difference. According to a ninth aspect of the present invention, in any one of the semiconductor device test apparatuses according to the sixth or seventh aspect, the multi-phase pulse generating means cascade-connects a plurality of delay elements having the same delay time,
The present invention proposes a semiconductor device test apparatus configured to obtain a multiphase pulse from each connection point of a plurality of cascade-connected delay elements.

According to a tenth aspect of the present invention, in any one of the semiconductor device test apparatuses according to the sixth and seventh aspects,
The plurality of comparison / judgment means sequentially outputs the result of the comparison judgment to the comparison / judgment means having the next longer delay time from the side having the shortest delay time of the strobe pulse composed of the multi-phase pulse. A configuration in which the validity determination result is output only from the comparison determination means that has detected a mismatch with the determination result, and the output bit position of the validity determination result is converted into a phase number of a strobe pulse in which a change point of the reference clock is detected. We propose a test device for semiconductor devices.

[0022]

According to the semiconductor device testing method of the present invention, the rise and fall timings of the reference clock are measured using the multi-phase pulses, so that the rise or fall timing of the reference clock can be measured within one test cycle. Can be measured. Moreover, by adopting a small phase difference given to the multi-phase pulse, the timing measurement accuracy of the rise and fall of the reference clock DQS can be made high. Therefore, the rising and falling timings of the reference clock can be measured in a short time and with high accuracy. As a result, the reference clock DQS and the data DA, DB,
It is possible to obtain a measurement result up to the change point of DC in a short time and to obtain an advantage that reliability can be improved.

[0023]

FIG. 1 shows a configuration of a main part of a semiconductor device test apparatus which operates using a semiconductor device test method according to the present invention. Before describing the main part of the present invention shown in FIG. 1, an outline of a test apparatus for testing a general semiconductor device will be described with reference to FIG. 2 just in case. In the figure, TES indicates the entire semiconductor device test apparatus. The semiconductor device test apparatus TES includes a main controller 13 and a pattern generator 1
4. Timing generator 15, waveform formatter 16, logical comparator 12, driver 17, signal reading circuit 11, failure analysis memory 18, logical amplitude reference voltage source 19, comparison reference voltage source 21, device power supply 22, etc. . still,
Here, the level comparator 10 shown in FIG. 12 is shown as being included in the signal reading circuit 11.

The main controller 13 is generally constituted by a computer system, and mainly comprises a pattern generator 14 and a timing generator 1 according to a test program created by a user.
5, the test pattern data is generated from the pattern generator 14, the test pattern data is converted into a test pattern signal having an actual waveform by the waveform formatter 16, and the test pattern signal is set by the logical amplitude reference voltage source 19. The voltage is applied to the semiconductor device under test DUT through the driver 17 that amplifies the voltage to a waveform having the determined amplitude value and stored.

The logical value of the response signal read from the semiconductor device under test DUT is read by the signal reading circuit 11. The logical comparator 12 compares the logical value read by the signal reading circuit 11 with the expected value output from the pattern generator 14, and when a mismatch occurs with the expected value, the memory cell at the read address has a defect. The failure address is stored in the failure analysis memory 18 every time a failure occurs.
At the end of the test, for example, it is determined whether the defective cell can be remedied.

FIG. 2 shows the configuration of a test apparatus for one pin. In reality, this configuration is provided for the number of pins of the semiconductor device under test DUT, and a test pattern input and a semiconductor test device are provided for each pin. The response signal of the device DUT is captured. In the present invention, as shown in FIG. 1, a level comparator 10, a polyphase pulse generator 30, and a plurality of signal reading circuits TC1, TC2, TC3, TC4, TC5... And a plurality of comparison / determination means PF1, PF2, PF3, PF4, PF5
, And these comparison / determination means PF1, PF2, PF3,
Conversion means 31 for converting the determination results of PF4, PF5... Into phase numbers of polyphase pulses, and a memory 3 for storing the phase numbers
2, a timing selection circuit 33 for selecting and outputting the generation timing of the strobe pulse STB from the phase number read from the memory 32 during the test, and a strobe generation for generating the strobe pulse STB at the timing selected by the timing selection circuit 33 The present invention proposes a semiconductor device test apparatus having a configuration provided with a circuit 34.

In this example, the polyphase pulse generator 30 includes a plurality of delay elements D whose delay times are set to slightly different values.
.., YY, DY2, DY3, DY4, DY5,. Each delay element DY1, DY2, DY3,
By making the delay time of DY4, DY5,... Have a time difference of, for example, 100 PS (picoseconds), a multi-phase pulse having a time difference of 100 PS can be generated. FIG. 3B shows an example of the multi-phase pulse. The multi-phase pulses P1, P2, P3, P4... Each having a phase difference of, for example, 100 PS from a predetermined phase position of the test cycle TD are input to the strobe pulses of the signal reading circuits TC1, TC2, TC3, TC4, TC5. Terminal.

Signal reading circuits TC1, TC2, TC3, T
The level comparison result from the level comparator 10 is input to each input terminal of C4, TC5,. In FIG. 1, the reference clock D
The configuration when measuring the rising timing of QS is shown. Therefore, the signal reading circuits TC1, TC2, TC3, T
The output of the voltage comparator CP1 for performing level comparison on the H logic side is input to each input terminal of C4, TC5,. Although the configuration for measuring the falling timing of the reference clock DQS is omitted in FIG. 1, the configuration is the same as the configuration shown in FIG. 1, in which case a voltage comparator that performs level comparison on the L logic side The output of CP2 is read by a multi-phase pulse.

FIG. 3 shows how the rising timing of the reference clock DQS is measured, and FIG.
7 shows how the timing of falling of S is measured. FIG. 3A
4A shows a reference clock DQ output from a pin PN for outputting a reference clock of a semiconductor device under test DUT.
5 shows a waveform of S. The comparison voltage VOH is applied to the voltage comparator CP1 constituting the level comparator 10, and when the level of the reference clock DQS becomes higher than the comparison voltage VOH, the voltage comparator CP1 outputs H logic.

Therefore, when a strobe pulse composed of a multi-phase pulse is applied after the voltage comparator CP1 outputs H logic, the signal reading circuit outputs H logic. The comparison determination means PF1, PF2, PF3, PF4, PF5,... Each have an expected value (H logic in this example) and a signal reading circuit T.
C1, TC2, TC3, TC4, TC5... Are compared with each other, and the signal reading circuits TC1, TC2, TC
If the output of TC3, TC4, TC5,... Matches the expected value of H logic, H logic indicating the coincidence is output.

Each of the comparison / determination means PF1, PF2, PF3,
PF4, PF5... Are further upstream (the phase sequence of the polyphase pulse is 1).
The comparison result of the comparison judgment means of the next lower number is compared with the own signal reading result, and it is determined that the comparison result of the preceding stage and the own signal reading result are valid when there is a mismatch. Judge and output a judgment result indicating validity. The examples of FIGS. 3 and 4 show a case where the comparison / determination means PF4 outputs a determination result of H logic indicating validity.

FIG. 5 shows an example of a specific configuration of the PF4 as an example of the comparison determining means. In FIG. 5, the reference clock DQ
A case is shown in which the circuit can also be used as a circuit for measuring the falling timing of S. Therefore, the signal reading circuit TC4 'is connected to the output side of the voltage comparator CP2, and the strobe input terminals of the signal reading circuits TC4 and TC4' receive the strobe pulses P4 and TC4 'shown in FIGS. Given as

The comparing / determining means PF4 compares the expected value EXP with the outputs of the signal reading circuits TC4 and TC4 ', the gates G1 and G2, the OR gate G3 which takes the logical sum of the outputs of these gates G1 and G2, and the OR gate G3 And an inconsistency detection gate G4 for detecting an inconsistency between the output of the first stage and the comparison result of the preceding stage. The rising timing of the reference clock DQS is determined by the voltage comparator CP1.
, The signal reading circuit TC4, the gate G1, the OR gate G3, and the mismatch detection gate G4. H logic is given as the expected value when measuring the rising timing of the reference clock DQS, and L logic is set as the expected value when detecting the falling timing. When the expected value of the H logic is set, the gate G1 becomes valid, and this gate G1
Monitors whether or not the output of the signal reading circuit TC4 is inverted to H logic.

When the output of the signal reading circuit TC4 is inverted to the H logic, the output of the gate G1 is also inverted to the H logic, and the H logic is input to the mismatch detection gate G4 through the OR gate G3. The non-coincidence detection gate G4 can be constituted by, for example, an exclusive OR circuit. One input terminal of the non-coincidence detection gate G4 is provided with the comparison / determination result P / F of the preceding stage. The comparison / determination result P / F of the preceding stage is not H logic, and its own signal reading circuit T
Only when the read result of C4 is inverted to H logic, the mismatch detection gate G4 outputs H logic. The output of the H logic is input to the conversion means 31 shown in FIG. 1 and is also supplied to the comparison determination means of the next stage, here PF5. In the comparison determination means PF5 of the next stage, its own signal reading circuit PC5
Although the logic is output, the detection result of mismatch is not output because the H logic is input from the comparison determination means PF4 in the preceding stage.
L logic is output.

As a result, only the comparison determination means to which the multi-phase pulse is applied first from the time when the level of the reference clock DQS exceeds the comparison voltage VOH provided for level comparison outputs H logic. Note that L logic is given to the mismatch detection gate G4 of the first-stage comparison / judgment means PF1 as a comparison judgment result of the first-stage. As a result, when its own signal reading circuit TC1 outputs H logic, it outputs an H logic mismatch detection signal, and detects that the reference clock DQS has risen at the beginning of the test cycle TD.

The conversion means 31 is provided with each of the comparison and judgment means PF1, P
F2, PF3, PF4, PF5... Are fetched and converted into data with the smallest possible number of bits.
That is, according to the present invention, the comparison determination means PF1, PF2, P
It is characterized in that the reading result of the signal reading circuit in which the respective judgment results of F3, PF4, PF5... Become valid is converted into the phase number of the given multiphase pulse. FIG. 6 shows a conversion algorithm of the conversion means 31. It is desirable to provide as many signal reading circuits TC1, TC2... And comparison judging means PF1, PF2... As possible with strobe intervals that can sufficiently satisfy the measurement accuracy with respect to device specifications. Comparison judgment means PF
1 to PF8 are shown as being present. When one of the eight comparison / determination means PF1 to PF8 outputs H logic (indicated by 1 in the figure), the bit position is set to a numerical value 1 to
8 and further subtracts “1” from the numerical value. In this example, the result is converted to 4-bit numerical data D0 to D7. 4-bit numerical data D0 to D7
Can be handled as a number representing the phase sequence of the polyphase pulses P1 to P8. It can be converted into a number for 16 phases from 0 to 15 by using 4 bits.
Store it in 2.

As described above, for example, by converting an 8-bit comparison result into 4-bit phase number data, an advantage that the storage space of the memory 32 can be reduced can be obtained. FIG.
In the embodiment shown in FIG. 2, the X and Y addresses applied from the pattern generator 14 to the semiconductor device under test DUT are appropriately converted by the address conversion circuit 35 as necessary (the memory 32).
And the measured values are stored in the addresses corresponding to the addresses to be applied to the semiconductor device under test DUT. Therefore, it is assumed that the memory 32 has addresses to be tested of the semiconductor device under test DUT, that is, all address spaces corresponding to the addresses to be tested.

Prior to testing the semiconductor device under test DUT, writing and reading are executed over all the addresses under test of the semiconductor device under test, and the rising and falling of the reference clock DQS output at the time of reading are executed. The timing is measured for each address applied to the semiconductor device under test DUT, and the phase number of the polyphase pulse obtained as a result of the measurement is stored in the memory 32. The falling timing of the reference clock DQS is measured by delaying the phases of the multiphase pulses P1, P2, P3, P4, P5... By a fixed amount toward the falling side of the reference clock DQS as shown in FIG. Done.

The rise or fall timing of the reference clock DQS is measured, and the test of the semiconductor device under test DUT is started in a state where the measurement result is stored in the memory 32. When testing a semiconductor device under test DUT,
Measurement results corresponding to the rising or falling timing of the reference clock DQS output when the address is accessed from the memory 32 in parallel with reading data from each address of the semiconductor device under test DUT Phase number). The read measurement result is input to the timing selection circuit 33 shown in FIG.
The application timing of the strobe pulse STB to be applied to the signal reading circuit 11 for reading data read from T is selected.

FIG. 7 shows an outline of the timing selection circuit 33. The timing selection circuit 33 outputs the strobe pulse STB
Memory 33A storing the occurrence timing of
And a selector 33B for selecting any of the generation timings stored in the timing memory 33A according to the measurement result read from the memory 32. The timing memory 33A has, for example, 200 PS, 3
16 time values of 00PS, 400PS, 500PS ... are stored. This time value is calculated for each test cycle T
It corresponds to the time value from the initial phase position of D, and indicates the timing of the rise or fall of the measured reference clock DQS. The timing given by this time value becomes a reference phase position for measuring the time dI1, dI2, dI3... Until the data change point to be measured. This time value is selected according to the measurement result stored in the memory 32, and the selected time value is input to the strobe generation circuit 34.

The strobe generation circuit 34 adds or subtracts the time (planned value) up to the change point of the data read from the semiconductor device under test DUT to the time value input from the timing selection circuit 33, and at the timing of the calculation result. A strobe pulse STB is generated, and the strobe pulse STB is applied to the signal reading circuit 11 to read data read from the semiconductor device under test DUT. Whether or not a data change point exists at the timing of the strobe pulse is determined. To test.

That is, the designer of the semiconductor device knows in advance the time from the rising or falling timing of the reference clock DQS to the change point of the data read from the semiconductor device as a design value. Therefore, the rising and falling timings of the reference clock DQS are measured in advance, and the timing is set to a known value, so that the data changes within a predetermined time range from the rising and falling timings of the reference clock DQS. Testing for the presence or absence of a point will enable an accurate test to be performed.

In the above description, the embodiment in which the rising or falling timing of the reference clock DQS is measured for each address of the semiconductor device under test DUT has been described. ), The rise and fall timings of the reference clock DQS gradually vary, by applying the present invention, it is possible to carry out a test in consideration of thermal drift.

FIG. 8 shows the embodiment. In this embodiment, a cycle counter 36 for counting the number of cycles of the test pattern output from the pattern generator 14 is provided. The cycle counter 36 counts which cycle of the test pattern is being tested. A case is shown in which the address conversion circuit 35 converts the data into an address signal of the memory 32 and accesses the memory 32 with the address signal. Therefore, prior to the test, in all the read modes from the start to the end of the test pattern (test program), the rising or falling timing position of the reference clock DQS output from the semiconductor device DUT is measured in advance. This measurement result is loaded into the memory 32. The test is started in a state where the rising or falling timing of the reference clock DQS is measured over the entire period from the start to the end of the test pattern. By reading the measurement result of the rising or falling timing of the reference clock DQS from the memory 32 during this test, and determining the timing of the strobe pulse for reading the data read from the device under test using this measurement result, Even if the timing of the reference clock DQS gradually changes with the passage of time, the timing at which data is read changes in accordance with the change, and a test can be performed in consideration of drift due to heat.

FIG. 9 shows a modified embodiment of the polyphase pulse generating means 30. In this embodiment, delay elements DY1, DY2, DY3, DY4, DY5... Having a slight delay time are connected in cascade, and a polyphase pulse with a slight phase difference is generated from each connection point. Show the case.

[0046]

As described above, according to the present invention, the multi-phase pulses P1, P2, P3, P4, and P4 shown in FIGS.
P5 ... and P1 ', P2', P3 ', P4', P5 '...
Is used to measure the rise or fall timing of the reference clock DQS within one test cycle TD, so that the rise or fall timing of the reference clock DQS can be measured in an extremely short time as compared with the related art. it can. As a result, this kind of semiconductor device can be tested in a short time and with high accuracy, and the advantage that the operational effect of the test apparatus can be enhanced can be obtained.

Since the measurement result of the rising or falling timing of the reference clock DQS is converted into the phase number of the multi-phase pulse, the number of data bits can be reduced. As a result, the storage capacity of the memory 32 can be reduced, thereby minimizing the cost increase in adding this circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor device test apparatus that operates using a semiconductor device test method according to the present invention.

FIG. 2 is a block diagram for explaining an outline of a general semiconductor device test apparatus.

FIG. 3 is a timing chart for explaining the operation of the main part of the semiconductor device test apparatus according to the present invention shown in FIG. 1;

FIG. 4 is a similar timing chart for explaining another example of the timing chart shown in FIG. 3;

FIG. 5 is a block diagram for explaining an example of the configuration of a comparison / determination means used in the semiconductor device test apparatus according to the present invention shown in FIG. 1;

FIG. 6 is a diagram for explaining the operation of the comparison / determination means shown in FIG. 5;

FIG. 7 is a block diagram for explaining a configuration of a timing selection circuit used in the semiconductor device test apparatus according to the present invention shown in FIG. 1;

FIG. 8 is a block diagram showing a modification of the semiconductor device test apparatus according to the present invention shown in FIG. 1;

FIG. 9 is a block diagram showing still another modified embodiment of the semiconductor device test apparatus according to the present invention.

FIG. 10 is a timing chart for explaining characteristics of a semiconductor device to be tested in the present invention.

FIG. 11 is a timing chart for explaining problems of the semiconductor device described in FIG. 10;

FIG. 12 is a block diagram for explaining a level comparator and a signal reading circuit provided in the semiconductor device test apparatus.

FIG. 13 is a timing chart for explaining operations of the level comparator and the signal reading circuit shown in FIG.

[Explanation of symbols]

 DQS Reference Clock DUT Semiconductor Device Under Test 10 Level Comparator CP1, CP2 Voltage Comparator 11 Signal Reading Circuit TC1 ... TC5 Signal Reading Circuit PF1 ... PF5 Comparison Judging Means 12 Logical Comparator P1 ... P6 Multiphase Pulse 30 Multiphase Pulse Generator 31 conversion means 32 memory 33 timing selection circuit 34 strobe generation circuit 35 address conversion circuit

Claims (10)

[Claims] 1. A reference clock for delivering the data is output along with the data output from the device under test, and the timing of the reference clock and the time until the data change point are measured. In a semiconductor device test apparatus for evaluating a device under test in accordance with a measured value, a timing at which the reference clock is output is measured and stored for all test addresses in advance for each test cycle, and the stored test cycle of each test cycle is measured. A method for testing a semiconductor device, comprising: determining a measurement result as a reference phase position for measuring a time until a change point of the data. 2. A semiconductor device test method according to claim 1, wherein a multi-phase pulse having a small phase difference is sequentially generated from a predetermined phase position, and the generation timing of the reference clock is detected from the multi-phase pulse. A method for measuring a change point of the reference clock by using a phase number of a strobe pulse that detects the change point of the reference clock by using the signal as a strobe pulse of a signal reading circuit for performing the operation. 3. The semiconductor device test method according to claim 1, wherein the phase number of the strobe pulse at which the change point of the reference clock is detected is stored in a memory having an address corresponding to the address under test of the semiconductor device under test. When testing the semiconductor device under test, the phase number is read from an address corresponding to the address applied to the semiconductor device under test in the memory, and the read timing of reading the logical value of the data is determined by the read phase number. A method for testing a semiconductor device, comprising: 4. The semiconductor device test method according to claim 1, wherein the phase number of the strobe pulse at which the change point of the reference clock is detected corresponds to an address indicating the order of generation of the test pattern applied to the semiconductor device under test. When testing a semiconductor device under test stored in a memory having an address, the phase number is read from an address indicating the order of generation of test patterns applied to the semiconductor device under test in the memory. A method for testing a semiconductor device, comprising determining a timing for reading a logical value of the data. 5. The semiconductor device test method according to claim 1, wherein a strobe pulse is generated at a preset timing in association with the phase number at which the reference clock change point is detected, and the strobe pulse is generated by the timing of the strobe pulse. A semiconductor device test method, comprising reading a logical value of data output by a test semiconductor device. 6. A data reading circuit for reading a logical value of data output from a semiconductor device under test in accordance with a strobe pulse application timing; and B, for measuring a generation timing of a reference clock output from the semiconductor device under test. C; a multi-phase pulse generating means for applying a strobe pulse composed of a multi-phase pulse having a slight phase difference to each of the plurality of signal reading circuits; E, a plurality of comparison / determination means for comparing the results read by each of the plurality of signal reading circuits with an expected value; and E, a determination result of the plurality of comparison / determination means based on a strobe pulse which detects a change point of the reference clock. Converting means for converting to a phase number; F, marking the phase number converted by the converting means on the semiconductor device under test. G, a memory for storing at an address corresponding to the selected address; G, a timing selection circuit for setting a generation timing of a strobe pulse corresponding to the phase number each time the phase number stored in the memory is read; A semiconductor device test apparatus comprising: a strobe generating circuit that generates a strobe pulse to be applied to the data reading circuit according to a timing set value set in a timing selecting circuit. 7. A data reading circuit for reading data output from a semiconductor device under test in accordance with a strobe pulse application timing; and B, provided for measuring the generation timing of a reference clock output from the semiconductor device under test. A plurality of signal reading circuits; C; a polyphase pulse generating means for applying a strobe pulse composed of a multiphase pulse having a slight phase difference to each of the plurality of signal reading circuits; A plurality of comparing and judging means for comparing the result read by each of the signal reading circuits with the expected value; and E, the judgment result of the plurality of comparing and judging means to the phase number of the strobe pulse detecting the change point of the reference clock. Conversion means for converting; F; a phase number converted by the conversion means applied to the semiconductor device under test; G, a memory for storing at an address corresponding to the address indicating the order of generation of the strobe pattern, and G, a timing selection for setting the generation timing of the strobe pulse corresponding to the phase number each time the phase number stored in the memory is read out A semiconductor device test apparatus comprising: a circuit; and H, a strobe generating circuit that generates a strobe pulse to be applied to the data reading circuit according to a timing set value set in the timing selecting circuit. 8. The semiconductor device test apparatus according to claim 6, wherein said multi-phase pulse generating means comprises a plurality of delay elements having slightly different delay times, and a pulse is applied to said plurality of delay elements. A semiconductor device test apparatus, which generates a multi-phase pulse that is applied with a slight phase difference. 9. The semiconductor device test apparatus according to claim 6, wherein the multi-phase pulse generating means cascade-connects a plurality of delay elements having the same delay time. A semiconductor device test apparatus wherein a multi-phase pulse is obtained from each connection point. 10. The semiconductor device test apparatus according to claim 6, wherein said plurality of comparison / judgment means includes a result of the comparison / judgment in ascending order of a delay time of a strobe pulse composed of said multi-phase pulse. Is output to the comparison and determination means having the next longer delay time,
Each comparing and judging means outputs a judging result to be valid only from the comparing and judging means which has detected inconsistency with the comparison judging result of each preceding stage. A semiconductor device test apparatus characterized in that it is configured to convert to a phase number of a strobe pulse.