JP2001196403A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor device called as a wafer level CSP to be improved in productivity and reduced in thickness ensuring mounting reliability for it. SOLUTION: This semiconductor device is equipped with a plurality of elastic insulating stays 14 preferably of a mesa-type on the main surface of a semiconductor chip 10 corresponding to each land of a printed wiring board. A plurality of wirings 17 for electrically connecting each of electrode pad to each land of the printed wiring board has a part 40 of the wiring 17 extended to the top of the insulating stay 14. An insulating resin 18 which forms a package covers the main surface with the region 40 of the wiring 17 exposed. A solder ball 19 is fixed in the exposed wiring region 40 on the top of the stay 40, by which the semiconductor chip 10 is mounted on the lands of the printed wiring board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called wafer-level CSP type semiconductor device in which semiconductor chips are packaged in a wafer state, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In the semiconductor device manufacturing industry, efforts are being made to further reduce the size of one packaged semiconductor device. The first effort to reduce the size of a semiconductor device is to reduce the size of the semiconductor chip itself. By reducing the size of the semiconductor chip, the number of chips that can be obtained from one wafer increases, the manufacturing cost can be reduced, and the moving distance of electrons between elements can be shortened.
Its operation speed is improved. Advances in microfabrication technology have made it possible to reduce the chip size of semiconductor devices having the same function. The current state-of-the-art design rule is 0.25 μm or less. According to this, it is possible to build more than 20 million transistors on one semiconductor chip.

The next effort to reduce the size of a semiconductor device is to make the size of a package for encapsulating a semiconductor chip as close as possible to the size of a built-in semiconductor chip. As a result of this effort,
Semiconductor devices of a type called a chip size package (Chip Size Package: CSP) or a chip scale package (Chip Scale Package) have been born. The chip size package has a package size such as two-dimensionally arranging connection terminals (for example, solder bumps; hereinafter, external connection terminals) for a printed wiring board on which a semiconductor device is mounted on a surface of a semiconductor chip. Successfully approached the chip size. By reducing the package size so as to approach the size of the semiconductor chip, the mounting area is reduced, and the wiring length between the electrodes on the chip and the external connection terminals is reduced, thereby reducing the size of the semiconductor chip itself. As in the case, the operation speed of the semiconductor device is improved.

On the other hand, there is a problem that the manufacturing cost cannot be reduced much even if the package size is reduced. This is because the package process is performed for each individual semiconductor chip cut out from the wafer, so that even if the package size is reduced, the number of process steps is constant and the productivity does not change.

[0005] Against such a background, a technique for packaging semiconductor chips in a wafer state (hereinafter referred to as a wafer-level CSP) has been proposed, and each company has been developing it for practical use. Wafer level CSP is a semiconductor manufacturing technology that packages individual semiconductor chips before cutting them out of the wafer. In the wafer-level CSP, since the package process can be integrated with the wafer process, there is an advantage that the package cost and, in turn, the chip manufacturing cost can be significantly reduced. For more detailed contents of wafer level CSP,
"Nikkei Micro Device published by Nikkei BP August 1998
Monthly Pages 44-71 ".

[0006]

On the other hand, the wafer-level CSP has a problem of mounting reliability on a printed wiring board as in the conventional CSP type semiconductor device. In a temperature cycle test for a semiconductor device of this type, a crack may be generated at a joint of an external connection terminal to a printed wiring board, resulting in an open defect. The main cause is a stress based on a difference in linear expansion coefficient between a silicon semiconductor chip and a printed wiring board made of FR4 or the like. In designing a wafer level CSP, it is necessary to take measures to alleviate this.

As a preferred method of absorbing the difference in linear expansion coefficient between the above members and relaxing the stress caused by the difference, a metal column is formed on the wiring pattern on the main surface of the semiconductor chip, and a solder bump is formed on the column. And the like having a structure in which external connection terminals are joined. In the semiconductor device, the main surface of the semiconductor chip and the periphery of the column are covered with an insulating resin. By interposing the pillar between the external connection terminal directly connected to the printed wiring board and the semiconductor chip, it is possible to mitigate the stress by deforming the pillar portion when the stress is generated.

On the other hand, a semiconductor device having the above-mentioned metal support has the following problems. (1) It takes time and cost to form the metal pillar on the main surface of the semiconductor chip. That is, the above-mentioned metal column is formed by metal plating (for example, copper plating) on the wiring pattern.
Are formed by laminating. In order to relieve the stress, it is necessary to make the pillars have a height of 100 μm or more, and it takes two hours or more to form the pillars by plating. In order to further improve the mounting reliability of the semiconductor device, it is necessary to further increase the height of the support (for example, 200 μm or more), but it is extremely difficult to realize this in view of the required time and cost. (2) Since the elastic modulus of the metal column is not always high (for example, the elastic modulus of copper is 110 GPa), the height of the column is set to 10
It is difficult to reduce the thickness to 0 μm or less, and as a result, the overall thickness of the semiconductor device cannot be reduced.

Therefore, an object of the present invention is to provide a wafer level C
It is an object of the present invention to improve the productivity and reduce the thickness of a semiconductor device called an SP while guaranteeing its mounting reliability.

[0010]

In order to achieve the above object, a semiconductor device of the present invention comprises a semiconductor substrate having an electric circuit formed on a main surface thereof, and an electrode pad formed on the semiconductor substrate. An insulating post formed on the semiconductor substrate at a position close to the electrode pad; a wiring formed on the semiconductor substrate from the electrode pad to the top of the insulating post; An insulating resin formed on the insulating resin, an opening formed on the insulating resin so that the wiring at the top of the insulating support is exposed, and a wiring on the top of the insulating support at the opening. External connection terminals formed so as to be connected to each other.

In a preferred aspect of the present invention, the insulating support is made of a polyimide resin, has a mesa shape, and has a height in a range of 30 μm to 60 μm.

The external connection terminal may be a solder ball, or the exposed wiring region may be formed to protrude from the surface of the insulating resin. It may be a terminal.

According to a method of manufacturing a semiconductor device of the present invention, an electrode pad is formed on a semiconductor substrate having an electric circuit formed on a main surface thereof, and an insulating pad is provided on the semiconductor substrate at a position close to the electrode pad. Forming a conductive pillar, forming a wiring from the electrode pad to the top of the insulating support on the semiconductor substrate, and exposing the wiring of the top of the insulating support on the semiconductor substrate. A step of forming an insulating resin; and a step of forming an external connection terminal on the wiring at the top of the insulating support.

In the method for manufacturing a semiconductor device according to the present invention,
The step of forming the insulating pillar includes forming an insulating resin film on the semiconductor substrate, etching the insulating resin film into a predetermined pattern, and curing the predetermined pattern. Forming the insulating pillar.

Further, in the method of manufacturing a semiconductor device according to the present invention, the step of forming the insulating resin so that the wiring at the top of the insulating support is exposed includes forming an insulating resin layer on the semiconductor substrate. And removing the insulating resin layer on the wiring on the top of the insulating support to expose the wiring on the top of the insulating support.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. In the method of manufacturing a semiconductor device according to the present embodiment, in a state of a wafer on which semiconductor elements are formed,
A package process is performed, and a packaged semiconductor device is obtained at the last stage of dicing the wafer. In the manufacturing method according to the present embodiment, insulating pillars are formed on the surface of a wafer on which semiconductor elements are formed, necessary wiring is provided, the wafer surface is sealed with resin, and solder balls as external connection terminals are formed. Transferring and dicing the wafer along the boundaries of the semiconductor devices to obtain individual packages. These specific steps will be sequentially described with reference to FIGS. It will be understood by those skilled in the art that these figures are shown deformed for explanation. In the figure, the cross section of a part of the wafer is shown.
Although only (corresponding to two semiconductor devices) are shown, it will be understood that the processes described below are performed over the entire area of the wafer according to the steps shown in the figure.

Prior to each of the illustrated steps, a normal wafer process is performed to form semiconductor elements arranged in a matrix on the surface of a silicon wafer. here,
One circuit pattern formed on a wafer corresponding to one semiconductor device is called a semiconductor element. On the wafer surface,
A plurality of electrode pads drawn from each semiconductor element are exposed, and in a later step, each electrode pad is electrically connected to an external connection terminal.

In the first step (A) according to the present embodiment, a photosensitive polyimide resin layer 11 is formed on the surface of the wafer 10 on which semiconductor elements have been formed in the above-described wafer process. This layer 11 covers the entire area of the wafer 10,
The electrode pad 10a is once covered. The layer 11 of photosensitive polyimide resin covers the surface of the relatively fragile silicon wafer, and mitigates the impact applied from the outside of the completed package from propagating to the wafer surface. Next, in a step (B), using a photomask, a region corresponding to the electrode pad 10a and a region along the boundary of the semiconductor element are masked, the photosensitive polyimide resin is exposed, and the polyimide resin on the region is exposed. Is removed by etching.

Next, steps (C) to (E) are performed to form a mesa bump as an insulating support on the wafer. That is, in the step (C), the photosensitive polyimide resin is dropped on the wafer 10 and uniformly spread over the entire area by the spin coater. After that, it is cured by curing, thereby forming a polyimide resin layer 12 having a predetermined thickness on the wafer 10. The thickness of the layer 12 is determined in consideration of the height of the mesa-type bump to be finally formed through the subsequent steps (D) and (E) (particularly, the amount of shrinkage due to curing in the step (E)). . In one example, the thickness of the layer was 0.06 mm in order to form a mesa bump having a height of 0.03 mm. In step (D),
Using a photomask, a region for forming a mesa bump,
That is, the region corresponding to the land of the printed wiring board is masked, and the exposed region of the photosensitive polyimide resin layer 12 is exposed to light and removed by etching. As a result, the pillar 13 made of a columnar polyimide resin is formed. Then the process
In (E), curing is performed on the remaining support 13 of the polyimide resin, thereby forming a mesa bump 14 on the wafer 10. In the curing, the contraction of the upper part of the columnar support 13 is larger than that of the lower part, so that a positive taper shape as shown in the step (E),
That is, the mesa-shaped bumps 14 are formed.

Next, on the wafer and the mesa bumps 14
Steps (F) to (I) in FIG.
Is carried out. In step (F), titanium tungsten (TiW) is deposited on the wafer surface including the mesa bumps 14 by ion sputtering, and then chromium (Cr), nickel
A barrier metal 15 is formed thereon by (Ni) or the like. Process
(G), a resist 16 for forming a wiring thereon is formed thereon.
Is formed by a photolithography technique. In step (H),
Copper (Cu) is plated on the barrier metal exposed by the resist 16 to form the wiring 17. As shown later in FIG. 4, one end of each wiring 17 is a circular region covering the mesa-shaped bump 14, and the other end is thinly extended to the electrode pad 10a. Then, after titanium tungsten (TiW) is deposited on the wafer surface again by ion sputtering, gold (A
u), palladium (Pd) and other hardly oxidizable noble metals are deposited on the wiring 17. In the following step (I), the resist 16 and the barrier metal 15 are removed. Through the above steps, the metal wiring is formed on the wafer 10.

Next, in a step (J) of FIG. 3, the resin 18 for the package is supplied onto the wafer 10 and spread uniformly over the entire surface of the wafer. The evenly spread surface height of the resin 18 completely covers the metal wiring 17. That is, in this step, the region 17 a of the wiring 17 on the mesa bump 14 is also temporarily buried in the resin 18. In order to uniformly supply the package resin 18 on the wafer, a spin coating method, a screen printing method, or another resin supply method can be adopted. The package resin 18 is preferably a photosensitive polyimide resin. Liquid or gel resin 18
Is cured by curing for a predetermined time. In the next step (K), the resin 1 on the mesa-shaped bump 14 is removed.
8 is removed, thereby exposing the wiring region 17a on the bump. Using a photomask, excluding the area on the area 17a, masking the area of the photosensitive polyimide resin 18, exposing the area on the area 17a,
Etching is removed (in the case of a negative type, a region on the region 17a is masked). Thereafter, the remaining resin 18 is cured to a hardness required as a package material.

In the present invention, the wiring region 1 on the bump
Other methods for exposing 7a are possible. For example, a method of grinding the entire surface of the resin 18 using a grinder or another grinding device may be considered. Grinding is performed until at least the end faces of all the mesa bumps 14 are exposed to the upper part.

Next, in the step (L), the solder balls 19 as external connection terminals formed in another step are transferred onto the wiring area 17a on each of the mesa bumps 14 and fixed by batch reflow. I do. Finally, in step (M),
The wafer 10 is diced using a dicing saw 31, and the semiconductor device 32 packaged through the above process is packaged.
Get.

FIG. 4 shows a plan view of a part of the wafer 10 in the step (I) of FIG. That is, in this drawing, the arrangement and shape of the metal wiring 17 in the region of one semiconductor chip are clearly shown. Each wiring 17 formed through the steps (F) to (I) has a circular shape covering the mesa-shaped bump 14 (when viewed three-dimensionally,
And a region 41 connected to the electrode pad 10a. The circular region 40 and the region 41 on the electrode pad are connected by a thin wiring 42. As described above, the solder ball 19 for realizing mounting on a printed board is fixed to the top of each circular area 40 (that is, the area 17a in FIG. 2). Wiring 17
Thus, electrical connection between the electrode pads 10a of the semiconductor chip and the solder balls 19 is realized.

As will be understood by those skilled in the art, the shape and arrangement of the metal wiring 17 are not limited. These may be anything that guarantees the electrical connection between the electrode pad 10a and the solder ball 19. That is, it is sufficient that a part of the wiring 17 reaches the top of the mesa bump 14 and the other part is on the electrode pad 10a. In order to achieve the object of the present invention, the region 40 may not completely cover the mesa bump 14. The arrangement of the metal wirings 17 is basically determined only by the positions of the electrode pads 10a on the chip, the positions of the mesa bumps 14 on which the solder balls are mounted, and the number thereof. Those skilled in the art understand that the arrangement of metal wiring that can be determined by these factors in the design of a semiconductor device is various,
It will be appreciated that the scope of the invention is not limited to the above arrangement.

FIG. 5 shows a finally manufactured semiconductor device,
That is, FIG. 4 is an enlarged view of a part of the step (M) in FIG. In the figure, the wafer 1 is positioned at the position of the mesa-shaped bump 14.
The plane obtained by cutting 0 is schematically drawn. This figure clearly shows that the metal wiring 17 is arranged so as to extend from the position of the electrode pad 10a and cover the mesa bump 14. In other words, one end (region 41) of the metal wiring 17 is connected to the electrode pad 10a under the resin 18 constituting the package, and the other end (region 40) is
It is exposed on the surface of the resin 18 on the mesa bump 14. This wiring 1 substantially corresponding to the thickness of the resin 18
7, the surface of the semiconductor chip (wafer 10)
That is, when the surface of the silicon is
Move away from the surface of the printed wiring board made of R4 or the like. The stress generated due to the difference between the linear expansion coefficients of these materials in a temperature cycle test or the like depends on the distance between the silicon surface and the printed wiring board surface. I do. The magnitude of the displacement sufficient to secure the mounting reliability satisfying the various criteria is determined by the height of the mesa-type bump 14.
Those skilled in the art will understand that they can be formed easily and in a short time by the lithography techniques shown in (C) to (E).

Further, in the present invention, the elasticity of the resinous mesa-shaped bumps 14 sandwiched between the wafer 10 and the solder balls 19 (and thus the printed wiring board) preferably functions to relieve the stress. Will be apparent to those skilled in the art. In order to obtain the same mounting reliability as a semiconductor device using a conventional metal support, the semiconductor device according to the present invention is:
Due to the difference in the elastic modulus, a bump having a lower height is sufficient, and the thickness of the entire package can be reduced. In the embodiment, the mesa-shaped bump 14 is a polyimide resin, and has an elastic modulus of 3.5 GPa.
It has an elastic modulus about 1/31 times that of a conventional column made of copper (elastic modulus: 110 GPa). However, in the present invention, the mesa bump is formed of another member having the same elastic modulus as the above, for example, polyetheramideimide (elastic modulus:
3.0 GPa). In one embodiment, the thickness H1 of the layer 11 is about 10 μm, the height H2 of the mesa bump 14 is about 30 μm, the thickness H3 of the metal wiring 17 is about 20 μm, the lower diameter D1 is about 400 μm, and the upper diameter is about 400 μm. D2 is about 300 μm, solder ball diameter D3 is about 3
00 μm. According to the production method according to the present invention,
There is no manufacturing problem in setting the height of the mesa bump to 200 μm or more.

FIG. 6 shows two examples of the structure of the package resin 18 around the mesa-shaped bump 14. Same figure
In the structure (A), the boundary of the package resin 18 reaches the plane area 60 of the metal wiring 17 at the top of the mesa bump 14. The solder ball 19 is fixed in a circular area surrounded by the package resin 18 in the plane area 60.
In the structure shown in FIG. 2B, the boundary of the package resin 18 is located in the inclined area 61 of the metal wiring 17 on the inclined surface of the mesa bump 14. That is, in this structure, the upper portion of the mesa-type metal wiring is exposed outside the package, and a circular groove 62 is formed around the periphery. At the time when the package resin 18 is etched in the above step (K), the boundary is perpendicular to the surface of the wafer, but in the subsequent curing step, the package resin 18 shrinks, and the groove 62 is shown in FIG. As shown in FIG.
When the solder balls 19 transferred to the plane region 60 are melted by reflow, the lower region flows into the grooves 62, whereby the solder balls 19 with respect to the metal wiring 17 are formed.
Will be firmly fixed.

The embodiment of the present invention has been described with reference to the drawings. Obviously, the scope of application of the present invention is not limited to the items shown in the above embodiment. In the embodiment, the external connection terminal is formed by transferring a solder ball formed in another process. However,
The external connection terminals could be mounted by other methods, for example, by forming stud bumps directly on the exposed wiring area.

Further, according to the present invention, the mesa-type bumps 1 are directly formed on the lands of the printed circuit board without using the solder balls.
4 to join the wiring region 17a. In this case, preferably, the region 17a is configured to protrude from the surface of the package resin 18.

[0031]

As described above, according to the present invention, in a semiconductor device called a wafer level CSP, it is possible to improve the productivity and to reduce the thickness of the device while guaranteeing the mounting reliability. Become.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the semiconductor device according to one embodiment of the present invention.

FIG. 3 is a view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a plan view of a part of the wafer in a step (I) of FIG. 2;

FIG. 5 is an enlarged cross-sectional view showing a part of a finally manufactured semiconductor device.

FIG. 6 is a cross-sectional view showing an example of the structure of a package resin around a mesa bump.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Wafer 10a Electrode pad 11 Polyimide resin layer 12 Polyimide resin layer 13 Post 14 Mesa bump 15 Barrier metal 16 Resist 17 Metal wiring 17a Wiring area on bump 18 Package resin 19 Solder ball 31 Dicing saw 32 Semiconductor device

Claims (8)

[Claims] A semiconductor substrate having an electric circuit formed on a main surface thereof; an electrode pad formed on the semiconductor substrate; and a electrode formed on the semiconductor substrate at a position close to the electrode pad. An insulating support; wiring formed on the semiconductor substrate from the electrode pad to the top of the insulating support; an insulating resin formed on the semiconductor substrate; and an insulating resin formed on the insulating resin. A semiconductor device comprising: an opening formed to expose a wiring at a top of a support; and an external connection terminal formed at the opening to be connected to a wiring on the top of the insulating support. 2. The semiconductor device according to claim 1, wherein said insulating pillar is a polyimide resin. 3. The semiconductor device according to claim 1, wherein the insulating pillar has a mesa shape. 4. The height of the insulating pillar is 30 μm to 60 μm.
4. The semiconductor device according to claim 1, wherein the semiconductor device is in a range of μm. 5. The semiconductor device according to claim 1, wherein said external connection terminal is a solder ball. 6. A step of forming an electrode pad on a semiconductor substrate having an electric circuit formed on a main surface thereof; and a step of forming an insulating pillar at a position on the semiconductor substrate close to the electrode pad. Forming a wiring from the electrode pad to the top of the insulating pillar on the semiconductor substrate; and forming an insulating resin on the semiconductor substrate so that the wiring at the top of the insulating pillar is exposed. Forming an external connection terminal on the wiring at the top of the insulating pillar. 7. The step of forming the insulating pillar includes the step of forming an insulating resin film on the semiconductor substrate, and the step of etching the insulating resin film into a predetermined pattern.
7. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming the insulating pillar by curing the predetermined pattern. 8. The step of forming the insulating resin so that the wiring on the top of the insulating support is exposed includes the steps of forming an insulating resin layer on the semiconductor substrate and forming the insulating resin on the top of the insulating support. Removing the insulating resin layer on the wiring to expose the wiring on the top of the insulating pillar.
Or a method of manufacturing a semiconductor device according to item 7.