JP2001190061A - Switching element driving circuit for inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching element driving circuit for inverter which can abruptly turn off the main switching elements of an inverter. SOLUTION: When IGBT1-IGBT4 installed to the inverter as main switching elements are turned off, the driving circuit 11 forcibly discharges electric charges to holding capacitors C11-C14 and related to the turning-on bias voltages for the gates of the IGBT1-IGBT4, by impressing forced discharge voltages which are reserved in direction to the turning-on bias voltage upon the capacitors C11-C14. Consequently, the main switching elements IGBT1-IGBT4 can be turned off abruptly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for driving a main switching element group of an inverter constituted by voltage-driven semiconductor switching elements.

[0002]

2. Description of the Related Art In general, in an inverter of a high voltage output,
A drive circuit for driving the main switch group is provided with a pulse transformer, and a control center is disposed on the primary side to protect the main switch group. In addition, for example, between the gate and the emitter of the IGBT constituting the main switch group, a gate voltage is held between the gate and the emitter. A capacitor is provided, and the capacitor is charged and discharged by a drive circuit to drive the main switch group. Then, in the conventional drive circuit, to turn on the main switch group, the switch circuit connected to the control power supply is turned on and off,
In order to hold the on-bias voltage to the main switch with a capacitor and turn off the main switch group, a short circuit connected to the capacitor was driven to remove the on-bias voltage to the main switch.

[0003]

However, in the conventional drive circuit for an inverter of a high-voltage specification, as described above, when the main switch group is turned off, a voltage between both terminals of the capacitor for holding the gate voltage is reduced. Since the short-circuit configuration was adopted, the discharge is performed only by the potential difference caused by the electric charge charged in the capacitor, it takes time until the discharge is completed, and the main switch group is rapidly turned off. Could not.

For this reason, in the conventional drive circuit, the two main switch groups cannot be alternately switched on and off at a high cycle. When a rectangular voltage wave is alternately output from the inverter, a rectangular wave is output. It is difficult to shorten the pause time during which the output becomes 0 V while the direction changes, and it was not possible to stably light a discharge lamp or the like.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a switching element drive circuit of an inverter capable of rapidly turning off a main switching element provided in the inverter.

[0006]

In order to achieve the above object, a switching element drive circuit for an inverter according to the first aspect of the present invention comprises a main part of an inverter composed of a voltage-driven semiconductor switching element. A drive circuit for driving a switching element group, in which a control pulse in an opposite direction is alternately applied to a primary coil to hold a secondary voltage of a secondary coil and a gate voltage of a main switching element. In the capacitor, the secondary coil is composed of a pair of secondary coils provided for each main switching element, and these secondary coils are connected in parallel to the holding capacitor, and one of the secondary coils and the holding capacitor are connected. And a discharging switch is provided between the other secondary coil and the holding capacitor. The charging switch is always off, and is turned on by the secondary-side pulse voltage accompanying the one-way control pulse to the primary coil. Based on the pulse voltage, both terminals of the holding capacitor are turned off. In the meantime, it turns off after the on-bias voltage to each main switching element is generated, and the discharge switch is always off, and the secondary side pulse voltage accompanying the reverse control pulse to the primary coil is turned on. Then, based on the pulse voltage, a forced discharge voltage in a direction opposite to the on-bias voltage is applied to the holding capacitor to remove the on-bias voltage.

According to the present invention, the charging switch comprises:
It turns on when a unidirectional control pulse is applied to the primary coil, and turns off when an on-bias voltage to the main switching element is generated between the two terminals of the holding capacitor by the secondary pulse voltage. As a result, the main switching element is kept in the ON state.

While no control pulse is applied to the primary coil, both the charging and discharging switches are turned off, the holding capacitor is disconnected from both the secondary coils, and the main switching element is turned on. Is held.

Furthermore, the discharge switch is turned on when a control pulse in the reverse direction is applied to the primary coil, and the forced discharge voltage in the direction opposite to the on-bias voltage is applied to the holding voltage by the pulse voltage on the secondary side. Applied to the capacitor. This allows
A large voltage, which is the sum of the on-bias voltage and the forcible discharge voltage, is generated between both terminals of the capacitor, and the charge related to the on-bias voltage that has been steeply charged in the holding capacitor is discharged, and the on-bias voltage is removed. Is done.

As described above, according to the present invention, when the main switching element is turned off, the holding capacitor includes:
By applying a forced discharge voltage in the opposite direction to the on-bias voltage to the main switching element, the charge related to the on-bias voltage charged in the holding capacitor is forcibly discharged, and the main switching element provided in the inverter is provided. Can be turned off steeply.

Further, specifically, in the switching element drive circuit according to the present invention, the charging switch is configured such that the first diode is turned on by a secondary-side pulse voltage accompanying a one-way control pulse to the primary-side coil. And a first reverse bias power supply for turning off the first FET when there is no pulse voltage.
A second diode and a second FE which are both turned on by a secondary pulse voltage accompanying a reverse control pulse to the primary coil;
T, the second FET can be provided with a second reverse bias power supply for causing no pulse voltage.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows the entire configuration of the inverter circuit according to the present embodiment. Each of the four main switching elements arranged in the H-bridge circuit includes, for example, IGBTs 1 to 4 as voltage-driven semiconductor switching elements. These IGBT groups are combined in a switching element drive circuit 11 (hereinafter simply referred to as “drive circuit 11”) to which the present invention is applied.
Driven.

The drive circuit 11 is shown in FIG. 2 in its entirety. One pair of IGBTs 1 and 4, which are turned on and off at the same timing, and a pair of pulse transformers corresponding to the other pair of IGBTs 2 and 3, respectively. PT1, PT2,
On the primary side of each of the pulse transformers PT1 and PT2, a driving circuit DR1 for driving the primary coils L11 and L12 is provided.
DR2 is provided.

The drive circuit DR1 shown on the upper side in FIG.
Are four sets of diodes D1 to D4 and switches S1 to S
4 constitute an H-bridge circuit, and these switches S
1 to S4 turn on / off in response to a control signal from the pulse logic circuit PLC1, and alternately apply the voltage of the control DC power supply E1 to the primary coil L11 of one of the pulse transformers PT1 as a reverse control pulse. The drive circuit DR2 shown on the lower side of the figure also has the same structure as the upper circuit DR1, and has a different timing from the upper drive circuit DR1.
By operating the diodes D5 to D8 and the switches S5 to S8, the voltage of the control DC power supply E1 is alternately applied to the primary coil L11 of the other pulse transformer PT2 as a reverse control pulse (see FIG. 3).

On the secondary side of each of the pulse transformers PT1 and PT2, a pair of secondary coils L2 for each IGBT is provided.
1, L22, and these secondary coils L21, L2
2 is connected in parallel to each of the holding capacitors C11 to C14 that hold the gate voltage of each IGBT. here,
The holding capacitors C11 to C14 may use parasitic capacitors between the gate and the emitter of the IGBT,
The IGBT may be constituted by an external capacitor connected between the gate terminal and the emitter terminal. The two secondary coils L21 and L22 are wound, for example, in the same number of turns to obtain the same secondary voltage. Further, a current limiting resistor R11 is provided between a common connection point of the two secondary coils L21 and L22 and the voltage holding capacitors C11 to C14.
To R14.

A circuit for connecting the IGBT 1 shown in the upper part of FIG. 2 to the pair of secondary coils L21 and L22 is shown in FIG. In FIG. 3, a diode D11 is connected between the upper secondary coil L21 (hereinafter, appropriately referred to as a "first coil L21") and the holding capacitor C11 with its cathode disposed on the holding capacitor C11 side. And one end of the first coil L21 (marked side)
Is turned on when a voltage E11 having a positive value is generated. The diode D11 and the first coil L2
1, a P-channel MOS type FET 11 (hereinafter referred to as “Q11”) has a drain connected to the diode D1.
1 side, the source is one end side of the first coil L21 (marked side),
The gate is arranged and connected to the other end of the first coil L21. Further, a reverse bias voltage for turning off Q11 is connected between Q11 and the first coil L21.
, A reverse bias power supply E51 applied between the gate and the source is provided.

On the other hand, a secondary coil L22 shown on the lower side in FIG. 1 (hereinafter referred to as "second coil L22" as appropriate)
And a holding capacitor C11, a diode D1
2 is connected so that the anode is disposed on the holding capacitor C11 side, and is turned on when a voltage E13 in which the other end of the second coil L22 (the side opposite to the mark) is positive is generated. is there. An N-channel MOS MFET 1 is provided between the diode D12 and the second coil L22.
2 (hereinafter referred to as “Q12”), the drain is connected to the diode D12, the source is connected to one end (marked side) of the second coil L22, and the gate terminal is connected to the other end of the second coil L22. I have. Further, Q12 and the second coil L22
A reverse bias power supply E52 for applying a reverse bias voltage for turning off Q12 between the gate and source of Q12 is provided between the power supply E52 and the power supply E52.

In FIG. 2, the IG shown second from the top
The circuit that connects the BT4 and each pair of the secondary coils L21 and L22 includes the above-described IGBT1 and the secondary coils L21 and L22.
22, a diode (D11, D12) and an FET (Q11,
Q12) is turned on and off at the same timing.

In FIG. 2, the circuit for connecting the IGBT3 and IGBT2 corresponding to the lower pulse transformer PT2 and each of the pair of secondary coils L21 and L22 is also the same as the IGBT1 and IG corresponding to the upper pulse transformer PT1.
It has the same configuration as the circuit that connects the BT4 and each pair of secondary coils L21, L22, and has a pair of diodes D15, 1
6, a pair of FETs (Q15, Q16), and a pair of reverse bias power supplies E71, E72. Then, the lower pulse transformer PT2 operates at a timing different from that of the upper transformer PT1, and based on the secondary voltage generated thereby, the diodes D15 and D16 of each circuit and the FETs (Q15 and Q16) are connected. Operate on / off.

The reverse bias power supplies E51 and E5
2, E71 and E72 are connected to the secondary coils L21. L
It is set smaller than the secondary voltage induced at 22. The reverse bias power supplies E51 and E52 are, for example,
4A, a plurality of diodes D90 connected in series and a capacitor C91 are connected in parallel, or as shown in FIG. 4B, a zener diode ZD92 and a capacitor C93 are connected. Can be connected in parallel.

Next, the operation of this embodiment having the above configuration will be described. In the drive circuit 11 of the present embodiment, the drive circuits DR1 and DR2 use the pulse transformers PT1 and PT2.
The IGBTs are turned on and off by applying control pulses alternately in opposite directions to the two primary coils L11 and L12. This will be described in detail below with reference to the time chart of FIG. 5 for the IGBT 1 shown in FIG.

In the drive circuit DR1 provided in one of the pulse transformers PT1 corresponding to the IGBT1, each switch S1
To S4 (hereinafter, simply referred to as “S1 to S4”) receive control signals from the pulse logic circuit PLC1, and S1 and S3
Is always on, and S2 and S4 are always off. Then, the operation of turning off S1 and turning on S2 for a short time Ton, and the operation of turning S1 on for a short time Ton
3 and the operation of turning on S4 are alternately repeated at intervals.

Here, the above Ton time (see FIG. 5) is obtained and set by the following equation. Ton time = (4 × Ae × N1 × B) / V1 V1: Voltage of DC power supply E1 for control Ae: Effective area of core of pulse transformer N1: Number of turns on primary side of pulse transformer B: Core of pulse transformer is saturated Magnetic flux density allowed

In a state where S1 and S3 are turned on and S2 and S4 are turned off, the first and second coils L2 on the secondary side are turned off.
1, L22, no induced electromotive force is generated, and each coil L2
1, Q provided between L22 and holding capacitor C11.
11 and Q12 are reverse bias power supplies E51 and E5, respectively.
2 is turned off by receiving a reverse bias voltage.

Then, the state is switched to a state where S3 is turned off and S4 is turned on, and when the state is maintained, the voltage of the control power supply E1 is applied to the primary coil L11 of the pulse transformer PT1 only during the maintained time Ton. Voltages E11 and E12 are generated when one end side (marked side) of the first and second coils L21 and L22 on the secondary side is positive.

Then, the voltage E generated in the first coil L21
11, the Q11 and the diode D11 become forward biased and turn on, and the current limiting resistor R11 and the holding capacitor C
E53 occurs between the 11 series circuits. Further, the voltage E12 generated in the second coil L22 acts as a bias voltage for turning off Q12, so that Q12 remains off.

The E53 charges the holding capacitor C11 through the current limiting resistor R11. The voltage EG1 related to the charge charged in the holding capacitor C11 is I
An on-bias voltage is applied to the gate of GBT1,
The IGBT 1 turns on.

Next, when S4 turns off and S3 returns to the on state, the primary coil L11 of the pulse transformer PT1 is turned on.
Enters the short-circuit mode by S1 and S3, the voltages E11 and E12 of both the secondary side coils L21 and L22 are all 0.
V. As a result, Q11 and Q12 receive the reverse bias voltage from the reverse bias power supplies E51 and E52, and return to the off state, and the two secondary coils L21 and L22 are turned off.
It is separated from the holding capacitor C11. Therefore, the charge charged in the holding capacitor C11 is kept held as it is, and the voltage EG1 between both terminals of the holding capacitor C11 is set as the on-bias voltage, and the IGBT1 is held in the on state.

Now, from the above state, S1 turns off and S2
Is switched to the ON state, and when the state is maintained for the time Ton, during that time, the voltage of the control power supply E1 is applied to the primary coil L11 of the pulse transformer PT1 in a direction opposite to the above operation. As a result, both the first and second
Voltages E11 and E12 are generated with the other ends of the two coils L21 and L22 (opposite the marks) being positive.

Then, since the voltage E11 generated in the first coil L21 becomes a bias voltage for turning off Q11, Q11 remains off. On the other hand, the voltage E12 generated in the second coil L22 becomes a bias voltage for turning on Q12, turning on Q12. As a result, the diode D11 becomes forward biased and turns on. A voltage E53 in the opposite direction to that described above is generated between the series circuit of the capacitors C11.

Then, based on the voltage E53, the voltage applied between the two terminals of the holding capacitor C11 becomes the forced discharge voltage according to the present invention, and the on-bias by the forced discharge voltage and the charge charged in the capacitor. The charge related to the on-bias voltage charged in the holding capacitor C11 is discharged by the large voltage including the voltage. As a result, the on-bias voltage is sharply removed,
Further, the storage capacitor C11 is charged to a negative potential. As a result, EG1 is in a reverse bias state with respect to the gate of IGBT1, and IGBT1 is turned off.

Next, when S2 is turned off and S1 returns to the original state of being turned on, the primary coil L11 of the pulse transformer PT1 again enters the short-circuit mode by S1 and S3, and the secondary side voltage E11, E12 all become 0V. As a result, both Q11 and Q12 receive the reverse bias voltage from the reverse bias power supplies E51 and E52, return to the off state, and the two secondary coils L21 and L22 are disconnected from the holding capacitor C11. Accordingly, the holding capacitor C11 is maintained while being charged with the reverse bias voltage for the gate of the IGBT1, and the IGBT1 is maintained in the off state.

In the same manner as the operation for driving the IBGT 1 described above, the drive circuit 11
4 is turned on and off at the same timing as the above IGBT 1, and IGBT 3 and IGBT 2 are connected to the IGBT 1.
On / off driving is performed at a timing of a phase difference of 180 degrees with respect to 1.

As described above, the drive circuit 1 of the present embodiment
According to the IGBTs 1 to 4,
Are turned off, the holding capacitors C11 to C1
By applying a forced discharge voltage in the direction opposite to the on-bias voltage to the gates of the IGBTs 1 to 4, the charge related to the on-bias voltage charged in the holding capacitors C11 to C14 is forcibly discharged. , IGBT1
To 4 can be turned off steeply. Therefore, according to the drive circuit 11, the IGBTs 1 and 4 and the IGBT
When switching between 3 and 2 alternately, the waiting time until the IGBT on one side is completely turned off can be set short, so that the pause time Ts of the alternating rectangular voltage wave output from the inverter (see FIG. 5) ) Can be shortened, and even a high-load discharge lamp can be stably lit.

<Second Embodiment> An inverter according to this embodiment is shown in FIG. 6 and includes a pair of drive circuits 40 having the same configuration as the drive circuit 11 of the first embodiment. , 40 are connected to four IGBTs 1 to 4 as in the first embodiment. A pair of IGs corresponding to the respective pulse transformers (not shown) provided in pairs in the respective drive circuits 40 are provided.
BT1, 4 (or IGBT2, 3) are connected in series,
The main switching elements SW1 to SW4 composed of the two IGBTs connected in series are connected in an H-bridge form to constitute a main circuit of the inverter. According to the present embodiment, the drive circuits 40, 40 can be operated in synchronization to drive a higher voltage inverter.

<Other Embodiments> The present invention is not limited to the above embodiments. For example, the following embodiments are also included in the technical scope of the present invention.
In addition to the following, various changes can be made without departing from the scope of the invention.

(1) In the first embodiment, the main switching element is composed of an IGBT, but if it is a voltage-controlled semiconductor switching element, for example, a MOS type F
It may be an ET, a junction FET, or the like.

(2) Drive circuit 1 of the first embodiment
1 drives the main switching element (IGBT) so as to output an alternating rectangular voltage wave from the inverter, but the output of the inverter may be PWM controlled or variable frequency controlled. Also in these cases, since the main switching elements are driven sharply, the output of the inverter can be accurately controlled.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an entire inverter according to a first embodiment;

FIG. 2 is a circuit diagram of the drive circuit.

FIG. 3 is a circuit diagram showing a part of the drive circuit.

FIG. 4 is a circuit diagram showing a configuration of a reverse bias power supply.

FIG. 5 is a time chart showing the operation of the drive circuit.

FIG. 6 is a circuit diagram showing a configuration of an entire inverter according to a second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Switching element drive circuit 13 ... Capacitor 40 ... Drive circuit C11 ... Holding capacitor D11, D15 ... Diode (first diode) D12, D16 ... Diode (second diode) E1 ... DC power supply for control E1 ... Power supply for control Voltage E51, E71: Reverse bias power supply (first reverse bias power supply) E52, E72: Reverse bias power supply (second reverse bias power supply) Q11, Q15: FET (first FET) Q12, Q16: FET (second FET) IGBT1 to IGBT4 (Main switching elements) L11, L12: Primary coil L21: First coil (one secondary coil) L22: Second coil (the other secondary coil) PT1, PT2: Pulse transformer

Claims (2)

[Claims] 1. A drive circuit for driving a main switching element group of an inverter constituted by a voltage-driven semiconductor switching element, wherein a control pulse in an opposite direction is alternately applied to a primary coil, and A secondary voltage of the side coil is provided to a holding capacitor that holds a gate voltage of the main switching element, wherein the secondary coil includes a pair of secondary coils provided for each of the main switching elements, and The secondary coils are connected in parallel to the holding capacitor, and a charge switch is provided between the one secondary coil and the holding capacitor, and the charging switch is connected between the other secondary coil and the holding capacitor. A discharge switch is provided in between, and the charge switch is always off, and a one-way control signal to the primary coil is provided. On at the secondary-side pulse voltage accompanying the pulse, and based on the pulse voltage, turn off after an on-bias voltage to each of the main switching elements is generated between both terminals of the holding capacitor, and Switch is always off, and is turned on by the secondary side pulse voltage accompanying the reverse control pulse to the primary side coil, and based on the pulse voltage, the reverse direction is opposite to the on-bias voltage. A switching element drive circuit for an inverter, wherein a forcible discharge voltage is applied to the holding capacitor to remove the on-bias voltage. 2. The charge switch comprises a first diode and a first FET that are both turned on by a secondary-side pulse voltage accompanying a one-way control pulse to the primary coil. A first reverse bias power supply that is turned off when there is no pulse voltage, and the discharge switch is turned on by a secondary pulse voltage accompanying a reverse control pulse to the primary coil. 2F and a second FET.
2. The switching element drive circuit for an inverter according to claim 1, further comprising a second reverse bias power supply for causing ET to occur when the pulse voltage is absent.