JP2001189435A - Stacked capacitor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a stacked capacitor, where a lower electrode is not required to be formed in the recess of high aspect ratio, and the lower electrode of required shape can be formed surely and stably. SOLUTION: This manufacturing method comprises a first step, in which a conductor layer 13 is formed on an interlayer insulating layer 10, second step in which a first mask layer 14 is formed on the conductor layer 13, third step in which a recess 15 is provided to the conductor layer 13 by etching using the first mask layer 14, fourth step in which a second mask layer 16 is formed in the recess 15, fifth step in which the first mask layer 14 is removed, and then a sidewall 17 is formed on the side wall of the second mask layer 16, sixth step in which the conductor layer 13 is etched using the side wall 17 and the second mask layer 16 as an etching mask for the formation of a bottomed cylindrical lower electrode 18, and the sidewall 17 and the second mask layer 16 are removed, and seventh process in which a dielectric film 20 is formed on the surface of the lower electrode 18 and an upper electrode 21 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a stacked capacitor in a dynamic random access memory (DRAM) and a method for manufacturing the same.

[0002]

2. Description of the Related Art A DRAM is composed of a plurality of memory cells including a MIS type semiconductor element (for example, MOSFET) for a switch and a memory capacitor. And
DRA with a capacity of several gigabytes at the academic level as a process driver in semiconductor devices
In recent years, for example, M has been announced. With this miniaturization, memory cells are being reduced in size, and the area occupied by memory capacitors is also being reduced.

The most important matter in a memory capacitor of a DRAM is to secure a required storage capacity of the memory capacitor in order to enhance the reliability of data (information) storage. The required amount of the storage capacitor is usually determined from the following viewpoint, and is usually about 20 to 40 pF. (1) Regardless of the DRAM generation, it must have sufficient resistance to soft errors due to alpha rays. (2) It is necessary to sufficiently cope with an increase in the total capacity and the total leak current of the bit lines as a result of an increase in the number of memory cells connected to the bit lines to reduce the chip area. (3) In spite of the fact that the threshold voltage _Vth cannot be reduced from the viewpoint of the leakage current of the MIS type semiconductor element for the switch, the power supply has been reduced, and the stored signal voltage tends to decrease accordingly.

[0004] Therefore, the memory capacitor has to secure a required storage capacity in spite of the occupied area being reduced as the memory cell is miniaturized.
To that end, various ideas have been devised.

Further, a logic circuit (also called a peripheral circuit)
When applied to a DRAM integrated logic integrated circuit in which a DRAM and a DRAM are mixed, a salicide (Self-Aligned Silicide) technology used for the logic circuit and a dual gate (Dual Gate, Dual Work Function Gate or
From the viewpoint of compatibility with a process having low heat resistance such as a technology (also referred to as a surface channel type CMOSFET), there is a strong demand for lowering the process temperature when fabricating a memory capacitor.

From the background described above, a memory capacitor based on an MIM (Metal-Insulator-Metal) structure which can be formed by a low-temperature process at 600 ° C. or less has been developed as a memory capacitor. In the memory capacitor having the MIM structure, attempts have been made to satisfy the demand for the memory capacitor by improving the material of the capacitor electrode (particularly, the electrode material forming the lower electrode) and the material of the capacitor dielectric film.
As a constituent material of the capacitor dielectric film, a metal oxide, for example, a high dielectric material such as Ta ₂ O ₅ , BST (barium strontium titanium oxide), or STO
Ferroelectric materials such as (strontium / titanium / oxide) have been developed. Particularly, as an electrode material constituting the lower electrode, a material which is not oxidized to become an insulator when heat treatment is performed in contact with the capacitor dielectric film, for example, W ₂ N having high oxidation resistance, Pt,
Materials that exhibit conductivity even when oxidized, such as Ru and Ir, have been developed.

Incidentally, the electrode material constituting the lower electrode is relatively difficult to process. Therefore, in general, the lower electrode is formed by etching using a hard mask as an etching mask and having many sputter components.

In general, a memory capacitor is formed on an interlayer insulating layer covering a switch MIS semiconductor element formed on a silicon semiconductor substrate, and a lower electrode is provided on one side of the MIS semiconductor element. They are electrically connected to the source / drain regions via contact plugs formed in the interlayer insulating layer. Usually, an insulating layer is formed on an interlayer insulating layer, a concave portion is provided in the insulating layer, and a lower electrode is formed in the concave portion. The top surface of the contact plug is exposed at the bottom of the recess. MO in high aspect ratio recess
Although a method of depositing the electrode material constituting the lower electrode by the CVD method is also being studied, there is a possibility that residual impurities due to the used source material may remain in the lower electrode,
There is a concern that the memory cells may be adversely affected. Therefore, although it is difficult from the viewpoint of coverage to deposit the electrode material constituting the lower electrode in the recess having a high aspect ratio by the sputtering method, it is inevitable to use the sputtering method at present.

[0009]

The present inventor has disclosed a means for solving such a problem in the formation of the lower electrode in Japanese Patent Application No. 9-51237 (Japanese Unexamined Patent Application Publication No. 10-25649).
No. 7). In this method, an electrode material film 20 which is continuous with the contact portion 7 and covers the contact portion 7 is formed on the interlayer insulating layer 3. Next, the upper part of the electrode material film 20 is etched to form the convex pattern 21 at a position substantially vertically above the contact part 7 on the upper part of the electrode material film 20. After that, a sidewall 22 is formed on the side wall of the convex pattern 21. Next, the electrode material film 20 is etched using the sidewall 22 as a mask,
A bottomed cylindrical lower electrode 23 is formed.

The method disclosed in this patent publication is an excellent method for forming the lower electrode without the necessity of depositing the electrode material constituting the lower electrode by sputtering in the concave portion having a high aspect ratio. is there. However, when the upper part of the electrode material film 20 is etched to form the convex pattern 21 as shown in a schematic partial end view of FIG. It becomes an upper constriction (taper shape). After the sidewalls 22 are formed on the side walls of the convex pattern 21 (see FIG. 21B), the sidewalls 22 are etched when the electrode material film 20 is etched using the sidewalls 22 as a mask.
The etching of the portion of the electrode material film 20 in contact with the electrode material film hardly progresses, and an acute portion may be formed in the electrode material film 20.
The structure obtained after removing the sidewalls 22 is shown in FIG.

As described above, when an acute angle portion is formed in the electrode material film 20, not only the coverage of the capacitor dielectric film becomes a problem, but also an electric field is concentrated on the acute angle portion, so that the characteristics and reliability of the memory capacitor are deteriorated. Problems arise. In addition, the height of the acute angle portion is not uniform, and the acute angle portion is not formed in a controlled state, so that the step of the capacitor becomes inconsistent and adversely affects the subsequent manufacturing process of the semiconductor device. There are cases.

Accordingly, a first object of the present invention is to provide a lower electrode having a desired shape stably without the necessity of depositing an electrode material constituting the lower electrode by sputtering in a recess having a high aspect ratio. It is an object of the present invention to provide a method of manufacturing a stack capacitor that can be reliably formed. Further, the second aspect of the present invention
It is an object of the present invention to provide a stacked capacitor having a lower electrode having a structure in which electric field concentration hardly occurs.

[0013]

According to a first aspect of the present invention, there is provided a method of manufacturing a stacked capacitor, comprising: a lower electrode; an upper electrode; and a lower electrode and an upper electrode. A MIS-type semiconductor element formed on the interlayer insulating layer covering the MIS-type semiconductor element formed in the semiconductor layer, and comprising a contact plug formed in the interlayer insulating layer. A method of manufacturing a stacked capacitor in which one of the source / drain regions and the lower electrode are electrically connected, comprising: (a) forming a conductor layer on an interlayer insulating layer; Forming one mask layer on the conductor layer;
(C) etching the conductor layer above the contact plug using the first mask layer as an etching mask;
(E) forming a second mask layer in the recess formed in the conductor layer, and (e) forming a second mask layer in the recess formed in the conductor layer. Removing the upper first mask layer, and then forming sidewalls on sidewalls of the second mask layer protruding from the conductor layer;
(F) The conductor layer is etched using the sidewall and the second mask layer as an etching mask to form a bottomed cylindrical lower electrode made of the conductor layer and connected to the contact plug. The method comprises the steps of: removing the wall and the second mask layer; and (g) forming a dielectric film on the surface of the lower electrode, and then forming an upper electrode covering the dielectric film.

A method for manufacturing a stacked capacitor according to a second aspect of the present invention for achieving the first object is as follows.
A lower electrode, an upper electrode, and a dielectric film sandwiched between the lower electrode and the upper electrode;
Formed on an interlayer insulating layer covering the IS type semiconductor element,
M via a contact plug formed in the interlayer insulating layer.
A method for manufacturing a stack capacitor in which one source / drain region and a lower electrode constituting an IS type semiconductor element are electrically connected, the method comprising: (a) forming a conductor layer on an interlayer insulating layer; B) a step of forming a patterned first mask layer on the conductor layer, and (c) etching the conductor layer above the contact plug using the first mask layer as an etching mask to form a bottom portion. Forming a recess in which the conductor layer is left in the conductor layer, and then retreating the side wall of the first mask layer on the conductor layer; and (d) the inside of the recess formed in the conductor layer and the conductor. Forming a second mask layer in a region surrounded by sidewalls of the first mask layer on the layer; (e) removing the first mask layer on the conductor layer; Conduction using the second mask layer as an etching mask The layers were etched consists conductive layer, after forming the bottomed cylindrical lower electrode connected to the contact plug, and removing the second mask layer,
(G) forming a dielectric film on the surface of the lower electrode, and then forming an upper electrode covering the dielectric film.

A method for manufacturing a stacked capacitor according to a third aspect of the present invention for achieving the above first object is as follows.
A lower electrode, an upper electrode, and a dielectric film sandwiched between the lower electrode and the upper electrode;
Formed on an interlayer insulating layer covering the IS type semiconductor element,
M via a contact plug formed in the interlayer insulating layer.
A method for manufacturing a stack capacitor in which one source / drain region and a lower electrode constituting an IS type semiconductor element are electrically connected, the method comprising: (a) forming a conductor layer on an interlayer insulating layer; (B) a step of forming a patterned first mask layer on the conductor layer; (c) a step of forming a second mask layer in a side wall shape on a side wall of the first mask layer; A) a step of etching a part of the conductor layer using the first mask layer and the second mask layer as an etching mask; (e) a step of removing the first mask layer; Etching the conductive layer above the contact plug using the second mask layer as an etching mask to form a bottomed cylindrical lower electrode composed of the conductive layer and connected to the contact plug; (G) Lower power After forming the dielectric film on the surface of, characterized in that it comprises the step, of forming an upper electrode which covers the dielectric film.

In the method for manufacturing a stacked capacitor according to a third aspect of the present invention, in step (b), a plurality of patterned annular first mask layers are formed on a conductor layer; In the step (c), if the second mask layer is formed in a side wall shape on each side wall of the annular first mask layer, a lower electrode having a multi-cylinder structure can be finally formed. Alternatively, in the step (b), after the patterned first mask layer is formed on the conductor layer, in the step (c), the side wall of the first mask layer is provided with a side wall of the second mask layer. In addition, a sidewall-shaped first mask layer is formed on the sidewall of the sidewall-shaped second mask layer, and the sidewall-shaped second mask layer is formed on the sidewall of the sidewall-shaped first mask layer. The lower electrode having a multi-cylinder structure can also be formed by repeating the step of forming a mask layer of the above, and finally forming the outermost side as the second mask layer having a sidewall shape.

A method of manufacturing a stacked capacitor according to a fourth aspect of the present invention for achieving the first object is as follows.
A lower electrode, an upper electrode, and a dielectric film sandwiched between the lower electrode and the upper electrode;
Formed on an interlayer insulating layer covering the IS type semiconductor element,
M via a contact plug formed in the interlayer insulating layer.
A method for manufacturing a stack capacitor in which one source / drain region and a lower electrode constituting an IS type semiconductor element are electrically connected, the method comprising: (a) forming a conductor layer on an interlayer insulating layer; (B) a step of forming a patterned first mask layer on the conductor layer; (c) a step of forming a second mask layer in a side wall shape on a side wall of the first mask layer; A) forming a third mask layer on the exposed conductor layer; e) removing the first mask layer; and f) forming the second mask layer and the third mask layer. A step of etching a part of the conductor layer using the etching mask; (g) a step of removing the third mask layer; and (h) using the remaining second mask layer as an etching mask. Etch the conductive layer above the contact plug A step of forming a bottomed cylindrical lower electrode made of a conductor layer and connected to the contact plug; and (iii) forming a dielectric film on the surface of the lower electrode and then covering the dielectric film with the upper electrode. Forming a step.

In the method for manufacturing a stacked capacitor according to a fourth aspect of the present invention, in the step (b), after the patterned first mask layer is formed on the conductor layer, the step (c) Forming a second mask layer in a side wall shape on a side wall of the first mask layer;
Forming a side wall-shaped third mask layer on a side wall of the side wall-shaped second mask layer, and forming a side wall-shaped second mask layer on a side wall of the side wall-shaped third mask layer By repeating such steps, a lower electrode having a multi-cylinder structure can be formed.

According to a second aspect of the present invention, there is provided a stacked capacitor including a lower electrode, an upper electrode, and a dielectric film sandwiched between the lower electrode and the upper electrode. Is formed on an interlayer insulating layer covering the MIS type semiconductor device, and one of the source / drain regions constituting the MIS type semiconductor device is electrically connected to the lower electrode via a contact plug formed in the interlayer insulating layer. Wherein the lower electrode has a cylindrical shape with a bottom, and a mask material layer exists between the upper end of the lower electrode and the dielectric film.

For example, the third embodiment or the fourth embodiment of the present invention
When the stack capacitor of the present invention is manufactured by the method for manufacturing a stack capacitor according to the aspect of the present invention, the mask material layer present between the upper end of the lower electrode and the dielectric film in the stack capacitor of the present invention includes Corresponds to a layer.

In the method for manufacturing a stacked capacitor according to the first to fourth aspects of the present invention, or in the stacked capacitor of the present invention, the stacked capacitor preferably has a cylindrical shape. In addition, the first aspect of the present invention
In the method for manufacturing a stacked capacitor according to the first to fourth aspects, it is preferable that an etching stopper film is formed between the interlayer insulating layer and the conductor layer before the step (a). By forming the etching stopper film on the interlayer insulating layer, it is possible to reliably prevent the interlayer insulating layer from being damaged when the sidewalls and the second mask layer are removed. The material forming the etching stopper film preferably has an etching selectivity between the material forming the sidewalls and the material forming the second mask layer, and examples thereof include silicon nitride (SiN).

In the method of manufacturing a stacked capacitor according to the first aspect of the present invention, the material forming the first mask layer (hard mask material) and the material forming the second mask layer (hard mask material) Between the material constituting the second mask layer and the material constituting the side wall, it is preferable that there is an etching selectivity. Or a conductive material. As a combination of a material forming the first mask layer / a material forming the second mask layer / a material forming the sidewall, PSG (PhosphoSicicate Glass) / NSG (N
on-doped Silicate Glass) / NSG, NSG / PSG
/ PSG combination can be exemplified.

Further, in the method for manufacturing a stacked capacitor according to the second aspect of the present invention, the material forming the first mask layer (hard mask material) and the second mask layer (hard mask material) are formed. It is preferable that there is an etching selectivity between the material and the material, and as long as this condition is satisfied, it does not matter essentially whether the material is an insulating material or a conductive material. Material constituting first mask layer / Second mask layer
PSG / N as a combination of materials constituting the mask layer of
SG and NSG / PSG can be exemplified.

Further, in the method of manufacturing a stacked capacitor according to the third aspect of the present invention, the material forming the first mask layer (hard mask material) and the second mask layer (hard mask material) are formed. It is preferable that there is an etching selectivity between the material and the material to be formed, and as long as this condition is satisfied, it does not matter essentially whether the material is an insulating material or a conductive material. Material for forming first mask layer /
As the combination of the materials constituting the second mask layer, specifically, SiO ₂ / SiN, PSG / SiO ₂ , SiO ₂ /
Examples of combinations of Si, carbon / SiO ₂ , and carbon / SiN can be given.

Further, in the method for manufacturing a stacked capacitor according to the fourth aspect of the present invention, the material forming the first mask layer (hard mask material) and the material forming the second mask layer (hard mask) There is an etching selectivity between the material constituting the third mask layer and the material constituting the third mask layer (hard mask material), and the material constituting the second mask layer (hard mask material) and the third mask layer It is preferable that there is an etching selectivity between the material constituting the material (hard mask material) and the material is not limited to an insulating material or a conductive material as long as this condition is satisfied. As a combination of a material forming the first mask layer / a material forming the second mask layer / a material forming the third mask layer, SOG (Spin On Glass) / SiN / S
iO ₂ , carbon / SiO ₂ / SiN, SiO ₂ / SiN
/ SiO ₂ .

Further, in the method for manufacturing a stacked capacitor according to various aspects of the present invention, the first mask layer,
The material constituting the second mask layer, the third mask layer, and the sidewall is, for example, basically, silicon oxide (S
consisted iO _2), by changing the etching rate by changing the amount of impurities contained in the silicon oxide, it is possible to make the etching selection ratio with the appropriate value. Instead of PSG, BPSG (Boro-Phospho
Sicicate Glass), BSG, AsSG, PbSG, Sb
SG or a carbon-based material can be used, and a carbon-based material can be used instead of NSG.

In the method for manufacturing the stacked capacitor according to the first to fourth aspects of the present invention, or the stacked capacitor of the present invention (hereinafter, these may be collectively simply referred to as the present invention). As a semiconductor layer, a silicon semiconductor substrate, a substrate on which silicon or Si-Ge mixed crystal is epitaxially grown on spinel, a substrate on which sapphire is epitaxially grown with silicon or Si-Ge mixed crystal, and a polycrystalline silicon on an insulating film. A melted and recrystallized substrate can be exemplified. As the silicon semiconductor substrate, an n-type silicon semiconductor substrate doped with an n-type impurity or a p-type silicon semiconductor substrate doped with a p-type impurity can be used.

Further, as a semiconductor layer, SOI (Semico)
nductor On Insulator) substrate can also be used. S
As a method of manufacturing an OI substrate, (1) After bonding a semiconductor substrate and a support substrate via an insulating layer, the semiconductor substrate is ground and polished from the back surface, so that a support made of the support substrate, an insulating layer, grinding,
A substrate bonding method for obtaining a semiconductor layer composed of a polished semiconductor substrate. (2) After an insulating layer is formed on the semiconductor substrate, hydrogen ions are ion-implanted into the semiconductor substrate to form a peeling layer inside the semiconductor substrate. The semiconductor substrate and the supporting substrate are attached to each other with an insulating layer interposed therebetween, and then the semiconductor substrate is separated (cleaved) from the separation layer by performing a heat treatment, and the remaining semiconductor substrate is ground and polished from the back surface to thereby form the supporting substrate. (3) Obtaining a semiconductor layer composed of a support, an insulating layer, and a semiconductor substrate after grinding and polishing. (3) Oxygen ions are implanted into the semiconductor substrate, and then heat treatment is performed. Forming an insulating layer inside a semiconductor substrate, a support formed of part of the semiconductor substrate below the insulating layer, and a semiconductor layer formed of part of the semiconductor substrate on the insulating layer, Re can each SIMOX (Separation b
y IMplanted OXygen) method (4) A single-crystal semiconductor layer is formed in a gas phase or a solid phase on an insulating layer formed on a semiconductor substrate corresponding to a support, whereby a support made of a semiconductor substrate and an insulating layer are formed. And (5) forming an insulating layer by partially making the surface of the semiconductor substrate porous by anodic oxidation, thereby forming a portion of the semiconductor substrate below the insulating layer. And a method for obtaining a semiconductor layer comprising a part of a semiconductor substrate on an insulating layer.

The gate electrode has, for example, a polysilicon layer containing impurities, a polycide structure having a two-layer structure of a polysilicon layer containing impurities and a silicide layer, and a two-layer structure of a polysilicon layer containing impurities and a metal layer. It can be composed of a polymetal structure and can be formed by a known method. The source / drain region and the channel formation region may have a known configuration, and can be formed by a known method.

As materials for forming the interlayer insulating layer, silicon oxide (SiO ₂ ), SOG (SpinOn Glass), PS
G, BPSG, BSG, AsSG, PbSG, SbS
G, NSG, LTO (Low Temperature Oxide, low temperature C
VD-SiO ₂ ), SiN, SiON, and a relative dielectric constant of 3.
An organic polymer material such as a low dielectric constant insulating material (e.g., polyaryl ether, cycloperfluorocarbon polymer, benzocyclobutene) of 5 or less, polyimide, or a laminate of these materials can be given.

As a material for forming the contact plug,
Examples include polysilicon containing impurities, various metals, metal compounds, and alloys (these are collectively referred to as a contact plug material for convenience). The contact plug is formed by forming an opening in the interlayer insulating layer above the source / drain region and forming a contact plug material layer made of a contact plug material on the interlayer insulating layer including the inside of the opening by sputtering or CVD. It can be formed by removing the contact plug material layer on the interlayer insulating layer by a chemical / mechanical polishing method (CMP method) or an etch back method. Alternatively, the contact plug can be formed based on the following method. That is, an interlayer insulating layer is formed on a semiconductor layer by a CVD method, and after a planarization process of the interlayer insulating layer is performed by a CMP method or the like, a hard mask layer made of polysilicon is formed on the entire surface by a CVD method. .
Thereafter, based on the lithography technique and the dry etching technique, openings are formed in the hard mask layer and the interlayer insulating layer. Next, a polysilicon layer is formed on the hard mask layer including the inside of the opening, and the polysilicon layer is etched back to form an opening diameter reducing mask in the opening. Then, using the hard mask layer and the opening diameter reducing mask as etching masks, an opening reaching the source / drain region is formed in the interlayer insulating layer based on a dry etching technique. After that, a contact plug material layer is deposited on the entire surface including the inside of the opening, and the contact plug material layer, the hard mask layer, and the opening diameter reduction mask are removed by an etch-back method or a CMP method. Complete the embedded contact plug.

In the present invention, as a material constituting the lower electrode or the conductor layer, tungsten (W), W ₂ N having high oxidation resistance, a laminated structure of Pt, Pd, Pt / Ti, and a laminated structure of Pt / Ta are used. structure, laminated structure of _{Pt / Ti / Ta, La 0.5} Sr 0.5 CoO 3 (LSCO), Pt / LS
A layered structure of CO, YBa ₂ Cu ₃ O ₇ , a material exhibiting conductivity even when oxidized, for example, Ru, Ir, or Ru
Metal oxides such as O ₂ and IrO ₂ , a RuO ₂ / Ru laminated structure, an IrO ₂ / Ir laminated structure, and polysilicon containing impurities can be given. In the laminated structure, the material described after “/” forms the contact plug side. The formation of the conductor layer can be performed by a sputtering method.

As a material forming the upper electrode, T
iN, tungsten (W), platinum (Pt), W ₂ N, R
u, RuO ₂ , and the materials mentioned as various materials constituting the lower electrode can be exemplified. The upper electrode may also serve as a plate line, or a plate line may be provided separately from the upper electrode.

As a material for forming the dielectric film, a metal oxide, for example, a high dielectric material such as Ta ₂ O ₅ can be used. Alternatively, lead zirconate titanate [PZT, Pb (BZ) is a solid solution of BST (barium strontium titanium oxide), STO (strontium titanium oxide), PbTiO ₃ , and PbZrO ₃ and PbTiO ₃ having a perovskite structure. Z
r _1-y , Ti _y ) O ₃ (where 0 <y <1)], PLZT which is a metal oxide obtained by adding La to PZT, or P
PZT-based compounds such as PNZT, which is a metal oxide obtained by adding Nb to ZT, and a Bi-based layered structure perovskite-type ferroelectric material can be used. The Bi-based layered structure perovskite type ferroelectric material belongs to a so-called nonstoichiometric compound, and has tolerance to a composition deviation at both sites of a metal element and an anion (O or the like) element. Also, it is not uncommon for the composition to exhibit optimal electrical characteristics at a position slightly deviating from the stoichiometric composition. The Bi-based layered structure perovskite-type ferroelectric material has, for example, the general formula (Bi ₂ O ₂ ) ²⁺ (A _m-1
B _m O _{3m +} 1) can be represented by ^2. Where "A"
Represents one kind of metal selected from the group consisting of metals such as Bi, Pb, Ba, Sr, Ca, Na, K, and Cd, and “B” represents Ti, Nb, Ta, W, and Mo. , Fe,
One type selected from the group consisting of Co and Cr, or a combination of a plurality of types at an arbitrary ratio. Also, m
Is an integer of 1 or more. Alternatively, the Bi-based layered structure perovskite type ferroelectric material is represented by Bi _x (Sr, Ca, Ba) _Y (Ta _Z , Nb _{1 -Z} ) ₂ O _d (1) (where 1.7 ≦ X ≦ 2.5, 0.6 ≦ Y ≦ 1.2, 0
≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) as a main crystal phase.
Note that “(Sr, Ca, Ba)” represents Sr, Ca, and Ba.
Means one element selected from the group consisting of Alternatively, ferroelectric _{materials, Bi X Sr Y Ta 2 O} d (2) ( where, 1.7 ≦ X ≦ 2.5,0.6 ≦ Y ≦ 1.2,
(8.0 ≦ d ≦ 10.0) as a main crystal phase. In these cases, it is more preferable that the crystal phase represented by the formula (1) or (2) be contained at 85% or more as a main crystal phase.
The ferroelectric material containing the crystal phase represented by the formula (1) or (2) as a main crystal phase includes Bi oxide,
Oxides of Ta and Nb, and composite oxides of Bi, Ta and Nb may be slightly contained. Here, if the composition of the ferroelectric material represented by the formula (1) is represented by a stoichiometric composition, for example, Bi ₂ SrTa ₂ O ₉ , Bi ₂ SrNb ₂ O ₉ ,
Bi ₂ BaTa ₂ O ₉ and Bi ₂ SrTaNbO ₉ can be exemplified. Alternatively, as a ferroelectric material, Bi
₄ SrTi ₄ O ₁₅ , Bi ₄ Ti ₃ O ₁₂ , Bi ₂ PbTa ₂ O ₉
And the like, but also in these cases, the ratio of each metal element can be changed to such an extent that the crystal structure does not change.

In the method for manufacturing a stacked capacitor according to the first or second aspect of the present invention, a flat conductor layer is formed, and a recess having the conductor layer left at the bottom is formed in the conductor layer. After that, the conductor layer is etched to form a bottomed cylindrical lower electrode. Therefore, in the method for manufacturing a stacked capacitor according to the third or fourth aspect of the present invention, the second mask is formed. Using the layer as an etching mask, the conductive layer above the contact plug is etched to form a bottomed cylindrical lower electrode composed of the conductive layer and connected to the contact plug, which is different from the prior art. It is not necessary to deposit the electrode material constituting the lower electrode by sputtering in the concave portion having a high aspect ratio. For example, a conductor layer may be formed on a flat interlayer insulating layer by sputtering. Further, the first aspect or the second aspect of the present invention.
In the method for manufacturing the stacked capacitor according to the aspect, the concave portion formed in the conductor layer is covered with the second mask layer, or the stack according to the third aspect or the fourth aspect of the present invention. In the method of manufacturing a capacitor, the conductive layer is etched to form a bottomed cylindrical lower electrode using the second mask layer as an etching mask, so that an acute angle portion is formed at the upper end of the lower electrode. There is no. In the stack capacitor of the present invention, since the mask material layer exists between the upper end of the lower electrode and the dielectric film, no acute angle portion is generated at the upper end of the lower electrode.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on an embodiment of the present invention (hereinafter abbreviated as an embodiment). Prior to that, a method for manufacturing a stacked capacitor according to the present invention will be described. (DR)
AM) and the stacked capacitor of the present invention will be described.

FIG. 1 is a schematic partial cross-sectional view of an example of a semiconductor device (DRAM) manufactured based on the method of manufacturing a stacked capacitor according to the present invention. The structure of this semiconductor device is the same as the structure of a conventional semiconductor device. This semiconductor device includes an MIS type semiconductor element (specifically, a MOSF) formed on a silicon semiconductor substrate 30 corresponding to a semiconductor layer.
ET). The MIS type semiconductor device includes a gate insulating film 32 formed on a surface of a silicon semiconductor substrate 30;
Gate electrode 33 formed on gate insulating film 32, source / drain regions 34A and 34B formed on silicon semiconductor substrate 30, source / drain regions 34A and 34B
And a channel forming region 35 located in a region of the silicon semiconductor substrate 30 sandwiched between the two. Note that each MIS type semiconductor element is isolated by an element isolation region 31. A lower insulating layer 40 is formed on the entire surface, and a bit line 42 is provided on the lower insulating layer 40. The bit line 42 is electrically connected to the other source / drain region 34B via the bit line contact plug 41. A node contact plug 43 is formed in the lower insulating layer 40 above one of the source / drain regions 34A. The node contact plug 43 forms an opening in the lower insulating layer 40 by using, for example, the super-resolution technique or the combination of the hard mask layer and the opening diameter reducing mask described above, and includes the inside of the opening. After forming a titanium layer and a TiN layer on the entire surface by a sputtering method, a tungsten layer is formed on the TiN layer by a CVD method. And a tungsten layer on the lower insulating layer 40;
It can be obtained by selectively removing a TiN layer, a titanium layer, and the like based on an etch-back method or a CMP method.
However, the method for forming the node contact plug 43 is not limited to this method. In the figure, the node contact plug 43 is represented by one layer.

On the lower insulating layer 40 including the bit line 42, an interlayer insulating layer 10 made of, for example, silicon oxide (SiO ₂ ) is formed. On the interlayer insulating layer 10, an etching stopper film 12 is formed. ing. The contact plug 11 is formed in the interlayer insulating layer 10 above the node contact plug 43. The contact plug 11 forms an opening in the etching stopper film 12 and the interlayer insulating layer 10 by using, for example, a super-resolution technique or a combination of the hard mask layer and the opening diameter reducing mask described above. Titanium layer, Ti
After forming the N layer by the sputtering method, CVD is performed on the TiN layer.
A tungsten layer is formed by a method. Then, it can be obtained by selectively removing the tungsten layer, the TiN layer, the titanium layer, and the like on the interlayer insulating layer 10 based on an etch-back method or a CMP method. However, contact plug 11
The method of forming is not limited to such a method. In the figure, the contact plug 11 is represented by one layer.

On the interlayer insulating layer 10, a stacked capacitor based on the manufacturing method of the present invention is formed. The stack capacitor having a cylindrical shape is composed of a lower electrode 1
8, an upper electrode 21, and a dielectric film 20 sandwiched between the lower electrode 18 and the upper electrode 21.
Is a contact plug 1 formed on an interlayer insulating layer 10.
1 and one source / drain region 34 via a node contact plug 43 formed in the lower insulating layer 40.
A is electrically connected.

FIG. 2 is a schematic partial cross-sectional view of a semiconductor device having a stack capacitor according to the present invention. The basic structure of the semiconductor device shown in FIG. 2 is the same as that of the semiconductor device shown in FIG. The semiconductor device shown in FIG. 2 differs from the semiconductor device shown in FIG. 1 in that a mask material layer 19 exists between the upper end of the lower electrode 18 and the dielectric film 20. As described above, the presence of the mask material layer 19 eliminates the formation of an acute angle portion at the upper end of the lower electrode 18, and can reduce the electric field concentration at the upper end of the lower electrode 18.

Embodiment 1 Embodiment 1 relates to a method for manufacturing a stacked capacitor according to the first aspect of the present invention. Hereinafter, a method of manufacturing the stacked capacitor according to the first embodiment will be described with reference to FIGS. 3 to 5 which are schematic partial end views of the interlayer insulating layer and the like.
Illustration of the MIS type semiconductor element and the like is omitted. In the first and second embodiments, the stack capacitor in the semiconductor device shown in FIG. 1 is manufactured.

[Step-100] After the bit line 42 is formed on the lower insulating layer 40, an interlayer insulating layer 10 made of silicon oxide (SiO ₂ ) is formed on the entire surface by the CVD method. Then, an etching stopper film 12 made of silicon nitride (SiN) is formed. Next, a contact plug 11 made of tungsten (W) or the like is formed.
After that, on the interlayer insulating layer 10 including the top surface of the contact plug 11 based on the sputtering method (more specifically, the etching stopper film 12 including the top surface of the contact plug 11 is formed).
Above), a conductor layer 13 made of ruthenium (Ru) is formed (see FIG. 3A). When the thickness of the conductor layer 13 is
Defines the height of the stack capacitor. When the contact plug 11 is made of polysilicon containing impurities and the conductor layer is made of a material other than polysilicon containing impurities, for example, TiN or the like may be used before the conductor layer 13 is formed. It is desirable to form a barrier layer made of TiON on the entire surface.

[Step-110] Next, a PSG layer is formed on the conductor layer 13 by a CVD method, and is patterned by patterning the PSG layer based on a lithography technique and a dry etching technique. One mask layer 14 is formed on the conductor layer 13. First
The planar shape of the opening provided in the mask layer 14 can be any desired shape such as a circle, an ellipse, a rectangle, and a rounded rectangle.

[Step-120] Thereafter, the conductive layer 13 above the contact plug 11 is etched using the first mask layer 14 as an etching mask, and the recess 15 in which the conductive layer 13 is left at the bottom is formed. Formed on the conductor layer 13. The shape of the concave portion 15 when the concave portion 15 is cut by a virtual plane extending in a direction perpendicular to the axis of the concave portion 15 can be any desired shape such as a circle, an ellipse, a rectangle, and a rounded rectangle.

[Step-130] Next, an NSG layer is deposited on the first mask layer 14 including the inside of the recess 15 by the CVD method, and the first mask layer 14 is etched by the etch-back method or the CMP method.
By removing the upper NSG layer, a second mask layer 16 made of NSG is formed in the concave portion 15 formed in the conductor layer 13 (see FIG. 4A).

[Step-140] Then, NSG and PSG
The first mask layer 14 made of PSG is removed using hydrofluoric acid or the like by utilizing the fact that there is an etching selectivity between the first mask layer 14 and the second mask layer 14. Next, an NSG layer is again deposited on the entire surface including the second mask layer 16 and the exposed conductor layer 13 by the CVD method, and by utilizing the fact that there is an etching selectivity between NSG and PSG, NSG is used. By etching back the layer, the second mask layer 16 protruding from the conductor layer 13 is formed.
A sidewall 17 made of NSG is formed on the side wall 16A (see FIG. 4B). The outer shape of the lower electrode is determined by the outer end portion 17A of the sidewall 17. Also, depending on the width of the sidewall 17 (the width of the sidewall 17 in a direction parallel to the top surface of the conductive layer 13),
The thickness of the upper end of the lower electrode is defined.

[Step-150] Next, sidewall 1
The conductor layer 13 is etched using the mask 7 and the second mask layer 16 as an etching mask (FIG. 4C).
reference). Thereby, a bottomed cylindrical lower electrode 18 made of the conductor layer 13 and connected to the contact plug 11 can be formed. The lower electrode 18 is in a state of being separated for each MIS type semiconductor element. After that, the sidewall 17 and the second mask layer 16 made of NSG are removed (see FIG. 5A). Etching stopper film 12
Is formed on the interlayer insulating layer 10, it is possible to reliably prevent the interlayer insulating layer 10 from being damaged when the sidewalls 17 and the second mask layer 16 are removed.

[Step-160] Thereafter, on the surface of the lower electrode 18, for example, a dielectric film 20 made of Ta ₂ O _{5 having} a thickness of about 10 nm or BST having a thickness of about 30 nm is formed by sputtering. Thereafter (see FIG. 5B), an upper electrode 21 (made of TiN) covering the dielectric film 20 is formed by CVD.
It is formed based on a method, a lithography technique, and a dry etching technique (see FIG. 5C). Thus, a stack capacitor having a cylindrical shape can be obtained.
The lower electrode 18 is provided for each MIS type semiconductor element, but the dielectric film 20 and the upper electrode 21 are shared by a plurality of MIS type semiconductor elements.

Embodiment 2 Embodiment 2 relates to a method for manufacturing a stacked capacitor according to the second aspect of the present invention. Hereinafter, a method of manufacturing the stacked capacitor according to the second embodiment will be described with reference to FIGS. 6 and 7 which are schematic partial end views of an interlayer insulating layer and the like.

[Step-200] First, silicon oxide (S
A conductive layer 13 made of ruthenium (Ru) is formed on the interlayer insulating layer 10 made of iO ₂ ) (more specifically, on the etching stopper film 12 including the top surface of the contact plug 11), and is formed from PSG. Forming a patterned first mask layer 114 on the conductor layer 13, and then etching the conductor layer 13 above the contact plug 11 using the first mask layer 114 as an etching mask; A recess 15 in which the conductive layer 13 is left at the bottom is formed in the conductive layer 13. Specifically, by performing the same steps as [Step-100] to [Step-120] in Embodiment 1, the structure shown in FIG. 6A can be obtained.

[Step-210] Thereafter, the first mask layer 114 made of PSG is isotropically etched using hydrofluoric acid or the like, and the side wall 114A of the first mask layer 114 on the conductor layer 13 is receded. (See FIG. 6B). The outline of the lower electrode is determined by the side wall 114A of the receded first mask layer 114. Also, the first mask layer 114
The thickness of the upper end of the lower electrode is defined by the amount of retreat.

[Step-220] Next, a region surrounded by the inside of the recess 15 formed in the conductor layer 13 and the side wall 114A of the first mask layer 114 on the conductor layer 13 (that is, the exposed region) A second mask layer 116 made of NSG is formed on the top surface of the conductor layer 13 (see FIG. 6C). Specifically, the conductive layer 1 in the concave portion 15 and the exposed conductive layer 1
3 on the first mask layer 14 including the top surface of
By depositing by the VD method and removing the NSG layer on the first mask layer 14 by the etch-back method or the CMP method, the second mask layer 116 made of NSG can be formed.

[Step-230] Then, NSG and PSG
The first mask layer 114 made of PSG on the conductor layer 13 is removed using hydrofluoric acid or the like by utilizing the fact that there is an etching selectivity between the first and second layers (see FIG. 7A).

[Step-240] Next, the second mask layer 1
16 as an etching mask, the conductive layer 13
Is etched (see FIG. 7B). Thereby, a bottomed cylindrical lower electrode 18 made of the conductor layer 13 and connected to the contact plug 11 can be formed. The lower electrode 18 is in a state of being separated for each MIS type semiconductor element. After that, the second mask layer 116 made of NSG is removed (see FIG. 7C). Since the etching stopper film 12 is formed on the interlayer insulating layer 10, when removing the second mask layer 116, the interlayer insulating layer 1
0 can be reliably prevented from occurring.

[Step-250] Thereafter, the same steps as [Step-160] of the first embodiment are performed to obtain a stack capacitor having a cylindrical shape similar to that shown in FIG. 5C. be able to.

Embodiment 3 Embodiment 3 relates to a method for manufacturing a stacked capacitor according to a third aspect of the present invention and a stacked capacitor of the present invention. Hereinafter, a method for manufacturing the stacked capacitor according to the third embodiment will be described with reference to FIGS. 8 to 10 which are schematic partial end views of the interlayer insulating layer and the like.

[Step-300] First, silicon oxide (S
After forming a conductor layer 13 made of ruthenium (Ru) on an interlayer insulating layer 10 made of iO ₂ ) (more specifically, on an etching stopper film 12 including a top surface of a contact plug 11), oxidation is performed. A first mask layer 214 made of silicon (SiO ₂ ) and patterned is formed on the conductor layer 13 (see FIG. 8A). The planar shape of the first mask layer 214 can be any desired shape, such as a circle, an ellipse, a rectangle, and a rounded rectangle.

[Step-310] Next, the first mask layer 2
A second mask layer 216 made of SiN is formed on the side wall 14 in a sidewall shape (see FIG. 8B). The second mask layer 216 can be formed by forming an SiN layer on the entire surface and then etching back the SiN layer. Sidewall-shaped second mask layer 2
The outer shape of the lower electrode is determined by the outer end 216A of the sixteen. Further, depending on the shape of the first mask layer 214,
The shape inside the bottomed cylindrical lower electrode is defined.

[Step-320] Then, using the first mask layer 214 and the second mask layer 216 as an etching mask, a part of the conductor layer 13 is
(See FIG. 9A). The thickness of the bottom of the bottomed cylindrical lower electrode formed later is defined by the amount of etching of the conductor layer 13 in the thickness direction.

[Step-330] Next, the first mask layer 2
14 (SiO ₂ ) and second mask layer 21
The first mask layer 214 is removed by utilizing the fact that there is an etching selectivity with the material (SiN) constituting 6 (see FIG. 9B).

[Step-340] Thereafter, the conductor layer 13 above the contact plug 11 is etched using the remaining second mask layer 216 as an etching mask, and the conductor layer 13 is formed. To form a bottomed cylindrical lower electrode 18 (see FIG. 9C). By optimizing the etching conditions, a mask material layer 19 composed of a part of the second mask layer 216 can be left at the upper end of the lower electrode 18.
The lower electrode 18 is in a state of being separated for each MIS type semiconductor element.

[Step-350] Then, by performing the same step as [Step-160] of the first embodiment, a stack capacitor having a cylindrical shape as shown in FIG. 10 or FIG. 2 can be obtained. In this stack capacitor, a mask material layer 19 exists between the upper end of the lower electrode 18 and the dielectric film 20.

(Fourth Embodiment) The fourth embodiment is a modification of the third embodiment. In the fourth embodiment, a plurality of patterned annular first mask layers are formed on the conductor layer, and then a second mask layer is formed on each side wall of the annular first mask layer. It is formed in a wall shape. As a result, a lower electrode having a multi-cylinder structure can be finally formed. Hereinafter, a method for manufacturing the stacked capacitor according to the fourth embodiment will be described with reference to FIGS. 11 to 13 which are schematic partial end views of the interlayer insulating layer and the like.

[Step-400] First, silicon oxide (S
After forming a conductor layer 13 made of ruthenium (Ru) on an interlayer insulating layer 10 made of iO ₂ ) (more specifically, on an etching stopper film 12 including a top surface of a contact plug 11), oxidation is performed. A first mask layer 214 made of silicon (SiO ₂ ) and patterned is formed on the conductor layer 13 (see FIG. 11A). The planar shape of the first mask layer 214 is annular (ring-shaped).
The external planar shape of the annular first mask layer 214 is circular,
Any desired shape, such as an ellipse, a rectangle, a rounded rectangle, etc., can be used. In the fourth embodiment, the single annular first mask layer 214 is used. However, multiple annular first mask layers 214 can be used as desired.

[Step-410] Next, a second mask layer 216 made of SiN is formed on the outermost side wall of the first annular mask layer 214 in a side wall shape.
An inner space (gap) in the first annular mask layer 214 is filled with a second mask layer 216 made of SiN (see FIG. 11B). Such a second mask layer 216
Can be formed by forming an SiN layer on the entire surface and then etching back the SiN layer. The outer edge of the sidewall-shaped second mask layer 216 determines the outer shape of the lower electrode. Also, the second mask layer 21
6 (second in a direction parallel to the top surface of the conductive layer 13).
The width of the mask layer 216) defines the cylindrical thickness of the lower electrode of the multi-cylinder structure.

[Step-420] Then, using the first mask layer 214 and the second mask layer 216 as an etching mask, a part of the conductor layer 13 is
(See FIG. 12A).
The thickness of the bottom of the bottom electrode of the cylindrical bottomed electrode having a multi-cylinder structure to be formed later is defined by the etching amount of the conductor layer 13 in the thickness direction.

[Step-430] Next, the first mask layer 2
14 (SiO ₂ ) and second mask layer 21
The first mask layer 214 is removed by utilizing the fact that there is an etching selectivity with the material (SiN) constituting 6 (see FIG. 12B).

[Step-440] Then, the conductor layer 13 above the contact plug 11 is etched using the remaining second mask layer 216 as an etching mask, and the conductor layer 13 is formed. Cylindrical bottom electrode 1 with a multi-cylinder structure connected to
8 (see FIG. 13). By optimizing the etching conditions, a mask material layer 19 composed of a part of the second mask layer 216 can be left at the upper end of the lower electrode 18. The lower electrode 18 is in a state of being separated for each MIS type semiconductor element.

[Step-450] Next, by executing the same step as [Step-160] of the first embodiment, a stacked capacitor having a multi-cylinder structure can be obtained. In this stack capacitor, a mask material layer 19 exists between the upper end of the lower electrode 18 and the dielectric film 20.

(Fifth Embodiment) A fifth embodiment is a modification of the fourth embodiment. In Embodiment 5, after forming the patterned first mask layer on the conductor layer,
Forming a second mask layer on the side wall of the first mask layer in a side wall shape, and further forming a first wall layer on the side wall of the second mask layer in a side wall shape; A side wall-shaped second mask layer is formed on a side wall of the wall-shaped first mask layer. Also by this, a lower electrode having a multi-cylinder structure can be finally formed. Hereinafter, a method for manufacturing the stacked capacitor of the fifth embodiment will be described with reference to FIGS. 14 to 16 which are schematic partial end views of the interlayer insulating layer and the like.

[Step-500] First, silicon oxide (S
After forming a conductor layer 13 made of ruthenium (Ru) on an interlayer insulating layer 10 made of iO ₂ ) (more specifically, on an etching stopper film 12 including a top surface of a contact plug 11), oxidation is performed. A first mask layer 214A made of silicon (SiO ₂ ) and patterned is formed on the conductor layer 13 (see FIG. 14A). The external planar shape of the first mask layer 214A can be any desired shape such as a circle, an ellipse, a rectangle, and a rounded rectangle.

[Step-510] Next, the first mask layer 2
14A, a second mask layer 216 made of SiN
A is formed in a sidewall shape, and a sidewall-shaped first mask layer 214B made of SiO ₂ is formed on the side wall of the sidewall-shaped second mask layer 216A. A sidewall-shaped second mask layer 216B made of SiN is formed on the side wall of the mask layer 214B (see FIG. 14B). Each of the sidewall-shaped mask layers has a SiO ₂ layer or an S
After forming the iN layer, it can be formed by etching back the SiO ₂ layer or the SiN layer.
In the drawings, the first mask layer is indicated by reference numeral 214 and the second mask layer is indicated by reference numeral 216 in some cases.

[Step-520] Then, using the first mask layer 214 and the second mask layer 216 as an etching mask, a part of the conductor layer 13 is removed.
(See FIG. 15A).
The thickness of the bottom of the bottom electrode of the cylindrical bottomed electrode having a multi-cylinder structure to be formed later is defined by the etching amount of the conductor layer 13 in the thickness direction.

[Step-530] Next, the first mask layer 2
14 (SiO ₂ ) and second mask layer 21
The first mask layer 214 is removed by utilizing the fact that there is an etching selectivity between the material (SiN) constituting the first mask layer 6 (see FIG. 15B).

[Step-540] Thereafter, the conductor layer 13 above the contact plug 11 is etched using the remaining second mask layer 216 as an etching mask, and the conductor layer 13 is formed. Cylindrical bottom electrode 1 with a multi-cylinder structure connected to
8 (see FIG. 16). By optimizing the etching conditions, a mask material layer 19 composed of a part of the second mask layer 216 can be left at the upper end of the lower electrode 18. The lower electrode 18 is in a state of being separated for each MIS type semiconductor element.

[Step-550] Then, by performing the same step as [Step-160] of the first embodiment, a stacked capacitor having a multi-cylinder structure can be obtained. In this stack capacitor, a mask material layer 19 exists between the upper end of the lower electrode 18 and the dielectric film 20.

(Embodiment 6) Embodiment 6 relates to a method for manufacturing a stacked capacitor according to the fourth aspect of the present invention. With the miniaturization of the stacked capacitor, for example, when the patterned first mask layer 214 is formed on the conductor layer 13 in [Step-300] of the third embodiment (see FIG. 8A) A phenomenon that the first mask layer 214 patterned in an island shape collapses may occur. By employing the method for manufacturing a stacked capacitor according to the sixth embodiment, the occurrence of such a phenomenon can be reliably prevented. Hereinafter, a method of manufacturing the stacked capacitor according to the sixth embodiment will be described with reference to FIGS. 17 to 19 which are schematic partial end views of the interlayer insulating layer and the like.

[Step-600] First, silicon oxide (S
After forming a conductor layer 13 made of ruthenium (Ru) on the interlayer insulating layer 10 made of iO ₂ ) (more specifically, on the etching stopper film 12 including the top surface of the contact plug 11), SOG Then, a patterned first mask layer 314 is formed on the conductor layer 13 (see FIG. 17A). The conductor layer 13 located below the concave portion 314A formed in the first mask layer 314 includes:
A lower electrode is formed in a later step. Recess 314A
Can be any desired shape such as a circle, an ellipse, a rectangle, and a rounded rectangle. Recess 314A
Of the lower electrode is determined by the side wall of the lower electrode.

[Step-610] Next, the first mask layer 3
A second mask layer 316 made of SiN is formed on the side wall of the fourteen concave portion 314A in a sidewall shape. The second mask layer 316 is formed by forming a SiN layer on the entire surface,
It can be formed by etching back the SiN layer. The outer end portion 316A of the sidewall-shaped second mask layer 316 defines the shape inside the lower electrode having a bottomed cylindrical shape.

[Step-620] Thereafter, a third mask layer 322 is formed on the exposed conductor layer 13 (FIG. 1).
7 (B)). Specifically, for example, after a silicon oxide (SiO ₂ ) layer is formed on the entire surface, the silicon oxide layer is polished by a CMP method, so that the concave portion 314A surrounded by the sidewall-shaped second mask layer 316 is formed.
The third mask layer 322 can be embedded therein.

[Step-630] Next, the material forming the first mask layer (SOG), the material forming the second mask layer (SiN), and the material forming the third mask layer (S
The structure shown in FIG. 18A can be obtained by removing the first mask layer 314 by utilizing the fact that there is an etching selectivity with respect to iO ₂ ). The second mask layer 3 is formed in the concave portion 314A formed in the first mask layer 314.
16. Since the third mask layer 322 is formed, a phenomenon such as collapse of the mask layer does not occur.

[Step-640] Then, using the second mask layer 314 and the third mask layer 322 as an etching mask, a part of the conductor layer 13 is removed.
After etching in the thickness direction (see FIG. 18B), the material (SiN) forming the second mask layer and the third
The third mask layer is removed by utilizing the fact that there is an etching selectivity between the material (SiO ₂ ) constituting the mask layer (see FIG. 19A). The thickness of the bottom of the bottomed cylindrical lower electrode formed later is defined by the amount of etching of the conductor layer 13 in the thickness direction.

[Step-650] Thereafter, the conductor layer 13 above the contact plug 11 is etched using the remaining second mask layer 316 as an etching mask, and the conductor layer 13 is formed of the conductor layer 13. To form a bottomed cylindrical lower electrode 18 connected to the substrate (see FIG. 19B). By optimizing the etching conditions, a mask material layer 19 composed of a part of the second mask layer 216 can be left at the upper end of the lower electrode 18.
The lower electrode 18 is in a state of being separated for each MIS type semiconductor element.

[Step-660] Then, by performing the same step as [Step-160] of the first embodiment, a stack capacitor having the same cylinder shape as that shown in FIG. 10 or FIG. 2 can be obtained. it can. In this stack capacitor, a mask material layer 19 exists between the upper end of the lower electrode 18 and the dielectric film 20.

(Embodiment 7) Embodiment 7 is a modification of Embodiment 6. In the seventh embodiment, after a patterned first mask layer is formed on a conductor layer, a second mask layer is formed in a side wall shape on a side wall of the first mask layer. Wall-shaped second
By forming a sidewall-shaped third mask layer on the side wall of the mask layer, and forming a sidewall-shaped second mask layer on the sidewall of the sidewall-shaped third mask layer, A lower electrode having a multi-cylinder structure is formed. Hereinafter, a method for manufacturing the stacked capacitor according to the sixth embodiment will be described with reference to FIG. 20 which is a schematic partial end view of an interlayer insulating layer and the like.

[Step-700] First, the same step as [Step-600] of the sixth embodiment is performed.

[Step-710] Next, the first mask layer 3
A second mask layer 316A made of SiN is formed in a side wall shape on the side wall of the fourteen concave portions 314A. Next, a sidewall-shaped third mask layer 322A made of SiO ₂ is formed on the sidewall of the sidewall-shaped second mask layer 316A, and SiN is deposited on the sidewall of the sidewall-shaped third mask layer 322A. A sidewall-shaped second mask layer 316B is formed, and a sidewall-shaped third mask layer 322B made of SiO ₂ is formed on the side wall of the sidewall-shaped second mask layer 316B (see FIG. 20). ). These sidewall-shaped mask layers are formed by forming a SiN layer or SiO ₂ layer on the entire surface,
It can be formed by etching back the SiN layer or the SiO ₂ layer.

[Step-720] Thereafter, by performing the same steps as [Step-620] to [Step-660] of the sixth embodiment, a stacked capacitor having a multi-cylinder structure can be obtained.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these embodiments. Structure of the semiconductor device described in the embodiment of the invention,
The materials, processing conditions, and the like used in the manufacture of the stacked capacitor are examples, and can be changed as appropriate. [Step-130] of Embodiment 1 and [Step-130] of Embodiment 2
220], the recess 15 is formed in the second mask layer 16,
116, the second mask layer 16, 1
The recess 16 may cover at least the side wall and the bottom of the recess 15 in the recess 15. In the third to seventh embodiments, the formation of the etching stopper film 12 is not necessary in some cases.

[0090]

According to the present invention, a conductor layer may be formed on a flat interlayer insulating layer by, for example, a sputtering method. Since there is no need to deposit the electrode material constituting the electrode, and it is not necessary to deposit the electrode material constituting the lower electrode by the CVD method, residual impurities due to the source material used in the CVD method are present in the lower electrode. There is no possibility of remaining, and there is no possibility of adversely affecting the characteristics of the stacked capacitor. Further, the conductive layer is etched in a state where the concave portion formed in the conductive layer is covered with the second mask layer or using the second mask layer as an etching mask, thereby forming a bottomed cylindrical lower electrode. Is formed, so that an acute angle portion does not occur at the upper end of the lower electrode,
There is no problem such as deterioration in characteristics and reliability of the stacked capacitor.

Further, the thermal budget in the manufacturing process of the stacked capacitor can be reduced,
The salicide technology and the dual gate technology have good compatibility with the manufacturing process of the stack capacitor, and the application to the DRAM integrated logic integrated circuit becomes easy.

In the stack capacitor of the present invention,
Since the mask material layer exists between the upper end of the lower electrode and the dielectric film, an acute angle portion does not occur at the upper end of the lower electrode, and the electric field concentration at the upper end of the lower electrode can be reduced. , Low leakage current and high yield can be achieved,
A stack capacitor having high reliability can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor device (DRAM) manufactured based on a method for manufacturing a stack capacitor according to the present invention.

FIG. 2 is a schematic partial cross-sectional view of a semiconductor device (DRAM) including a stack capacitor according to the present invention.

FIG. 3 is a schematic partial end view of an interlayer insulating layer and the like for describing a method of manufacturing the stacked capacitor according to the first embodiment of the present invention;

FIG. 4 is a schematic partial end view of an interlayer insulating layer and the like for explaining the method of manufacturing the stacked capacitor according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a schematic partial end view of an interlayer insulating layer and the like for explaining the method of manufacturing the stacked capacitor according to the first embodiment of the present invention, following FIG. 4;

FIG. 6 is a schematic partial end view of an interlayer insulating layer and the like for describing a method of manufacturing a stacked capacitor according to Embodiment 2 of the present invention;

FIG. 7 is a schematic partial end view of an interlayer insulating layer and the like for explaining the method of manufacturing the stacked capacitor according to the second embodiment of the present invention, following FIG. 6;

FIG. 8 is a schematic partial end view of an interlayer insulating layer and the like for describing a method for manufacturing a stacked capacitor according to Embodiment 3 of the present invention;

FIG. 9 is a schematic partial end view of an interlayer insulating layer and the like for explaining the method for manufacturing the stacked capacitor according to the third embodiment of the present invention, following FIG. 8;

FIG. 10 is a schematic partial end view of an interlayer insulating layer and the like for explaining the method for manufacturing the stacked capacitor according to the third embodiment of the present invention, following FIG. 9;

FIG. 11 is a schematic partial end view of an interlayer insulating layer and the like for describing a method of manufacturing a stacked capacitor according to Embodiment 4 of the present invention;

FIG. 12 is a schematic partial end view of an interlayer insulating layer and the like for explaining the method for manufacturing the stacked capacitor according to the fourth embodiment of the invention, following FIG. 8;

FIG. 13 is a schematic partial end view of the interlayer insulating layer and the like for illustrating the method of manufacturing the stacked capacitor according to the fourth embodiment of the invention, following FIG. 9;

FIG. 14 is a schematic partial end view of an interlayer insulating layer and the like for describing a method of manufacturing a stacked capacitor according to a fifth embodiment of the present invention.

FIG. 15 is a schematic partial end view of an interlayer insulating layer and the like for explaining the method of manufacturing the stacked capacitor according to the fifth embodiment of the present invention, following FIG. 14;

FIG. 16 is a schematic partial end view of an interlayer insulating layer and the like for explaining the method of manufacturing the stacked capacitor according to the fifth embodiment of the present invention, following FIG. 15;

FIG. 17 is a schematic partial end view of an interlayer insulating layer and the like for describing a method of manufacturing a stacked capacitor according to Embodiment 6 of the present invention;

FIG. 18 is a schematic partial end view of the interlayer insulating layer and the like for illustrating the method of manufacturing the stacked capacitor according to the sixth embodiment of the invention, following FIG. 17;

FIG. 19 is a schematic partial end view of the interlayer insulating layer and the like for illustrating the method for manufacturing the stacked capacitor according to the sixth embodiment of the invention, following FIG. 18;

FIG. 20 is a schematic partial end view of an interlayer insulating layer and the like for describing a method of manufacturing a stacked capacitor according to Embodiment 7 of the present invention;

FIG. 21 is a view for explaining a problem in a conventional method for manufacturing a stacked capacitor.

[Explanation of symbols]

10 ... interlayer insulating layer, 11 ... contact plug,
12 etching stopper film, 13 conductor layer, 14, 114, 214, 314 first mask layer, 15 recess, 16, 116, 216, 316
..Second mask layer, 17 ... side wall, 18
... lower electrode, 19 ... mask material layer, 20 ...
Dielectric film, 21 ... upper electrode, 314A ... recess,
322: third mask layer, 30: silicon semiconductor substrate, 31: element isolation region, 32: gate insulating film, 33: gate electrode, 34A, 34B: source / drain Region, 35 ... channel forming region, 4
0: Lower insulating layer, 41: Contact plug for bit line, 42: Bit line, 43: Contact plug for node

Claims (17)

[Claims] A lower electrode, an upper electrode, a dielectric film sandwiched between the lower electrode and the upper electrode, formed on an interlayer insulating layer covering the MIS type semiconductor element formed on the semiconductor layer; A method for manufacturing a stacked capacitor in which one source / drain region constituting a MIS type semiconductor element and a lower electrode are electrically connected via a contact plug formed in said interlayer insulating layer, comprising: Forming a conductive layer on the conductive layer; (b) forming a patterned first mask layer on the conductive layer; and (c) making contact using the first mask layer as an etching mask. Etch the conductor layer above the plug,
(E) forming a second mask layer in the recess formed in the conductor layer; (e) forming a second mask layer in the recess formed in the conductor layer; Removing the first mask layer above,
Forming a sidewall on the side wall of the second mask layer protruding from the conductor layer; and (f) etching the conductor layer using the sidewall and the second mask layer as an etching mask; Forming a bottomed cylindrical lower electrode connected to the contact plug and then removing the sidewall and the second mask layer; and (g) forming a dielectric film on the surface of the lower electrode. Forming an upper electrode covering the dielectric film. 2. The method according to claim 1, wherein the stack capacitor has a cylindrical shape. 3. The method according to claim 1, wherein an etching stopper film is formed between the interlayer insulating layer and the conductor layer prior to the step (a). 4. An etching selectivity exists between a material forming the first mask layer and a material forming the second mask layer, and forms a sidewall with the material forming the second mask layer. 2. The method according to claim 1, wherein the material has an etching selectivity. 5. A semiconductor device comprising: a lower electrode; an upper electrode; and a dielectric film sandwiched between the lower electrode and the upper electrode, formed on an interlayer insulating layer covering the MIS type semiconductor element formed on the semiconductor layer. A method for manufacturing a stacked capacitor in which one source / drain region constituting a MIS type semiconductor element and a lower electrode are electrically connected via a contact plug formed in said interlayer insulating layer, comprising: Forming a conductive layer on the conductive layer; (b) forming a patterned first mask layer on the conductive layer; and (c) making contact using the first mask layer as an etching mask. Etch the conductor layer above the plug,
Forming a recess in which the conductor layer is left at the bottom in the conductor layer, and then retreating the side wall of the first mask layer on the conductor layer; and (d) in the recess formed in the conductor layer and (E) forming a second mask layer on a region of the conductor layer surrounded by sidewalls of the first mask layer; (e) removing the first mask layer on the conductor layer; The conductor layer is etched by using the second mask layer as an etching mask to form a bottomed cylindrical lower electrode composed of the conductor layer and connected to the contact plug. (G) forming a dielectric film on the surface of the lower electrode, and then forming an upper electrode covering the dielectric film. 6. The method according to claim 5, wherein the stack capacitor has a cylindrical shape. 7. The method according to claim 5, wherein prior to the step (a), an etching stopper film is formed between the interlayer insulating layer and the conductor layer. 8. The method according to claim 5, wherein there is an etching selectivity between the material forming the first mask layer and the material forming the second mask layer. . 9. A semiconductor device comprising: a lower electrode; an upper electrode; a dielectric film sandwiched between the lower electrode and the upper electrode; formed on an interlayer insulating layer covering the MIS type semiconductor element formed on the semiconductor layer; A method for manufacturing a stacked capacitor in which one source / drain region constituting a MIS type semiconductor element and a lower electrode are electrically connected via a contact plug formed in said interlayer insulating layer, comprising: Forming a conductive layer on the conductive layer; (b) forming a patterned first mask layer on the conductive layer; and (c) forming a second mask on a side wall of the first mask layer. (D) forming a layer in a sidewall shape; (d) etching a part of the conductor layer using the first mask layer and the second mask layer as an etching mask; Remove mask layer And (f) etching the conductor layer above the contact plug using the remaining second mask layer as an etching mask to form a bottomed cylindrical member made of the conductor layer and connected to the contact plug. Forming a lower electrode, and (g) forming a dielectric film on the surface of the lower electrode, and then forming an upper electrode covering the dielectric film. 10. The method of claim 9, wherein the stacked capacitor has a cylindrical shape. 11. The method according to claim 9, wherein an etching stopper film is formed between the interlayer insulating layer and the conductor layer prior to the step (a). 12. The method according to claim 9, wherein there is an etching selectivity between a material forming the first mask layer and a material forming the second mask layer. . 13. A lower electrode, an upper electrode, and a dielectric film sandwiched between the lower electrode and the upper electrode, formed on an interlayer insulating layer covering the MIS type semiconductor element formed on the semiconductor layer; A method for manufacturing a stacked capacitor in which one source / drain region constituting a MIS type semiconductor element and a lower electrode are electrically connected via a contact plug formed in said interlayer insulating layer, comprising: Forming a conductive layer on the conductive layer; (b) forming a patterned first mask layer on the conductive layer; and (c) forming a second mask on a side wall of the first mask layer. (E) forming a third mask layer on the exposed conductor layer; (e) removing the first mask layer; ) Second mask layer and third mask Etching a portion of the conductor layer using the layer as an etching mask; (g) removing the third mask layer; and (h) using the remaining second mask layer as an etching mask. Forming a bottomed cylindrical lower electrode made of a conductive layer and connected to the contact plug by etching the conductive layer above the contact plug using: (i) a dielectric film on the surface of the lower electrode Forming a top electrode covering the dielectric film after the formation of the capacitor. 14. The method according to claim 13, wherein the stacked capacitor has a cylindrical shape. 15. The method according to claim 13, wherein an etching stopper film is formed between the interlayer insulating layer and the conductor layer prior to the step (A). 16. A method for forming a first mask layer, comprising the steps of:
There is an etching selectivity between the material forming the third mask layer and the material forming the third mask layer, and
14. The method according to claim 13, wherein there is an etching selectivity between the material forming the third mask layer and the material forming the third mask layer. 17. A semiconductor device comprising: a lower electrode; an upper electrode; a dielectric film sandwiched between the lower electrode and the upper electrode; formed on an interlayer insulating layer covering the MIS type semiconductor element formed on the semiconductor layer; A stack capacitor in which one of the source / drain regions constituting the MIS type semiconductor element is electrically connected to a lower electrode via a contact plug formed in the interlayer insulating layer, wherein the lower electrode has a bottomed cylindrical shape; A stack capacitor, wherein a mask material layer exists between the upper end of the lower electrode and the dielectric film.