JP2001186218A - Line test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system capable of specifying a circuit for diagnosing packages in a device and easily specifying a faulty package. SOLUTION: When a diagnostic bit is allocated to each package and passed through each package in a station device composed of a plurality of packages 1, 2,..., diagnostic information is added to the allocated bit and a checking circuit 100 checks the diagnostic bit to discriminate the package being the cause of failure. In a line test, the problem that a circuit scale becomes large or the like because a checking circuit has to be provided in each package to discriminate the faulty package can be dealt with by one checking circuit even when the number of packages is large by adding the diagnostic bit to each package. Thus a package is efficiently designed and the number of parts is reduced, then cost is reduced and the faulty package is easily specified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system and a system suitable for simplifying a circuit for diagnosing a package in an apparatus and for identifying a package in which a failure occurs.

[0002]

BACKGROUND OF THE INVENTION In a station device composed of a plurality of packages, a line test is an effective means for maintaining reliability and the like.

[0003] Conventionally, in order to identify a faulty package, a fault identification circuit must be provided in each package. For this reason, the diagnostic circuit in the apparatus becomes large and complicated, and it takes a very long time to perform debugging, and the number of design errors increases. Also, the large circuit size means that
This raises the problem of higher costs.

(B) In addition, in addition, in the conventional technique, a test pattern is transmitted and checked by a check circuit in a termination package. In this method, it is understood that a fault occurs in the device. Difficult to identify faulty packages.

(C) In order to identify a faulty package, a check circuit must be designed for each package, and the same check circuits are mounted by the number of packages. For this reason, the circuit scale of the entire device is
There was a problem that it became larger.

(D) Therefore, it is desirable to simplify a circuit for diagnosing a package in an apparatus and to identify a package that is in trouble. It is also desirable to be able to solve the problem that, in a line test, a check circuit must be provided for each package in order to identify a faulty package, thereby increasing the circuit size. In addition, the number of diagnostic check circuits becomes one, and the package design is made more efficient, the number of parts used is reduced, and the cost is reduced.

[0007] The present invention has been improved from such a point,
The disadvantages described above can be resolved, the circuit for diagnosing the package in the device is simplified, and the failure package can be easily specified.

[0008]

According to the present invention, the following line test system is provided. That is, according to the present invention, in a station device composed of a plurality of packages, a diagnostic bit is assigned to each package, and when passing through each package, diagnostic information is added to the assigned bits. Is checked to identify the package that has become an obstacle.

Further, in the common part of the station device, the data is looped back and the line part is checked.

[0010] The allocation bits of other packages are as follows:
The present invention is characterized in that the contents are passed through the own package, and the other package information makes it harder to receive a failure in the own package.

Further, the present invention is characterized in that the assigned bits are changed cyclically.

Further, the present invention is characterized in that the assigned bits are changed acyclically.

[0013]

According to the present invention, it is possible to simplify the circuit for diagnosing the package in the apparatus and to specify the obstructing package. According to the present invention, a diagnostic bit is added to each package in a line test, in order to identify a faulty package, a check circuit must be provided in each package, which increases the circuit scale. By doing so, even if the number of packages is large, the solution can be satisfactorily solved by the method of the present invention in which the number of check circuits is one. In a preferred example, even if there are a plurality of packages, if there is only one check circuit, faults in all packages can be detected. Therefore, according to the present invention, the number of diagnostic check circuits is reduced to one, the package design is made more efficient, the number of components used is reduced, and the cost is reduced, and the faulty package can be easily specified.

According to the present invention, furthermore, the data is returned in the common unit of the station device and the line unit is checked, so that even if another line unit is inserted / extracted, the system can be suitably implemented as a system in which the influence does not occur. Alternatively, the allocation bit of the other package can be suitably implemented as a method of passing through the inside of the own package and making the other package information less susceptible to a failure in the own package.

Also, it is possible to suitably implement the check circuit by simply changing the assigned bits cyclically, or to improve the reliability by changing the assigned bits acyclically. It can be suitably implemented.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. Referring to FIGS. 1 and 2, this is also a diagram showing the principle of the present invention, and includes a plurality of packages (the number of packages is generally one, two, three,...).
In a station device composed of a plurality of packages (1 to 5 packages in the illustrated example) in the case of n-1 or n, a diagnostic bit is assigned to each package and the signal passes through each package In this case, diagnostic information is added to the allocated bits, and as a result, as shown in the figure, the packages 1, 2,.
Have a basic configuration of circuits (1-1, 1-2), (2-1, 2-2),... For adding diagnostic information to bits allocated at the time of passing through each package. , (5
-1, 5-2). on the other hand,
Using such diagnostic information, the diagnostic bits are checked to identify the package in which a failure has occurred. For this purpose, a circuit 100 is provided as shown in the figure.

Here, the circuits 1-1, 1-2,..., 5-
1 is a diagnostic bit insertion circuit, circuits 1-2, 2-2,.
5-2 is a diagnostic bit generation circuit, and circuit 100 is a diagnostic bit check circuit.

Data is input from the first package 1 and sequentially transmitted to the fifth package 5 via the subsequent packages 2, 3, and 4, respectively. In this case, the package 1 has a diagnostic bit inserting circuit 1-1 and a diagnostic bit generating circuit 1-2, and the package 2 also has a diagnostic bit inserting circuit 2-1 and a diagnostic bit generating circuit 2-2. Packages 3 and 4, respectively
Similarly, a configuration having a diagnostic bit insertion circuit and a diagnostic bit generation circuit (for example, FIG.
4). Similarly, the package 5 can be configured to include the diagnostic bit insertion circuit 5-1 and the diagnostic bit generation circuit 5-2. However, here, the package 5 also includes the diagnostic bit check circuit 100. .

As shown in FIG. 1, in the package 1, information in the package is collected by a circuit 1-2 (diagnosis bit generation circuit) (diagnosis bit), and is collected by a circuit 1-1 (diagnosis bit insertion circuit). The time slot TS (n-
It is inserted at the 0th bit of 1) (FIG. 2). Also in the package 2, the information collected by the circuit 2-2 (diagnosis bit generation circuit) is transferred to the first bit of TS (n-1) on the highway by the circuit 2-1 (diagnosis bit insertion circuit). Insert (Fig. 2). Similarly, for packages 3, 4, and 5, the aggregated package information is aggregated into each package, and package 5
Circuit 100 (diagnosis bit check circuit) detects a diagnostic bit of each package and identifies a faulty package.

As described above, a plurality of packages 1
, A diagnostic bit is assigned to each of the packages 1, 2,..., And when passing through each of the packages 1, 2,. Information is added to the diagnostic bit check circuit 1
At 00, the diagnostic bit can be checked to identify the failing package. Therefore, in this method, even if there are a plurality of packages 1, 2,... (Here, the first to fifth packages), if one circuit 100 is provided, the failure of all the packages can be detected.

As described above, the method according to the present invention has a problem in that, in order to identify a faulty package in a line test, a check circuit must be provided in each package, so that the circuit scale becomes large. By adding a diagnostic bit to each of the packages 1, 2,..., Even if the number of packages 1, 2,.

Therefore, this method which can simplify the circuit for diagnosing the package in the apparatus and can identify the package which is in the trouble is considered at the beginning of the specification (a) to (d).
This is a good improvement from the viewpoint described in (d). If the test pattern is transmitted and checked by the check circuit in the terminal package, or if a fault identification circuit must be placed in each package to identify the faulty package, the former method will be used in the equipment. Although it is understood that the failure package is difficult, it is difficult to specify the failure package. In the latter case, in order to identify the faulty package, a check circuit must be designed in each package, and the same check circuits are mounted by the number of packages. For this reason, the diagnostic circuit in the apparatus becomes large and complicated, and it takes a very long time to perform debugging, and the number of design errors increases. Also, the large circuit size means that
The problem of higher costs will arise,
In this method, there is no such problem, and the method according to the present invention has one diagnostic check circuit, which has the effect of improving the efficiency of package design and reducing the number of parts used, such as cost reduction. It is easy to do.

FIGS. 3 and 4 are block diagrams of a line diagnostic system according to an embodiment of the present invention in which the basic principle is the same as that described above. Here, an example of four packages is used. The input of the package 1 and the output of the package 4 may be upstream (downstream) data. Hereinafter, the main parts will be described.

The package 1 includes a diagnostic bit insertion circuit 1-
1 and a diagnostic bit generation circuit 1-2. The package 2 also has a diagnostic bit insertion circuit 2-1 and a diagnostic bit generation circuit 2-2, and the package 3 also has a diagnostic bit insertion circuit 3-1 and a diagnostic bit generation circuit 3-2. The package 4 has a diagnostic bit insertion circuit 4-1 and a diagnostic bit generation circuit 4-2, and here also has a diagnostic bit check circuit 100.

In the package 1 shown in the figure, the bits generated in the circuit 1-2 are transmitted by the circuit 1-1 to the TS0 (for test) and TS1 as shown in the time chart of FIG.
(For communication), TS2 (for communication),..., Are inserted into the 0th bit (G0) of the test TS0. In the package 2, the bit generated in the circuit 2-2 is transferred to the circuit 2-1.
, Inserted into the first bit (G0) of TS0 (FIG. 4)
The diagnostic bits are inserted into the packages 3 and 4 similarly to the packages 1 and 2, and the diagnostic bits inserted in the packages 1 to 4 are checked by the circuit 100 placed in the package 4.

In this embodiment, there is an effect that all packages can be diagnosed if only one circuit 100 is used for diagnosing the packages 1 to 4. The same effect as described above can also be obtained with this line diagnosis system.

FIGS. 5 and 6 show another embodiment of the present invention.
This embodiment is also a modification of the above embodiment. The main parts will be described below. As shown in FIG.
Are diagnostic data insertion circuits 1-1 (1) to 4-1 (1) and diagnostic bit generation circuits 1-2 (1) to 4-2 (1), respectively, The diagnostic bit insertion circuits 1-1 (2) to 4-1 (2) and the diagnostic bit generation circuits 1-2 (2) to 4-2 (2)
It has two sets of diagnostic bit insertion circuits and diagnostic bit generation circuits.

The package 4 shown in FIG. 5 has a configuration in which the package 4 shown in FIG. 3 includes the diagnostic bit check circuit 100, whereas the package 4 shown in FIG.
00 is provided. Diagnostic bit check circuit 1
00 is a second set of diagnostic bit insertion circuits 1-1 (2) and diagnostic bit generation circuits 1-2 (2) on the package 1 side.
(Upstream data) side.

The present invention can be configured and implemented as described above. The difference from the case of FIGS.
(Turnback circuit), the highway is turned back at the end of the device, and the input / output of the device can be diagnosed by one circuit 100 (diagnosis bit check circuit). In addition to providing the same operational effects as described above, there is such an effect.

FIGS. 7 and 8 show still another embodiment of the present invention. This embodiment can be considered as a modification of the above-described embodiment (FIGS. 5 and 6), and three packages are shown as an example. Hereinafter, the main parts will be described.

In FIG. 7, 1-1 (1) to 3-1 (1), 1
-2 (1) to 3-2 (1), 1-1 (2) to 3-1
(2) and 1-2 (2) to 3-2 (3) are the same as those in the above-described embodiment, which are included in the packages 1 to 3 respectively.
A set of diagnostic bit insertion circuits and a diagnostic bit generation circuit. In this embodiment, the diagnostic bit check circuit has a configuration in which a circuit 101 and a circuit 102 are provided.
The diagnostic bit check circuit 101 is provided on the system (downstream data) side of the diagnostic bit insertion circuit 3-1 (1) and the diagnostic bit generation circuit 3-2 (1) of the package 3, and
The diagnostic bit check circuit 102 can be provided on the system (uplink data) side of the diagnostic bit insertion circuit 1-1 (2) and the diagnostic bit generation circuit 1-2 (2) of the package 1.

The present embodiment differs from the configuration of FIG. 5 in that the point of the turn of the highway is turned not at the end of the device but at a common part (package 2 in the illustrated example), so that the package is This has the effect of preventing other packages from being affected during maintenance or package insertion / removal. Therefore, in addition to providing the same operation and effect as described above, there is such an effect. The present invention
It can also be implemented in this way.

FIGS. 9 and 10 show still another embodiment of the present invention. In the following, a description will be given of the main part. Compared with the case of the configuration according to each of the above-described embodiments, for example, in the case of the package 1, input data to the diagnostic bit insertion circuit 1-1 (uplink (downlink)) ) Data) as one input and an output obtained from the internal circuit 1-10 of the package 1 connected to the circuit 1-1 as the other input. These may be the same for the packages 2 and 3. The illustrated example shows an example in which three packages are provided, and the package 3 has the diagnostic bit check circuit 100.

This embodiment differs from FIGS. 1 to 8 in that
A circuit (diagnosis bit insertion circuit) 1-11 can be added to transmit a time slot of a diagnosis bit to the package 2 without passing through the internal circuit 1-10. As a result, even if the package 1 fails, the diagnostic bit can be inserted into the subsequent packages without being affected by the package 1, and the circuit of the package 3 (diagnosis bit check circuit)
At 100, there is an effect that the diagnosis in the apparatus can be performed correctly. Therefore, in addition to providing the same operation and effect as described above, there is such an effect. The present invention
You may implement in this way.

The present invention is not limited to the above embodiment, but can be variously modified and changed. For example, FIGS.
(Including the case of the principle configuration of FIGS. 1 and 2), by changing the diagnostic allocation bit cyclically,
It is possible to provide a more reliable function by simplifying the check circuit, changing the diagnostic allocation bit acyclically (for example, setting it to "L" once every 1 ms). Therefore, the present invention can be implemented as a line test method in which the check circuit is simplified by changing the cyclic value in such a manner, and the assigned bits are changed in an acyclic manner to improve the reliability. It can also be implemented as an enhanced line test scheme.

The contents described in the above embodiments can be regarded as the following inventions.

[Appendix 1] In a station device composed of a plurality of packages, a diagnostic bit is assigned to each package, and when passing through each package, diagnostic information is added to the assigned bits. A line test method or a line diagnostic method or system, wherein a diagnostic bit is checked to identify a faulty package.

[Appendix 2] In the common part of the station device,
A line test method or a line diagnosis method or system that does not affect the insertion and removal of other line parts by checking the loopback part of the data.

[Appendix 3] A line test method or a line diagnosis method or system in which bits allocated to another package are passed through the own package and failures in the own package are hardly caused by other package information.

[Additional Item 4] A line test system or a line diagnostic system or system in which allocation bits are changed cyclically to simplify a check circuit.

[Supplementary Note 5] A line test method or a line diagnostic method or system in which the allocation bits are changed acyclically (for example, set to “L” once every 1 ms) to improve reliability.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention and is also used for explaining the principle of a plurality of packages, a diagnostic bit insertion circuit, a diagnostic bit generation circuit, and a diagnostic bit check circuit in each package.

FIG. 2 is a time chart for explaining the same example.

FIG. 3 shows another embodiment of the present invention, and is a diagram showing a plurality of packages, a diagnostic bit insertion circuit, a diagnostic bit generation circuit, and a diagnostic bit check circuit, respectively.

FIG. 4 is a time chart for explaining the same example.

FIG. 5 shows still another embodiment of the present invention, which is also a modification of FIG. 3, and includes a plurality of packages, a diagnostic bit insertion circuit and a diagnostic bit generation circuit, a folding circuit, and a diagnostic bit check circuit. FIG.

FIG. 6 is a time chart for explaining the same example.

FIG. 7 shows still another embodiment of the present invention, which is also a modification of FIG. 5, and shows a plurality of packages, a diagnostic bit insertion circuit, a diagnostic bit generation circuit, and a diagnostic bit check circuit, respectively. is there.

FIG. 8 is a time chart for explaining the same example.

FIG. 9 shows still another embodiment of the present invention, and is a diagram showing a package, a diagnostic bit insertion circuit, a diagnostic bit generation circuit and an internal circuit, and a diagnostic bit check circuit, respectively.

FIG. 10 is a time chart for explaining the same example.

[Explanation of symbols]

1,2,3,4,5 Package 1-1,2-1,3-1,4-1,5-1 Diagnostic Bit Insertion Circuit 1-1 (1), 2-1 (1), 3-1 (1), 4-1
(1) Diagnostic bit insertion circuit 1-1 (2), 2-1 (2), 3-1 (2), 4-1
(2) Diagnostic bit insertion circuit 1-2, 2-2, 3-2, 4-2, 5-2 diagnostic bit generation circuit 1-2 (1), 2-2 (1), 3-2 (1) , 4-2
(1) Diagnosis bit generation circuit 1-2 (2), 2-2 (2), 3-2 (2), 4-2
(2) Diagnostic bit generation circuit 1-10 to 3-10 Internal circuit 1-11 to 3-11 Diagnostic bit insertion circuit 100, 101, 102 Diagnostic bit check circuit 200 Loopback circuit

Claims (5)

[Claims] In a station device composed of a plurality of packages, a diagnostic bit is assigned to each package, and when passing through each package, diagnostic information is added to the assigned bits, and the diagnostic bit is added to a check circuit. A line test method characterized by checking and identifying the package that is in trouble. 2. The line test system according to claim 1, wherein the common unit of the station device performs a loopback line check on the data. 3. The circuit test method according to claim 1, wherein the allocation bits of the other package are passed through the own package, and the other package information makes it difficult to receive a failure in the own package. 4. The circuit test method according to claim 1, wherein the assigned bits are changed cyclically. 5. The circuit test method according to claim 1, wherein the assigned bits are changed acyclically.